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authorJosé Fonseca <jfonseca@vmware.com>2010-03-06 09:45:05 +0000
committerJosé Fonseca <jfonseca@vmware.com>2010-03-06 09:45:05 +0000
commit89258652b6a1d282bed14549907892bdfda752f0 (patch)
tree843c6b16d9d149f2c763cc26447dcb3a8aa17a7b /src
parent44703217f73095c4946e06057e399e447b252576 (diff)
gallivm: Answer question/comment.
Diffstat (limited to 'src')
-rw-r--r--src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
index 84d03a145f7..28ff362cac4 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
@@ -586,6 +586,17 @@ emit_instruction(
if (indirect_temp_reference(inst))
return FALSE;
+ /*
+ * Stores and write masks are handled in a general fashion after the long
+ * instruction opcode switch statement.
+ *
+ * Although not stricitly necessary, we avoid generating instructions for
+ * channels which won't be stored, in cases where's that easy. For some
+ * complex instructions, like texture sampling, it is more convenient to
+ * assume a full writemask and then let LLVM optimization passes eliminate
+ * redundant code.
+ */
+
assert(info->num_dst <= 1);
if(info->num_dst) {
FOR_EACH_DST0_ENABLED_CHANNEL( inst, chan_index ) {
@@ -1131,7 +1142,6 @@ emit_instruction(
break;
case TGSI_OPCODE_TEX:
- /* XXX what about dst0 writemask? */
emit_tex( bld, inst, FALSE, FALSE, dst0 );
break;