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authorMarek Olšák <marek.olsak@amd.com>2014-07-26 17:15:39 +0200
committerCarl Worth <cworth@cworth.org>2014-07-30 22:09:45 -0700
commit71102219ea97aaee0c6d8076d26857581340535d (patch)
treea5f05c63b1e0e14f06cb1ad00b5b010d18815e1d /src
parentd26ac40bada800cce24ed7c988fbc31dff89681d (diff)
r600g,radeonsi: switch all occurences of array_size to util_max_layer
This fixes 3D texture support in all these cases, because array_size is 1 with 3D textures and depth0 actually contains the "array size". util_max_layer is universal and returns the last layer index for any texture target. A lot of the cases below can't actually be hit with 3D textures, but let's be consistent. This fixes a failure in: piglit layered-rendering/clear-color-all-types 3d single_level for r600g and radeonsi, which was caused by an incorrect CMASK size calculation. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> (cherry picked from commit a9528cef6b6ff4875c9d125a60b7309a2ad24766)
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/r600/r600_blit.c5
-rw-r--r--src/gallium/drivers/radeon/r600_texture.c9
-rw-r--r--src/gallium/drivers/radeonsi/si_blit.c2
3 files changed, 10 insertions, 6 deletions
diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c
index bbc64ac79a2..6fab57caaa1 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -430,7 +430,8 @@ static void r600_clear(struct pipe_context *ctx, unsigned buffers,
* disable fast clear for texture array.
*/
/* Only use htile for first level */
- if (rtex->htile_buffer && !level && rtex->surface.array_size == 1) {
+ if (rtex->htile_buffer && !level &&
+ util_max_layer(&rtex->resource.b.b, level) == 0) {
if (rtex->depth_clear_value != depth) {
rtex->depth_clear_value = depth;
rctx->db_state.atom.dirty = true;
@@ -837,7 +838,7 @@ static void r600_flush_resource(struct pipe_context *ctx,
if (!rtex->is_depth && rtex->cmask.size) {
r600_blit_decompress_color(ctx, rtex, 0, res->last_level,
- 0, res->array_size - 1);
+ 0, util_max_layer(res, 0));
}
}
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 519f0991fc5..0e5956836bb 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -380,7 +380,8 @@ void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
out->alignment = MAX2(256, base_align);
- out->size = rtex->surface.array_size * align(slice_bytes, base_align);
+ out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
+ align(slice_bytes, base_align);
}
static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
@@ -427,7 +428,8 @@ static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
out->slice_tile_max -= 1;
out->alignment = MAX2(256, base_align);
- out->size = rtex->surface.array_size * align(slice_bytes, base_align);
+ out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
+ align(slice_bytes, base_align);
}
static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
@@ -523,7 +525,8 @@ static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen,
pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
base_align = num_pipes * pipe_interleave_bytes;
- return rtex->surface.array_size * align(slice_bytes, base_align);
+ return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
+ align(slice_bytes, base_align);
}
static unsigned r600_texture_htile_alloc_size(struct r600_common_screen *rscreen,
diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index 1dfff49d102..ea1065480d8 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -735,7 +735,7 @@ static void si_flush_resource(struct pipe_context *ctx,
if (!rtex->is_depth && rtex->cmask.size) {
si_blit_decompress_color(ctx, rtex, 0, res->last_level,
- 0, res->array_size - 1);
+ 0, util_max_layer(res, 0));
}
}