diff options
| author | Kenneth Graunke <kenneth@whitecape.org> | 2013-07-11 10:24:15 -0700 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2013-07-18 16:57:21 -0700 |
| commit | 7ce5c6b2147f9af524f4073b6ee3b29c0a5a1522 (patch) | |
| tree | e97358dbc8cb24baa1fdb2e29feb2e70d6e79274 /src/mesa | |
| parent | 30f33deccb7d481f638e34f2d9d9c107df871eab (diff) | |
i965: Combine URB code emission into a single group.
All four URB packets need to be programmed together in order for the GPU
state to be valid. Putting them in separate BEGIN..ADVANCE blocks is
risky: if we're nearing the end of a batch, the batch could be flushed
inbetween two of the commands, causing the URB programming to be split
into two batchbuffers.
This -might- be okay with hardware contexts, but it offers no advantages
over keeping them together, and has a potential for hangs.
Putting them into a single BEGIN..ADVANCE block ensures they'll be kept
in the same batch, which seems wise.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_urb.c | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c index ce01ddab66a..350f644dfcd 100644 --- a/src/mesa/drivers/dri/i965/gen7_urb.c +++ b/src/mesa/drivers/dri/i965/gen7_urb.c @@ -60,12 +60,10 @@ gen7_allocate_push_constants(struct brw_context *brw) if (brw->is_haswell && brw->gt == 3) size = 16; - BEGIN_BATCH(2); + BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_VS << 16 | (2 - 2)); OUT_BATCH(size); - ADVANCE_BATCH(); - BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_PS << 16 | (2 - 2)); OUT_BATCH(size | size << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT); ADVANCE_BATCH(); @@ -105,27 +103,21 @@ void gen7_emit_urb_state(struct brw_context *brw, GLuint nr_vs_entries, GLuint vs_size, GLuint vs_start) { - BEGIN_BATCH(2); + BEGIN_BATCH(8); OUT_BATCH(_3DSTATE_URB_VS << 16 | (2 - 2)); OUT_BATCH(nr_vs_entries | ((vs_size - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) | (vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT)); - ADVANCE_BATCH(); /* Allocate the GS, HS, and DS zero space - we don't use them. */ - BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_URB_GS << 16 | (2 - 2)); OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) | (vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT)); - ADVANCE_BATCH(); - BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_URB_HS << 16 | (2 - 2)); OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) | (vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT)); - ADVANCE_BATCH(); - BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_URB_DS << 16 | (2 - 2)); OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) | (vs_start << GEN7_URB_STARTING_ADDRESS_SHIFT)); |