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authorChad Versace <chad.versace@linux.intel.com>2013-07-18 10:00:15 -0700
committerChad Versace <chad.versace@linux.intel.com>2013-07-18 16:18:21 -0700
commit2f346395f5109c0fc4db86de3d2754001ddf0bb9 (patch)
treeb1fd4aa3f2a41f0492eba26f57a0ec55c1a5ac7a /src/mesa
parenta16d47465ecdbaef0548207c1bc037493a67ebec (diff)
i965/hsw: Change L3 MOCS of SURFACE_STAT
Change from "not cacheable" to "cacheable" in L3. Do so for the draw upload path and blorp. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/gen7_blorp.cpp4
-rw-r--r--src/mesa/drivers/dri/i965/gen7_wm_surface_state.c6
2 files changed, 8 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index fbdd2bee705..0c08584baea 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -143,6 +143,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
*/
struct intel_region *region = surface->mt->region;
uint32_t tile_x, tile_y;
+ uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
uint32_t tiling = surface->map_stencil_as_y_tiled
? I915_TILING_Y : region->tiling;
@@ -175,7 +176,8 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
assert(tile_x % 4 == 0);
assert(tile_y % 2 == 0);
surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
- SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET);
+ SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET) |
+ SET_FIELD(mocs, GEN7_SURFACE_MOCS);
surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index fe9780387b7..34cf63b0754 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -286,6 +286,7 @@ gen7_update_texture_surface(struct gl_context *ctx,
struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
uint32_t tile_x, tile_y;
+ uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
if (tObj->Target == GL_TEXTURE_BUFFER) {
gen7_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
@@ -334,6 +335,7 @@ gen7_update_texture_surface(struct gl_context *ctx,
*/
surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
(tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
+ SET_FIELD(mocs, GEN7_SURFACE_MOCS) |
/* mip count */
(intelObj->_MaxLevel - tObj->BaseLevel));
@@ -512,6 +514,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
bool is_array = false;
int depth = MAX2(rb->Depth, 1);
int min_array_element;
+ uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0;
GLenum gl_target = rb->TexImage ?
rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
@@ -571,7 +574,8 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
assert(brw->has_surface_tile_offset);
- surf[5] = irb->mt_level - irb->mt->first_level;
+ surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS) |
+ (irb->mt_level - irb->mt->first_level);
surf[2] = SET_FIELD(irb->mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
SET_FIELD(irb->mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);