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authorChad Versace <chad.versace@linux.intel.com>2013-11-26 17:04:24 -0800
committerIan Romanick <ian.d.romanick@intel.com>2013-12-06 08:08:09 -0800
commitedca52e6e7169f490b8c1ee4c6103d97c0409f3c (patch)
tree36f6dd67f4e7a6fd79aa6249e85c627e7e3c8113 /src/mesa
parent2457b5bfa48096dde63cb5a14d9db94bccc6767d (diff)
i965/hsw: Apply non-msrt fast color clear w/a to all HSW GTs
Pre-patch, the workaround was applied to only HSW GT3. However, the workaround also fixes render corruption on the HSW GT1 Chromebook, codenamed Falco. Also, update the BSpec quote that discusses the workaround to reflect the latest BSpec. The BSpec states that the workaround is required for Ivybridge and Baytrail as well as Haswell. But, we apply the workaround to only Haswell because (a) we suspect that is the only hardware where it is actually required and (b) we haven't yet validated the workaround for the other hardware. CC: "9.2, 10.0" <mesa-stable@lists.freedesktop.org> CC: Anuj Phogat <anuj.phogat@gmail.com> OTC-Tracker: CHRMOS-812 Reviewed-by: Paul Berry <stereotype441@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Chad Versace <chad.versace@linux.intel.com> (cherry picked from commit 8b659cef3a244b1acdbbca0beb704a66b6bc2fbc)
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp_clear.cpp18
1 files changed, 12 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 02ec2737ac3..3f096b513fa 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -265,13 +265,19 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct brw_context *brw,
x_align *= 16;
y_align *= 32;
- if (brw->is_haswell && brw->gt == 3) {
+ if (brw->is_haswell) {
/* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
- * Backend > MCS Buffer for Render Target(s) [DevIVB+]:
- * [DevHSW:GT3]: Clear rectangle must be aligned to two times the
- * number of pixels in the table shown below...
- * x_align, y_align values computed above are the relevant entries
- * in the referred table.
+ * Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
+ * Clear of Non-MultiSampled Render Target Restrictions":
+ *
+ * [IVB, VLVT, HSW]: Clear rectangle must be aligned to two times
+ * the number of pixels in the table shown below... x_align,
+ * y_align values computed above are the relevant entries in the
+ * referred table.
+ *
+ * We apply the workaround to only Haswell because (a) we suspect that
+ * is the only hardware where it is actually required and (b) we
+ * haven't yet validated the workaround for the other hardware.
*/
x0 = ROUND_DOWN_TO(x0, 2 * x_align);
y0 = ROUND_DOWN_TO(y0, 2 * y_align);