diff options
| author | Kenneth Graunke <kenneth@whitecape.org> | 2014-05-20 14:52:39 -0700 |
|---|---|---|
| committer | Ian Romanick <ian.d.romanick@intel.com> | 2014-05-23 09:54:15 -0700 |
| commit | d2521a44af66af5c99090eb30487798f8b6dde1c (patch) | |
| tree | 867cb6f87013068e65231ca812a930c456f55484 /src/mesa | |
| parent | 00f2dcb791bf108669d4d3c809613f81510bf8ba (diff) | |
i965: Use WE_all for FB write header setup on Broadwell.
I forgot to disable writemasking on the OR and MOV which set the render
target index and "source 0 alpha present to render target" bit.
Using get_element_ud is equivalent and avoids a line-wrap.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 7d3985ca6cdd5f2f7ff68b269798d69394164dec)
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen8_fs_generator.cpp | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp index de06a97b2ec..26cb991a316 100644 --- a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp @@ -73,16 +73,17 @@ gen8_fs_generator::generate_fb_write(fs_inst *ir) if (ir->target > 0 && c->key.replicate_alpha) { /* Set "Source0 Alpha Present to RenderTarget" bit in the header. */ - OR(vec1(retype(brw_message_reg(ir->base_mrf), BRW_REGISTER_TYPE_UD)), - vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)), - brw_imm_ud(1 << 11)); + gen8_instruction *inst = + OR(get_element_ud(brw_message_reg(ir->base_mrf), 0), + vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)), + brw_imm_ud(1 << 11)); + gen8_set_mask_control(inst, BRW_MASK_DISABLE); } if (ir->target > 0) { /* Set the render target index for choosing BLEND_STATE. */ - MOV(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, ir->base_mrf, 2), - BRW_REGISTER_TYPE_UD), - brw_imm_ud(ir->target)); + MOV_RAW(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, ir->base_mrf, 2), + brw_imm_ud(ir->target)); } } |