diff options
| author | Dylan Baker <dylan.c.baker@intel.com> | 2021-04-09 09:49:49 -0700 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2021-12-03 23:53:06 +0000 |
| commit | 184a690fca700aa9ef2ae2e58b0f4bd86562aa6d (patch) | |
| tree | 0e420f4877711d8b7008890f52b9c3625a84e14d /src/mesa/drivers | |
| parent | 4d45b280bf9a1c804cea5de4d15c317b6bdebfc5 (diff) | |
classic/r200: Delete driver
This will now only be available on the Amber branch
Reviewed-by: Emma Anholt <emma@anholt.net>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10153>
Diffstat (limited to 'src/mesa/drivers')
58 files changed, 0 insertions, 15400 deletions
diff --git a/src/mesa/drivers/dri/meson.build b/src/mesa/drivers/dri/meson.build index b772dc2dca6..7eb010dc57b 100644 --- a/src/mesa/drivers/dri/meson.build +++ b/src/mesa/drivers/dri/meson.build @@ -33,11 +33,6 @@ if with_dri_i965 _dri_drivers += libi965 _dri_link += 'i965_dri.so' endif -if with_dri_r200 - subdir('r200') - _dri_drivers += libr200 - _dri_link += 'r200_dri.so' -endif if with_dri_nouveau subdir('nouveau') _dri_drivers += libnouveau_vieux diff --git a/src/mesa/drivers/dri/r200/meson.build b/src/mesa/drivers/dri/r200/meson.build deleted file mode 100644 index 6dfad43cd6a..00000000000 --- a/src/mesa/drivers/dri/r200/meson.build +++ /dev/null @@ -1,88 +0,0 @@ -# Copyright © 2017 Intel Corporation - -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), to deal -# in the Software without restriction, including without limitation the rights -# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -# copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: - -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. - -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -# SOFTWARE. - -files_r200 = files( - 'radeon_buffer_objects.c', - 'radeon_buffer_objects.h', - 'radeon_cmdbuf.h', - 'radeon_common.c', - 'radeon_common.h', - 'radeon_common_context.c', - 'radeon_common_context.h', - 'radeon_debug.c', - 'radeon_debug.h', - 'radeon_dma.c', - 'radeon_dma.h', - 'radeon_fbo.c', - 'radeon_fog.c', - 'radeon_fog.h', - 'radeon_mipmap_tree.c', - 'radeon_mipmap_tree.h', - 'radeon_pixel_read.c', - 'radeon_queryobj.c', - 'radeon_queryobj.h', - 'radeon_span.c', - 'radeon_span.h', - 'radeon_tex_copy.c', - 'radeon_texture.c', - 'radeon_texture.h', - 'radeon_tile.c', - 'radeon_tile.h', - 'r200_blit.c', - 'r200_blit.h', - 'r200_cmdbuf.c', - 'r200_context.c', - 'r200_context.h', - 'r200_fragshader.c', - 'r200_ioctl.c', - 'r200_ioctl.h', - 'r200_maos.c', - 'r200_maos.h', - 'r200_reg.h', - 'r200_sanity.c', - 'r200_sanity.h', - 'r200_state.c', - 'r200_state.h', - 'r200_state_init.c', - 'r200_swtcl.c', - 'r200_swtcl.h', - 'r200_tcl.c', - 'r200_tcl.h', - 'r200_tex.c', - 'r200_tex.h', - 'r200_texstate.c', - 'r200_vertprog.c', - 'r200_vertprog.h', - 'radeon_chipset.h', - 'radeon_screen.c', - 'radeon_screen.h', - 'server/radeon_reg.h', -) - -libr200 = static_library( - 'r200', - files_r200, - include_directories : [ - inc_include, inc_src, inc_mapi, inc_mesa, inc_gallium, inc_gallium_aux, inc_dri_common, inc_util, include_directories('server'), - ], - c_args : ['-DRADEON_R200'], - gnu_symbol_visibility : 'hidden', - dependencies : [dep_libdrm, dep_libdrm_radeon, idep_mesautil], -) diff --git a/src/mesa/drivers/dri/r200/r200_blit.c b/src/mesa/drivers/dri/r200/r200_blit.c deleted file mode 100644 index 5c4f8170a3c..00000000000 --- a/src/mesa/drivers/dri/r200/r200_blit.c +++ /dev/null @@ -1,576 +0,0 @@ -/* - * Copyright (C) 2009 Maciej Cencora <m.cencora@gmail.com> - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "radeon_common.h" -#include "r200_context.h" -#include "r200_blit.h" -#include "r200_tex.h" - -static inline uint32_t cmdpacket0(struct radeon_screen *rscrn, - int reg, int count) -{ - if (count) - return CP_PACKET0(reg, count - 1); - return CP_PACKET2; -} - -/* common formats supported as both textures and render targets */ -unsigned r200_check_blit(mesa_format mesa_format, uint32_t dst_pitch) -{ - /* XXX others? */ - switch (mesa_format) { -#if UTIL_ARCH_LITTLE_ENDIAN - case MESA_FORMAT_B8G8R8A8_UNORM: - case MESA_FORMAT_B8G8R8X8_UNORM: - case MESA_FORMAT_B5G6R5_UNORM: - case MESA_FORMAT_B4G4R4A4_UNORM: - case MESA_FORMAT_B5G5R5A1_UNORM: -#else - case MESA_FORMAT_A8R8G8B8_UNORM: - case MESA_FORMAT_X8R8G8B8_UNORM: - case MESA_FORMAT_R5G6B5_UNORM: - case MESA_FORMAT_A4R4G4B4_UNORM: - case MESA_FORMAT_A1R5G5B5_UNORM: -#endif - case MESA_FORMAT_A_UNORM8: - case MESA_FORMAT_L_UNORM8: - case MESA_FORMAT_I_UNORM8: - /* swizzled - probably can't happen with the disabled Choose8888TexFormat code */ - case MESA_FORMAT_A8B8G8R8_UNORM: - case MESA_FORMAT_R8G8B8A8_UNORM: - break; - default: - return 0; - } - - /* Rendering to small buffer doesn't work. - * Looks like a hw limitation. - */ - if (dst_pitch < 32) - return 0; - - /* ??? */ - if (_mesa_get_format_bits(mesa_format, GL_DEPTH_BITS) > 0) - return 0; - - return 1; -} - -static inline void emit_vtx_state(struct r200_context *r200) -{ - BATCH_LOCALS(&r200->radeon); - - BEGIN_BATCH(14); - if (r200->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { - OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS, 0); - } else { - OUT_BATCH_REGVAL(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); - } - OUT_BATCH_REGVAL(R200_SE_VAP_CNTL, (R200_VAP_FORCE_W_TO_ONE | - (9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT))); - OUT_BATCH_REGVAL(R200_SE_VTX_STATE_CNTL, 0); - OUT_BATCH_REGVAL(R200_SE_VTE_CNTL, 0); - OUT_BATCH_REGVAL(R200_SE_VTX_FMT_0, R200_VTX_XY); - OUT_BATCH_REGVAL(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT)); - OUT_BATCH_REGVAL(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | - RADEON_BFACE_SOLID | - RADEON_FFACE_SOLID | - RADEON_VTX_PIX_CENTER_OGL | - RADEON_ROUND_MODE_ROUND | - RADEON_ROUND_PREC_4TH_PIX)); - END_BATCH(); -} - -static void inline emit_tx_setup(struct r200_context *r200, - mesa_format src_mesa_format, - mesa_format dst_mesa_format, - struct radeon_bo *bo, - intptr_t offset, - unsigned width, - unsigned height, - unsigned pitch) -{ - uint32_t txformat = R200_TXFORMAT_NON_POWER2; - BATCH_LOCALS(&r200->radeon); - - assert(width <= 2048); - assert(height <= 2048); - assert(offset % 32 == 0); - -#if UTIL_ARCH_LITTLE_ENDIAN - txformat |= tx_table_le[src_mesa_format].format; -#else - txformat |= tx_table_be[src_mesa_format].format; -#endif - - if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE) - offset |= R200_TXO_MACRO_TILE; - if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE) - offset |= R200_TXO_MICRO_TILE; - - switch (dst_mesa_format) { - /* le */ - case MESA_FORMAT_B8G8R8A8_UNORM: - case MESA_FORMAT_B8G8R8X8_UNORM: - case MESA_FORMAT_B5G6R5_UNORM: - case MESA_FORMAT_B4G4R4A4_UNORM: - case MESA_FORMAT_B5G5R5A1_UNORM: - /* be */ - case MESA_FORMAT_A8R8G8B8_UNORM: - case MESA_FORMAT_X8R8G8B8_UNORM: - case MESA_FORMAT_R5G6B5_UNORM: - case MESA_FORMAT_A4R4G4B4_UNORM: - case MESA_FORMAT_A1R5G5B5_UNORM: - /* little and big */ - case MESA_FORMAT_A_UNORM8: - case MESA_FORMAT_L_UNORM8: - case MESA_FORMAT_I_UNORM8: - default: - /* no swizzle required */ - BEGIN_BATCH(10); - OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | - RADEON_TEX_BLEND_0_ENABLE)); - OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO | - R200_TXC_ARG_B_ZERO | - R200_TXC_ARG_C_R0_COLOR | - R200_TXC_OP_MADD)); - OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 | - R200_TXC_OUTPUT_REG_R0)); - OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO | - R200_TXA_ARG_B_ZERO | - R200_TXA_ARG_C_R0_ALPHA | - R200_TXA_OP_MADD)); - OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, (R200_TXA_CLAMP_0_1 | - R200_TXA_OUTPUT_REG_R0)); - END_BATCH(); - break; - case MESA_FORMAT_A8B8G8R8_UNORM: - case MESA_FORMAT_R8G8B8A8_UNORM: -#if UTIL_ARCH_LITTLE_ENDIAN - if (dst_mesa_format == MESA_FORMAT_A8B8G8R8_UNORM) { -#else - if (dst_mesa_format == MESA_FORMAT_R8G8B8A8_UNORM) { -#endif - BEGIN_BATCH(10); - OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | - RADEON_TEX_BLEND_0_ENABLE)); - OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO | - R200_TXC_ARG_B_ZERO | - R200_TXC_ARG_C_R0_COLOR | - R200_TXC_OP_MADD)); - /* XXX I don't think this can work. This is output rotation, and alpha contains - * red, not alpha (we'd write gbrr). */ - OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 | - R200_TXC_OUTPUT_ROTATE_GBA | - R200_TXC_OUTPUT_REG_R0)); - OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO | - R200_TXA_ARG_B_ZERO | - R200_TXA_ARG_C_R0_ALPHA | - R200_TXA_OP_MADD)); - OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, (R200_TXA_CLAMP_0_1 | - (R200_TXA_REPL_RED << R200_TXA_REPL_ARG_C_SHIFT) | - R200_TXA_OUTPUT_REG_R0)); - END_BATCH(); - } - else { - /* XXX pretty sure could do this with just 2 instead of 4 instructions. - * Like so: - * 1st: use RGA output rotation, rgb arg replicate b, a arg r, write mask rb. - * That's just one instruction in fact but I'm not entirely sure it works - * if some of those incoming r0 components are never written (due to mask) - * in the shader itself to r0. - * In any case this case (and the one above) may not be reachable with - * disabled Choose8888TexFormat code. */ - BEGIN_BATCH(34); - OUT_BATCH_REGVAL(RADEON_PP_CNTL, (RADEON_TEX_0_ENABLE | - RADEON_TEX_BLEND_0_ENABLE | - RADEON_TEX_BLEND_1_ENABLE | - RADEON_TEX_BLEND_2_ENABLE | - RADEON_TEX_BLEND_3_ENABLE)); - /* r1.r = r0.b */ - OUT_BATCH_REGVAL(R200_PP_TXCBLEND_0, (R200_TXC_ARG_A_ZERO | - R200_TXC_ARG_B_ZERO | - R200_TXC_ARG_C_R0_COLOR | - R200_TXC_OP_MADD)); - OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_0, (R200_TXC_CLAMP_0_1 | - R200_TXC_OUTPUT_MASK_R | - (R200_TXC_REPL_BLUE << R200_TXC_REPL_ARG_C_SHIFT) | - R200_TXC_OUTPUT_REG_R1)); - /* r1.a = r0.a */ - OUT_BATCH_REGVAL(R200_PP_TXABLEND_0, (R200_TXA_ARG_A_ZERO | - R200_TXA_ARG_B_ZERO | - R200_TXA_ARG_C_R0_ALPHA | - R200_TXA_OP_MADD)); - OUT_BATCH_REGVAL(R200_PP_TXABLEND2_0, (R200_TXA_CLAMP_0_1 | - R200_TXA_OUTPUT_REG_R1)); - /* r1.g = r0.g */ - OUT_BATCH_REGVAL(R200_PP_TXCBLEND_1, (R200_TXC_ARG_A_ZERO | - R200_TXC_ARG_B_ZERO | - R200_TXC_ARG_C_R0_COLOR | - R200_TXC_OP_MADD)); - OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_1, (R200_TXC_CLAMP_0_1 | - R200_TXC_OUTPUT_MASK_G | - (R200_TXC_REPL_GREEN << R200_TXC_REPL_ARG_C_SHIFT) | - R200_TXC_OUTPUT_REG_R1)); - /* r1.a = r0.a */ - OUT_BATCH_REGVAL(R200_PP_TXABLEND_1, (R200_TXA_ARG_A_ZERO | - R200_TXA_ARG_B_ZERO | - R200_TXA_ARG_C_R0_ALPHA | - R200_TXA_OP_MADD)); - OUT_BATCH_REGVAL(R200_PP_TXABLEND2_1, (R200_TXA_CLAMP_0_1 | - R200_TXA_OUTPUT_REG_R1)); - /* r1.b = r0.r */ - OUT_BATCH_REGVAL(R200_PP_TXCBLEND_2, (R200_TXC_ARG_A_ZERO | - R200_TXC_ARG_B_ZERO | - R200_TXC_ARG_C_R0_COLOR | - R200_TXC_OP_MADD)); - OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_2, (R200_TXC_CLAMP_0_1 | - R200_TXC_OUTPUT_MASK_B | - (R200_TXC_REPL_RED << R200_TXC_REPL_ARG_C_SHIFT) | - R200_TXC_OUTPUT_REG_R1)); - /* r1.a = r0.a */ - OUT_BATCH_REGVAL(R200_PP_TXABLEND_2, (R200_TXA_ARG_A_ZERO | - R200_TXA_ARG_B_ZERO | - R200_TXA_ARG_C_R0_ALPHA | - R200_TXA_OP_MADD)); - OUT_BATCH_REGVAL(R200_PP_TXABLEND2_2, (R200_TXA_CLAMP_0_1 | - R200_TXA_OUTPUT_REG_R1)); - /* r0.rgb = r1.rgb */ - OUT_BATCH_REGVAL(R200_PP_TXCBLEND_3, (R200_TXC_ARG_A_ZERO | - R200_TXC_ARG_B_ZERO | - R200_TXC_ARG_C_R1_COLOR | - R200_TXC_OP_MADD)); - OUT_BATCH_REGVAL(R200_PP_TXCBLEND2_3, (R200_TXC_CLAMP_0_1 | - R200_TXC_OUTPUT_REG_R0)); - /* r0.a = r1.a */ - OUT_BATCH_REGVAL(R200_PP_TXABLEND_3, (R200_TXA_ARG_A_ZERO | - R200_TXA_ARG_B_ZERO | - R200_TXA_ARG_C_R1_ALPHA | - R200_TXA_OP_MADD)); - OUT_BATCH_REGVAL(R200_PP_TXABLEND2_3, (R200_TXA_CLAMP_0_1 | - R200_TXA_OUTPUT_REG_R0)); - END_BATCH(); - } - break; - } - - BEGIN_BATCH(18); - OUT_BATCH_REGVAL(R200_PP_CNTL_X, 0); - OUT_BATCH_REGVAL(R200_PP_TXMULTI_CTL_0, 0); - OUT_BATCH_REGVAL(R200_PP_TXFILTER_0, (R200_CLAMP_S_CLAMP_LAST | - R200_CLAMP_T_CLAMP_LAST | - R200_MAG_FILTER_NEAREST | - R200_MIN_FILTER_NEAREST)); - OUT_BATCH_REGVAL(R200_PP_TXFORMAT_0, txformat); - OUT_BATCH_REGVAL(R200_PP_TXFORMAT_X_0, 0); - OUT_BATCH_REGVAL(R200_PP_TXSIZE_0, ((width - 1) | - ((height - 1) << RADEON_TEX_VSIZE_SHIFT))); - OUT_BATCH_REGVAL(R200_PP_TXPITCH_0, pitch * _mesa_get_format_bytes(src_mesa_format) - 32); - - OUT_BATCH_REGSEQ(R200_PP_TXOFFSET_0, 1); - OUT_BATCH_RELOC(bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - - END_BATCH(); -} - -static inline void emit_cb_setup(struct r200_context *r200, - struct radeon_bo *bo, - intptr_t offset, - mesa_format mesa_format, - unsigned pitch, - unsigned width, - unsigned height) -{ - uint32_t dst_pitch = pitch; - uint32_t dst_format = 0; - BATCH_LOCALS(&r200->radeon); - - switch (mesa_format) { - /* The first of each pair is for little, the second for big endian */ - case MESA_FORMAT_B8G8R8A8_UNORM: - case MESA_FORMAT_A8R8G8B8_UNORM: - case MESA_FORMAT_B8G8R8X8_UNORM: - case MESA_FORMAT_X8R8G8B8_UNORM: - /* These two are valid both for little and big endian (swizzled) */ - case MESA_FORMAT_A8B8G8R8_UNORM: - case MESA_FORMAT_R8G8B8A8_UNORM: - dst_format = RADEON_COLOR_FORMAT_ARGB8888; - break; - case MESA_FORMAT_B5G6R5_UNORM: - case MESA_FORMAT_R5G6B5_UNORM: - dst_format = RADEON_COLOR_FORMAT_RGB565; - break; - case MESA_FORMAT_B4G4R4A4_UNORM: - case MESA_FORMAT_A4R4G4B4_UNORM: - dst_format = RADEON_COLOR_FORMAT_ARGB4444; - break; - case MESA_FORMAT_B5G5R5A1_UNORM: - case MESA_FORMAT_A1R5G5B5_UNORM: - dst_format = RADEON_COLOR_FORMAT_ARGB1555; - break; - case MESA_FORMAT_A_UNORM8: - case MESA_FORMAT_L_UNORM8: - case MESA_FORMAT_I_UNORM8: - dst_format = RADEON_COLOR_FORMAT_RGB8; - break; - default: - break; - } - - if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE) - dst_pitch |= R200_COLOR_TILE_ENABLE; - if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE) - dst_pitch |= R200_COLOR_MICROTILE_ENABLE; - - BEGIN_BATCH(22); - OUT_BATCH_REGVAL(R200_RE_AUX_SCISSOR_CNTL, 0); - OUT_BATCH_REGVAL(R200_RE_CNTL, 0); - OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT, 0); - OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, (((width - 1) << RADEON_RE_WIDTH_SHIFT) | - ((height - 1) << RADEON_RE_HEIGHT_SHIFT))); - OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK, 0xffffffff); - OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO); - OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format); - - OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET, 1); - OUT_BATCH_RELOC(bo, offset, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); - OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH, 1); - OUT_BATCH_RELOC(bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); - - END_BATCH(); -} - -static GLboolean validate_buffers(struct r200_context *r200, - struct radeon_bo *src_bo, - struct radeon_bo *dst_bo) -{ - int ret; - - radeon_cs_space_reset_bos(r200->radeon.cmdbuf.cs); - - ret = radeon_cs_space_check_with_bo(r200->radeon.cmdbuf.cs, - src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0); - if (ret) - return GL_FALSE; - - ret = radeon_cs_space_check_with_bo(r200->radeon.cmdbuf.cs, - dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT); - if (ret) - return GL_FALSE; - - return GL_TRUE; -} - -/** - * Calculate texcoords for given image region. - * Output values are [minx, maxx, miny, maxy] - */ -static inline void calc_tex_coords(float img_width, float img_height, - float x, float y, - float reg_width, float reg_height, - unsigned flip_y, float *buf) -{ - buf[0] = x / img_width; - buf[1] = buf[0] + reg_width / img_width; - buf[2] = y / img_height; - buf[3] = buf[2] + reg_height / img_height; - if (flip_y) - { - buf[2] = 1.0 - buf[2]; - buf[3] = 1.0 - buf[3]; - } -} - -static inline void emit_draw_packet(struct r200_context *r200, - unsigned src_width, unsigned src_height, - unsigned src_x_offset, unsigned src_y_offset, - unsigned dst_x_offset, unsigned dst_y_offset, - unsigned reg_width, unsigned reg_height, - unsigned flip_y) -{ - float texcoords[4]; - float verts[12]; - BATCH_LOCALS(&r200->radeon); - - calc_tex_coords(src_width, src_height, - src_x_offset, src_y_offset, - reg_width, reg_height, - flip_y, texcoords); - - verts[0] = dst_x_offset; - verts[1] = dst_y_offset + reg_height; - verts[2] = texcoords[0]; - verts[3] = texcoords[3]; - - verts[4] = dst_x_offset + reg_width; - verts[5] = dst_y_offset + reg_height; - verts[6] = texcoords[1]; - verts[7] = texcoords[3]; - - verts[8] = dst_x_offset + reg_width; - verts[9] = dst_y_offset; - verts[10] = texcoords[1]; - verts[11] = texcoords[2]; - - BEGIN_BATCH(14); - OUT_BATCH(R200_CP_CMD_3D_DRAW_IMMD_2 | (12 << 16)); - OUT_BATCH(RADEON_CP_VC_CNTL_PRIM_WALK_RING | - RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST | - (3 << 16)); - OUT_BATCH_TABLE(verts, 12); - END_BATCH(); -} - -/** - * Copy a region of [@a width x @a height] pixels from source buffer - * to destination buffer. - * @param[in] r200 r200 context - * @param[in] src_bo source radeon buffer object - * @param[in] src_offset offset of the source image in the @a src_bo - * @param[in] src_mesaformat source image format - * @param[in] src_pitch aligned source image width - * @param[in] src_width source image width - * @param[in] src_height source image height - * @param[in] src_x_offset x offset in the source image - * @param[in] src_y_offset y offset in the source image - * @param[in] dst_bo destination radeon buffer object - * @param[in] dst_offset offset of the destination image in the @a dst_bo - * @param[in] dst_mesaformat destination image format - * @param[in] dst_pitch aligned destination image width - * @param[in] dst_width destination image width - * @param[in] dst_height destination image height - * @param[in] dst_x_offset x offset in the destination image - * @param[in] dst_y_offset y offset in the destination image - * @param[in] width region width - * @param[in] height region height - * @param[in] flip_y set if y coords of the source image need to be flipped - */ -unsigned r200_blit(struct gl_context *ctx, - struct radeon_bo *src_bo, - intptr_t src_offset, - mesa_format src_mesaformat, - unsigned src_pitch, - unsigned src_width, - unsigned src_height, - unsigned src_x_offset, - unsigned src_y_offset, - struct radeon_bo *dst_bo, - intptr_t dst_offset, - mesa_format dst_mesaformat, - unsigned dst_pitch, - unsigned dst_width, - unsigned dst_height, - unsigned dst_x_offset, - unsigned dst_y_offset, - unsigned reg_width, - unsigned reg_height, - unsigned flip_y) -{ - struct r200_context *r200 = R200_CONTEXT(ctx); - - if (!r200_check_blit(dst_mesaformat, dst_pitch)) - return GL_FALSE; - - /* Make sure that colorbuffer has even width - hw limitation */ - if (dst_pitch % 2 > 0) - ++dst_pitch; - - /* Need to clamp the region size to make sure - * we don't read outside of the source buffer - * or write outside of the destination buffer. - */ - if (reg_width + src_x_offset > src_width) - reg_width = src_width - src_x_offset; - if (reg_height + src_y_offset > src_height) - reg_height = src_height - src_y_offset; - if (reg_width + dst_x_offset > dst_width) - reg_width = dst_width - dst_x_offset; - if (reg_height + dst_y_offset > dst_height) - reg_height = dst_height - dst_y_offset; - - if (src_bo == dst_bo) { - return GL_FALSE; - } - - if (src_offset % 32 || dst_offset % 32) { - return GL_FALSE; - } - - if (0) { - fprintf(stderr, "src: size [%d x %d], pitch %d, " - "offset [%d x %d], format %s, bo %p\n", - src_width, src_height, src_pitch, - src_x_offset, src_y_offset, - _mesa_get_format_name(src_mesaformat), - src_bo); - fprintf(stderr, "dst: pitch %d, offset[%d x %d], format %s, bo %p\n", - dst_pitch, dst_x_offset, dst_y_offset, - _mesa_get_format_name(dst_mesaformat), dst_bo); - fprintf(stderr, "region: %d x %d\n", reg_width, reg_height); - } - - /* Flush is needed to make sure that source buffer has correct data */ - radeonFlush(&r200->radeon.glCtx, 0); - - rcommonEnsureCmdBufSpace(&r200->radeon, 102, __func__); - - if (!validate_buffers(r200, src_bo, dst_bo)) - return GL_FALSE; - - /* 14 */ - emit_vtx_state(r200); - /* 52 */ - emit_tx_setup(r200, src_mesaformat, dst_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch); - /* 22 */ - emit_cb_setup(r200, dst_bo, dst_offset, dst_mesaformat, dst_pitch, dst_width, dst_height); - /* 14 */ - emit_draw_packet(r200, src_width, src_height, - src_x_offset, src_y_offset, - dst_x_offset, dst_y_offset, - reg_width, reg_height, - flip_y); - - radeonFlush(ctx, 0); - - /* We submitted those packets outside our state atom mechanism. Thus - * make sure the atoms are resubmitted the next time. */ - r200->hw.cst.dirty = GL_TRUE; - r200->hw.ctx.dirty = GL_TRUE; - r200->hw.vap.dirty = GL_TRUE; - r200->hw.msk.dirty = GL_TRUE; - r200->hw.pix[0].dirty = GL_TRUE; - r200->hw.pix[1].dirty = GL_TRUE; - r200->hw.pix[2].dirty = GL_TRUE; - r200->hw.pix[3].dirty = GL_TRUE; - r200->hw.sci.dirty = GL_TRUE; - r200->hw.set.dirty = GL_TRUE; - r200->hw.tex[0].dirty = GL_TRUE; - r200->hw.vte.dirty = GL_TRUE; - r200->hw.vtx.dirty = GL_TRUE; - - return GL_TRUE; -} diff --git a/src/mesa/drivers/dri/r200/r200_blit.h b/src/mesa/drivers/dri/r200/r200_blit.h deleted file mode 100644 index 23057476336..00000000000 --- a/src/mesa/drivers/dri/r200/r200_blit.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2009 Maciej Cencora <m.cencora@gmail.com> - * - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining - * a copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sublicense, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial - * portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE - * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION - * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION - * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef R200_BLIT_H -#define R200_BLIT_H - -void r200_blit_init(struct r200_context *r200); - -unsigned r200_check_blit(mesa_format mesa_format, uint32_t dst_pitch); - -unsigned r200_blit(struct gl_context *ctx, - struct radeon_bo *src_bo, - intptr_t src_offset, - mesa_format src_mesaformat, - unsigned src_pitch, - unsigned src_width, - unsigned src_height, - unsigned src_x_offset, - unsigned src_y_offset, - struct radeon_bo *dst_bo, - intptr_t dst_offset, - mesa_format dst_mesaformat, - unsigned dst_pitch, - unsigned dst_width, - unsigned dst_height, - unsigned dst_x_offset, - unsigned dst_y_offset, - unsigned width, - unsigned height, - unsigned flip_y); - -#endif // R200_BLIT_H diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c deleted file mode 100644 index 4a068e0d930..00000000000 --- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c +++ /dev/null @@ -1,300 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - -/* - * Authors: - * Keith Whitwell <keithw@vmware.com> - */ - -#include "main/glheader.h" - -#include "main/macros.h" -#include "main/context.h" -#include "util/simple_list.h" - -#include "radeon_common.h" -#include "r200_context.h" -#include "r200_ioctl.h" -#include "radeon_reg.h" - -/* The state atoms will be emitted in the order they appear in the atom list, - * so this step is important. - */ -#define insert_at_tail_if(atom_list, atom) \ - do { \ - struct radeon_state_atom* current_atom = (atom); \ - if (current_atom->check) \ - insert_at_tail((atom_list), current_atom); \ - } while(0) - -void r200SetUpAtomList( r200ContextPtr rmesa ) -{ - int i, mtu; - - mtu = rmesa->radeon.glCtx.Const.MaxTextureUnits; - - make_empty_list(&rmesa->radeon.hw.atomlist); - rmesa->radeon.hw.atomlist.name = "atom-list"; - - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.ctx ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.set ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.lin ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.msk ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpt ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vtx ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vap ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vte ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.msc ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.cst ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.zbs ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcl ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.msl ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcg ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.grd ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.fog ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.tam ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.tf ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.atf ); - for (i = 0; i < mtu; ++i) - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.tex[i] ); - for (i = 0; i < mtu; ++i) - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.cube[i] ); - for (i = 0; i < 6; ++i) - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.pix[i] ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.afs[0] ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.afs[1] ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.stp ); - for (i = 0; i < 8; ++i) - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.lit[i] ); - for (i = 0; i < 3 + mtu; ++i) - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.mat[i] ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.eye ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.glt ); - for (i = 0; i < 2; ++i) - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.mtl[i] ); - for (i = 0; i < 6; ++i) - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.ucp[i] ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.spr ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.ptp ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.prf ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.pvs ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpp[0] ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpp[1] ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpi[0] ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpi[1] ); - insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.sci ); -} - -/* Fire a section of the retained (indexed_verts) buffer as a regular - * primtive. - */ -void r200EmitVbufPrim( r200ContextPtr rmesa, - GLuint primitive, - GLuint vertex_nr ) -{ - BATCH_LOCALS(&rmesa->radeon); - - assert(!(primitive & R200_VF_PRIM_WALK_IND)); - - radeonEmitState(&rmesa->radeon); - - radeon_print(RADEON_RENDER|RADEON_SWRENDER,RADEON_VERBOSE, - "%s cmd_used/4: %d prim %x nr %d\n", __func__, - rmesa->store.cmd_used/4, primitive, vertex_nr); - - BEGIN_BATCH(3); - OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_VBUF_2, 0); - OUT_BATCH(primitive | R200_VF_PRIM_WALK_LIST | R200_VF_COLOR_ORDER_RGBA | - (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT)); - END_BATCH(); -} - -static void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type) -{ - BATCH_LOCALS(&rmesa->radeon); - - if (vertex_count > 0) { - BEGIN_BATCH(8+2); - OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_INDX_2, 0); - OUT_BATCH(R200_VF_PRIM_WALK_IND | - R200_VF_COLOR_ORDER_RGBA | - ((vertex_count + 0) << 16) | - type); - - OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2); - OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810); - OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset); - OUT_BATCH((vertex_count + 1)/2); - radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->radeon.tcl.elt_dma_bo, - RADEON_GEM_DOMAIN_GTT, 0, 0); - END_BATCH(); - } -} - -void r200FlushElts(struct gl_context *ctx) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - int nr, elt_used = rmesa->tcl.elt_used; - - radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s %x %d\n", __func__, rmesa->tcl.hw_primitive, elt_used); - - assert( rmesa->radeon.dma.flush == r200FlushElts ); - rmesa->radeon.dma.flush = NULL; - - nr = elt_used / 2; - - radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo); - - r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive); - - radeon_bo_unref(rmesa->radeon.tcl.elt_dma_bo); - rmesa->radeon.tcl.elt_dma_bo = NULL; - - if (R200_ELT_BUF_SZ > elt_used) - radeonReturnDmaRegion(&rmesa->radeon, R200_ELT_BUF_SZ - elt_used); -} - - -GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, - GLuint primitive, - GLuint min_nr ) -{ - GLushort *retval; - - radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s %d prim %x\n", __func__, min_nr, primitive); - - assert((primitive & R200_VF_PRIM_WALK_IND)); - - radeonEmitState(&rmesa->radeon); - - radeonAllocDmaRegion(&rmesa->radeon, &rmesa->radeon.tcl.elt_dma_bo, - &rmesa->radeon.tcl.elt_dma_offset, R200_ELT_BUF_SZ, 4); - rmesa->tcl.elt_used = min_nr * 2; - - radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1); - retval = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset; - - assert(!rmesa->radeon.dma.flush); - rmesa->radeon.glCtx.Driver.NeedFlush |= FLUSH_STORED_VERTICES; - rmesa->radeon.dma.flush = r200FlushElts; - - return retval; -} - -void r200EmitMaxVtxIndex(r200ContextPtr rmesa, int count) -{ - BATCH_LOCALS(&rmesa->radeon); - - BEGIN_BATCH(2); - OUT_BATCH(CP_PACKET0(R200_SE_VF_MAX_VTX_INDX, 0)); - OUT_BATCH(count); - END_BATCH(); -} - -void r200EmitVertexAOS( r200ContextPtr rmesa, - GLuint vertex_size, - struct radeon_bo *bo, - GLuint offset ) -{ - BATCH_LOCALS(&rmesa->radeon); - - radeon_print(RADEON_SWRENDER, RADEON_VERBOSE, "%s: vertex_size 0x%x offset 0x%x \n", - __func__, vertex_size, offset); - - - BEGIN_BATCH(7); - OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, 2); - OUT_BATCH(1); - OUT_BATCH(vertex_size | (vertex_size << 8)); - OUT_BATCH_RELOC(bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0); - END_BATCH(); -} - -void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset) -{ - BATCH_LOCALS(&rmesa->radeon); - uint32_t voffset; - int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2; - int i; - - radeon_print(RADEON_RENDER, RADEON_VERBOSE, - "%s: nr=%d, ofs=0x%08x\n", - __func__, nr, offset); - - BEGIN_BATCH(sz+2+ (nr*2)); - OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, sz - 1); - OUT_BATCH(nr); - - { - for (i = 0; i + 1 < nr; i += 2) { - OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) | - (rmesa->radeon.tcl.aos[i].stride << 8) | - (rmesa->radeon.tcl.aos[i + 1].components << 16) | - (rmesa->radeon.tcl.aos[i + 1].stride << 24)); - - voffset = rmesa->radeon.tcl.aos[i + 0].offset + - offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; - OUT_BATCH(voffset); - voffset = rmesa->radeon.tcl.aos[i + 1].offset + - offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; - OUT_BATCH(voffset); - } - - if (nr & 1) { - OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | - (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); - voffset = rmesa->radeon.tcl.aos[nr - 1].offset + - offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; - OUT_BATCH(voffset); - } - for (i = 0; i + 1 < nr; i += 2) { - voffset = rmesa->radeon.tcl.aos[i + 0].offset + - offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; - radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->radeon.tcl.aos[i+0].bo, - RADEON_GEM_DOMAIN_GTT, - 0, 0); - voffset = rmesa->radeon.tcl.aos[i + 1].offset + - offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; - radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->radeon.tcl.aos[i+1].bo, - RADEON_GEM_DOMAIN_GTT, - 0, 0); - } - if (nr & 1) { - voffset = rmesa->radeon.tcl.aos[nr - 1].offset + - offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; - radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, - rmesa->radeon.tcl.aos[nr-1].bo, - RADEON_GEM_DOMAIN_GTT, - 0, 0); - } - } - END_BATCH(); -} diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c deleted file mode 100644 index d7264deca29..00000000000 --- a/src/mesa/drivers/dri/r200/r200_context.c +++ /dev/null @@ -1,413 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell <keithw@vmware.com> - */ - -#include <stdbool.h> -#include "main/glheader.h" -#include "main/api_arrayelt.h" -#include "main/api_exec.h" -#include "main/context.h" - -#include "main/extensions.h" -#include "main/version.h" -#include "main/vtxfmt.h" - -#include "swrast/swrast.h" -#include "swrast_setup/swrast_setup.h" -#include "vbo/vbo.h" - -#include "tnl/tnl.h" -#include "tnl/t_pipeline.h" - -#include "drivers/common/driverfuncs.h" - -#include "r200_context.h" -#include "r200_ioctl.h" -#include "r200_state.h" -#include "r200_tex.h" -#include "r200_swtcl.h" -#include "r200_tcl.h" -#include "r200_vertprog.h" -#include "radeon_queryobj.h" -#include "r200_blit.h" -#include "radeon_fog.h" - -#include "radeon_span.h" - -#include "utils.h" -#include "util/driconf.h" /* for symbolic values of enum-type options */ -#include "util/u_memory.h" - -/* Return various strings for glGetString(). - */ -static const GLubyte *r200GetString( struct gl_context *ctx, GLenum name ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - static char buffer[128]; - unsigned offset; - GLuint agp_mode = (rmesa->radeon.radeonScreen->card_type == RADEON_CARD_PCI)? 0 : - rmesa->radeon.radeonScreen->AGPMode; - - switch ( name ) { - case GL_VENDOR: - return (GLubyte *)"Mesa Project"; - - case GL_RENDERER: - offset = driGetRendererString( buffer, "R200", agp_mode ); - - sprintf( & buffer[ offset ], " %sTCL", - !(rmesa->radeon.TclFallback & R200_TCL_FALLBACK_TCL_DISABLE) - ? "" : "NO-" ); - - return (GLubyte *)buffer; - - default: - return NULL; - } -} - - -extern const struct tnl_pipeline_stage _r200_render_stage; -extern const struct tnl_pipeline_stage _r200_tcl_stage; - -static const struct tnl_pipeline_stage *r200_pipeline[] = { - - /* Try and go straight to t&l - */ - &_r200_tcl_stage, - - /* Catch any t&l fallbacks - */ - &_tnl_vertex_transform_stage, - &_tnl_normal_transform_stage, - &_tnl_lighting_stage, - &_tnl_fog_coordinate_stage, - &_tnl_texgen_stage, - &_tnl_texture_transform_stage, - &_tnl_point_attenuation_stage, - &_tnl_vertex_program_stage, - /* Try again to go to tcl? - * - no good for asymmetric-twoside (do with multipass) - * - no good for asymmetric-unfilled (do with multipass) - * - good for material - * - good for texgen - * - need to manipulate a bit of state - * - * - worth it/not worth it? - */ - - /* Else do them here. - */ -/* &_r200_render_stage, */ /* FIXME: bugs with ut2003 */ - &_tnl_render_stage, /* FALLBACK: */ - NULL, -}; - - - -/* Initialize the driver's misc functions. - */ -static void r200InitDriverFuncs( struct dd_function_table *functions ) -{ - functions->GetString = r200GetString; -} - - -static void r200_emit_query_finish(radeonContextPtr radeon) -{ - BATCH_LOCALS(radeon); - struct radeon_query_object *query = radeon->query.current; - - BEGIN_BATCH(4); - OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0)); - OUT_BATCH_RELOC(query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0); - END_BATCH(); - query->curr_offset += sizeof(uint32_t); - assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE); - query->emitted_begin = GL_FALSE; -} - -static void r200_init_vtbl(radeonContextPtr radeon) -{ - radeon->vtbl.swtcl_flush = r200_swtcl_flush; - radeon->vtbl.fallback = r200Fallback; - radeon->vtbl.update_scissor = r200_vtbl_update_scissor; - radeon->vtbl.emit_query_finish = r200_emit_query_finish; - radeon->vtbl.check_blit = r200_check_blit; - radeon->vtbl.blit = r200_blit; - radeon->vtbl.is_format_renderable = radeonIsFormatRenderable; - radeon->vtbl.revalidate_all_buffers = r200ValidateBuffers; -} - - -/* Create the device specific rendering context. - */ -GLboolean r200CreateContext( gl_api api, - const struct gl_config *glVisual, - __DRIcontext *driContextPriv, - const struct __DriverContextConfig *ctx_config, - unsigned *error, - void *sharedContextPrivate) -{ - __DRIscreen *sPriv = driContextPriv->driScreenPriv; - radeonScreenPtr screen = (radeonScreenPtr)(sPriv->driverPrivate); - struct dd_function_table functions; - r200ContextPtr rmesa; - struct gl_context *ctx; - int i; - int tcl_mode; - - if (ctx_config->flags & ~(__DRI_CTX_FLAG_DEBUG | __DRI_CTX_FLAG_NO_ERROR)) { - *error = __DRI_CTX_ERROR_UNKNOWN_FLAG; - return false; - } - - if (ctx_config->attribute_mask) { - *error = __DRI_CTX_ERROR_UNKNOWN_ATTRIBUTE; - return false; - } - - assert(driContextPriv); - assert(screen); - - /* Allocate the R200 context */ - rmesa = align_calloc(sizeof(*rmesa), 16); - if ( !rmesa ) { - *error = __DRI_CTX_ERROR_NO_MEMORY; - return GL_FALSE; - } - - rmesa->radeon.radeonScreen = screen; - r200_init_vtbl(&rmesa->radeon); - /* init exp fog table data */ - radeonInitStaticFogData(); - - /* Parse configuration files. - * Do this here so that initialMaxAnisotropy is set before we create - * the default textures. - */ - driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache, - screen->driScreen->myNum, "r200", NULL, NULL, NULL, 0, NULL, 0); - rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache, - "def_max_anisotropy"); - - if (driQueryOptionb( &rmesa->radeon.optionCache, "hyperz")) - rmesa->using_hyperz = GL_TRUE; - - /* Init default driver functions then plug in our R200-specific functions - * (the texture functions are especially important) - */ - _mesa_init_driver_functions(&functions); - _tnl_init_driver_draw_function(&functions); - r200InitDriverFuncs(&functions); - r200InitIoctlFuncs(&functions); - r200InitStateFuncs(&rmesa->radeon, &functions); - r200InitTextureFuncs(&rmesa->radeon, &functions); - r200InitShaderFuncs(&functions); - radeonInitQueryObjFunctions(&functions); - - if (!radeonInitContext(&rmesa->radeon, api, &functions, - glVisual, driContextPriv, - sharedContextPrivate)) { - align_free(rmesa); - *error = __DRI_CTX_ERROR_NO_MEMORY; - return GL_FALSE; - } - - rmesa->radeon.swtcl.RenderIndex = ~0; - rmesa->radeon.hw.all_dirty = 1; - - ctx = &rmesa->radeon.glCtx; - - driContextSetFlags(ctx, ctx_config->flags); - - /* Initialize the software rasterizer and helper modules. - */ - _swrast_CreateContext( ctx ); - _vbo_CreateContext( ctx, false ); - _tnl_CreateContext( ctx ); - _swsetup_CreateContext( ctx ); - - ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache, - "texture_units"); - ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits = ctx->Const.MaxTextureUnits; - ctx->Const.MaxTextureCoordUnits = ctx->Const.MaxTextureUnits; - - ctx->Const.MaxCombinedTextureImageUnits = ctx->Const.MaxTextureUnits; - - ctx->Const.StripTextureBorder = GL_TRUE; - - /* FIXME: When no memory manager is available we should set this - * to some reasonable value based on texture memory pool size */ - ctx->Const.MaxTextureSize = 2048; - ctx->Const.Max3DTextureLevels = 9; - ctx->Const.MaxCubeTextureLevels = 12; - ctx->Const.MaxTextureRectSize = 2048; - ctx->Const.MaxRenderbufferSize = 2048; - - ctx->Const.MaxTextureMaxAnisotropy = 16.0; - - /* No wide AA points. - */ - ctx->Const.MinPointSize = 1.0; - ctx->Const.MinPointSizeAA = 1.0; - ctx->Const.MaxPointSizeAA = 1.0; - ctx->Const.PointSizeGranularity = 0.0625; - ctx->Const.MaxPointSize = 2047.0; - - /* mesa initialization problem - _mesa_init_point was already called */ - ctx->Point.MaxSize = ctx->Const.MaxPointSize; - - ctx->Const.MinLineWidth = 1.0; - ctx->Const.MinLineWidthAA = 1.0; - ctx->Const.MaxLineWidth = 10.0; - ctx->Const.MaxLineWidthAA = 10.0; - ctx->Const.LineWidthGranularity = 0.0625; - - ctx->Const.Program[MESA_SHADER_VERTEX].MaxNativeInstructions = R200_VSF_MAX_INST; - ctx->Const.Program[MESA_SHADER_VERTEX].MaxNativeAttribs = 12; - ctx->Const.Program[MESA_SHADER_VERTEX].MaxNativeTemps = R200_VSF_MAX_TEMPS; - ctx->Const.Program[MESA_SHADER_VERTEX].MaxNativeParameters = R200_VSF_MAX_PARAM; - ctx->Const.Program[MESA_SHADER_VERTEX].MaxNativeAddressRegs = 1; - - ctx->Const.MaxDrawBuffers = 1; - ctx->Const.MaxColorAttachments = 1; - - ctx->Const.ShaderCompilerOptions[MESA_SHADER_VERTEX].OptimizeForAOS = GL_TRUE; - - /* Install the customized pipeline: - */ - _tnl_destroy_pipeline( ctx ); - _tnl_install_pipeline( ctx, r200_pipeline ); - - /* Try and keep materials and vertices separate: - */ -/* _tnl_isolate_materials( ctx, GL_TRUE ); */ - - - /* Configure swrast and TNL to match hardware characteristics: - */ - _swrast_allow_pixel_fog( ctx, GL_FALSE ); - _swrast_allow_vertex_fog( ctx, GL_TRUE ); - _tnl_allow_pixel_fog( ctx, GL_FALSE ); - _tnl_allow_vertex_fog( ctx, GL_TRUE ); - - - for ( i = 0 ; i < R200_MAX_TEXTURE_UNITS ; i++ ) { - _math_matrix_ctr( &rmesa->TexGenMatrix[i] ); - _math_matrix_set_identity( &rmesa->TexGenMatrix[i] ); - } - _math_matrix_ctr( &rmesa->tmpmat ); - _math_matrix_set_identity( &rmesa->tmpmat ); - - ctx->Extensions.ARB_occlusion_query = true; - ctx->Extensions.ARB_point_sprite = true; - ctx->Extensions.ARB_texture_border_clamp = true; - ctx->Extensions.ARB_texture_cube_map = true; - ctx->Extensions.ARB_texture_env_combine = true; - ctx->Extensions.ARB_texture_env_dot3 = true; - ctx->Extensions.ARB_texture_env_crossbar = true; - ctx->Extensions.ARB_texture_filter_anisotropic = true; - ctx->Extensions.ARB_texture_mirror_clamp_to_edge = true; - ctx->Extensions.ARB_vertex_program = true; - ctx->Extensions.ATI_fragment_shader = (ctx->Const.MaxTextureUnits == 6); - ctx->Extensions.ATI_texture_env_combine3 = true; - ctx->Extensions.ATI_texture_mirror_once = true; - ctx->Extensions.EXT_blend_color = true; - ctx->Extensions.EXT_blend_equation_separate = true; - ctx->Extensions.EXT_blend_func_separate = true; - ctx->Extensions.EXT_blend_minmax = true; - ctx->Extensions.EXT_gpu_program_parameters = true; - ctx->Extensions.EXT_point_parameters = true; - ctx->Extensions.EXT_texture_env_dot3 = true; - ctx->Extensions.EXT_texture_filter_anisotropic = true; - ctx->Extensions.EXT_texture_mirror_clamp = true; - ctx->Extensions.NV_fog_distance = true; - ctx->Extensions.NV_texture_rectangle = true; - ctx->Extensions.OES_EGL_image = true; - - if (!(rmesa->radeon.radeonScreen->chip_flags & R200_CHIPSET_YCBCR_BROKEN)) { - /* yuv textures don't work with some chips - R200 / rv280 okay so far - others get the bit ordering right but don't actually do YUV-RGB conversion */ - ctx->Extensions.MESA_ycbcr_texture = true; - } - ctx->Extensions.EXT_texture_compression_s3tc = true; - ctx->Extensions.ANGLE_texture_compression_dxt = true; - -#if 0 - r200InitDriverFuncs( ctx ); - r200InitIoctlFuncs( ctx ); - r200InitStateFuncs( ctx ); - r200InitTextureFuncs( ctx ); -#endif - /* plug in a few more device driver functions */ - /* XXX these should really go right after _mesa_init_driver_functions() */ - radeon_fbo_init(&rmesa->radeon); - radeonInitSpanFuncs( ctx ); - r200InitTnlFuncs( ctx ); - r200InitState( rmesa ); - r200InitSwtcl( ctx ); - - rmesa->prefer_gart_client_texturing = - (getenv("R200_GART_CLIENT_TEXTURES") != 0); - - tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode"); - if (getenv("R200_NO_RAST")) { - fprintf(stderr, "disabling 3D acceleration\n"); - FALLBACK(rmesa, R200_FALLBACK_DISABLE, 1); - } - else if (tcl_mode == DRI_CONF_TCL_SW || getenv("R200_NO_TCL") || - !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { - if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { - rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL; - fprintf(stderr, "Disabling HW TCL support\n"); - } - TCL_FALLBACK(&rmesa->radeon.glCtx, R200_TCL_FALLBACK_TCL_DISABLE, 1); - } - - _mesa_override_extensions(ctx); - _mesa_compute_version(ctx); - - /* Exec table initialization requires the version to be computed */ - _mesa_initialize_dispatch_tables(ctx); - _mesa_initialize_vbo_vtxfmt(ctx); - - *error = __DRI_CTX_ERROR_SUCCESS; - return GL_TRUE; -} - - -void r200DestroyContext( __DRIcontext *driContextPriv ) -{ - radeonDestroyContext(driContextPriv); -} diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h deleted file mode 100644 index 8ac39f1c575..00000000000 --- a/src/mesa/drivers/dri/r200/r200_context.h +++ /dev/null @@ -1,650 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell <keithw@vmware.com> - */ - -#ifndef __R200_CONTEXT_H__ -#define __R200_CONTEXT_H__ - -#include "tnl/t_vertex.h" -#include "drm-uapi/drm.h" -#include "radeon_drm.h" -#include "dri_util.h" - -#include "main/macros.h" -#include "main/mtypes.h" -#include "r200_reg.h" -#include "r200_vertprog.h" - -#ifndef R200_EMIT_VAP_PVS_CNTL -#error This driver requires a newer libdrm to compile -#endif - -#include "radeon_screen.h" -#include "radeon_common.h" - -struct r200_context; -typedef struct r200_context r200ContextRec; -typedef struct r200_context *r200ContextPtr; - - -struct r200_vertex_program { - struct gl_program mesa_program; /* Must be first */ - int translated; - /* need excess instr: 1 for late loop checking, 2 for - additional instr due to instr/attr, 3 for fog */ - VERTEX_SHADER_INSTRUCTION instr[R200_VSF_MAX_INST + 6]; - int pos_end; - int inputs[VERT_ATTRIB_MAX]; - GLubyte inputmap_rev[16]; - int native; - int fogpidx; - int fogmode; -}; - -#define R200_TEX_ALL 0x3f - - -struct r200_texture_env_state { - radeonTexObjPtr texobj; - GLuint outputreg; - GLuint unitneeded; -}; - -#define R200_MAX_TEXTURE_UNITS 6 - -struct r200_texture_state { - struct r200_texture_env_state unit[R200_MAX_TEXTURE_UNITS]; -}; - - -/* Trying to keep these relatively short as the variables are becoming - * extravagently long. Drop the driver name prefix off the front of - * everything - I think we know which driver we're in by now, and keep the - * prefix to 3 letters unless absolutely impossible. - */ - -#define CTX_CMD_0 0 -#define CTX_PP_MISC 1 -#define CTX_PP_FOG_COLOR 2 -#define CTX_RE_SOLID_COLOR 3 -#define CTX_RB3D_BLENDCNTL 4 -#define CTX_RB3D_DEPTHOFFSET 5 -#define CTX_RB3D_DEPTHPITCH 6 -#define CTX_RB3D_ZSTENCILCNTL 7 -#define CTX_CMD_1 8 -#define CTX_PP_CNTL 9 -#define CTX_RB3D_CNTL 10 -#define CTX_RB3D_COLOROFFSET 11 -#define CTX_CMD_2 12 /* why */ -#define CTX_RB3D_COLORPITCH 13 /* why */ -#define CTX_CMD_3 14 -#define CTX_RB3D_BLENDCOLOR 15 -#define CTX_RB3D_ABLENDCNTL 16 -#define CTX_RB3D_CBLENDCNTL 17 -#define CTX_STATE_SIZE_NEWDRM 18 - -#define SET_CMD_0 0 -#define SET_SE_CNTL 1 -#define SET_RE_CNTL 2 /* replace se_coord_fmt */ -#define SET_STATE_SIZE 3 - -#define VTE_CMD_0 0 -#define VTE_SE_VTE_CNTL 1 -#define VTE_STATE_SIZE 2 - -#define LIN_CMD_0 0 -#define LIN_RE_LINE_PATTERN 1 -#define LIN_RE_LINE_STATE 2 -#define LIN_CMD_1 3 -#define LIN_SE_LINE_WIDTH 4 -#define LIN_STATE_SIZE 5 - -#define MSK_CMD_0 0 -#define MSK_RB3D_STENCILREFMASK 1 -#define MSK_RB3D_ROPCNTL 2 -#define MSK_RB3D_PLANEMASK 3 -#define MSK_STATE_SIZE 4 - -#define VPT_CMD_0 0 -#define VPT_SE_VPORT_XSCALE 1 -#define VPT_SE_VPORT_XOFFSET 2 -#define VPT_SE_VPORT_YSCALE 3 -#define VPT_SE_VPORT_YOFFSET 4 -#define VPT_SE_VPORT_ZSCALE 5 -#define VPT_SE_VPORT_ZOFFSET 6 -#define VPT_STATE_SIZE 7 - -#define ZBS_CMD_0 0 -#define ZBS_SE_ZBIAS_FACTOR 1 -#define ZBS_SE_ZBIAS_CONSTANT 2 -#define ZBS_STATE_SIZE 3 - -#define MSC_CMD_0 0 -#define MSC_RE_MISC 1 -#define MSC_STATE_SIZE 2 - -#define TAM_CMD_0 0 -#define TAM_DEBUG3 1 -#define TAM_STATE_SIZE 2 - -#define TEX_CMD_0 0 -#define TEX_PP_TXFILTER 1 /*2c00*/ -#define TEX_PP_TXFORMAT 2 /*2c04*/ -#define TEX_PP_TXFORMAT_X 3 /*2c08*/ -#define TEX_PP_TXSIZE 4 /*2c0c*/ -#define TEX_PP_TXPITCH 5 /*2c10*/ -#define TEX_PP_BORDER_COLOR 6 /*2c14*/ -#define TEX_PP_CUBIC_FACES 7 -#define TEX_PP_TXMULTI_CTL 8 -#define TEX_CMD_1_NEWDRM 9 -#define TEX_PP_TXOFFSET_NEWDRM 10 -#define TEX_STATE_SIZE_NEWDRM 11 - -#define CUBE_CMD_0 0 /* 1 register follows */ /* this command unnecessary */ -#define CUBE_PP_CUBIC_FACES 1 /* 0x2c18 */ /* with new enough drm */ -#define CUBE_CMD_1 2 /* 5 registers follow */ -#define CUBE_PP_CUBIC_OFFSET_F1 3 /* 0x2d04 */ -#define CUBE_PP_CUBIC_OFFSET_F2 4 /* 0x2d08 */ -#define CUBE_PP_CUBIC_OFFSET_F3 5 /* 0x2d0c */ -#define CUBE_PP_CUBIC_OFFSET_F4 6 /* 0x2d10 */ -#define CUBE_PP_CUBIC_OFFSET_F5 7 /* 0x2d14 */ -#define CUBE_STATE_SIZE 8 - -#define PIX_CMD_0 0 -#define PIX_PP_TXCBLEND 1 -#define PIX_PP_TXCBLEND2 2 -#define PIX_PP_TXABLEND 3 -#define PIX_PP_TXABLEND2 4 -#define PIX_STATE_SIZE 5 - -#define TF_CMD_0 0 -#define TF_TFACTOR_0 1 -#define TF_TFACTOR_1 2 -#define TF_TFACTOR_2 3 -#define TF_TFACTOR_3 4 -#define TF_TFACTOR_4 5 -#define TF_TFACTOR_5 6 -#define TF_STATE_SIZE 7 - -#define ATF_CMD_0 0 -#define ATF_TFACTOR_0 1 -#define ATF_TFACTOR_1 2 -#define ATF_TFACTOR_2 3 -#define ATF_TFACTOR_3 4 -#define ATF_TFACTOR_4 5 -#define ATF_TFACTOR_5 6 -#define ATF_TFACTOR_6 7 -#define ATF_TFACTOR_7 8 -#define ATF_STATE_SIZE 9 - -/* ATI_FRAGMENT_SHADER */ -#define AFS_CMD_0 0 -#define AFS_IC0 1 /* 2f00 */ -#define AFS_IC1 2 /* 2f04 */ -#define AFS_IA0 3 /* 2f08 */ -#define AFS_IA1 4 /* 2f0c */ -#define AFS_STATE_SIZE 33 - -#define PVS_CMD_0 0 -#define PVS_CNTL_1 1 -#define PVS_CNTL_2 2 -#define PVS_STATE_SIZE 3 - -/* those are quite big... */ -#define VPI_CMD_0 0 -#define VPI_OPDST_0 1 -#define VPI_SRC0_0 2 -#define VPI_SRC1_0 3 -#define VPI_SRC2_0 4 -#define VPI_OPDST_63 253 -#define VPI_SRC0_63 254 -#define VPI_SRC1_63 255 -#define VPI_SRC2_63 256 -#define VPI_STATE_SIZE 257 - -#define VPP_CMD_0 0 -#define VPP_PARAM0_0 1 -#define VPP_PARAM1_0 2 -#define VPP_PARAM2_0 3 -#define VPP_PARAM3_0 4 -#define VPP_PARAM0_95 381 -#define VPP_PARAM1_95 382 -#define VPP_PARAM2_95 383 -#define VPP_PARAM3_95 384 -#define VPP_STATE_SIZE 385 - -#define TCL_CMD_0 0 -#define TCL_LIGHT_MODEL_CTL_0 1 -#define TCL_LIGHT_MODEL_CTL_1 2 -#define TCL_PER_LIGHT_CTL_0 3 -#define TCL_PER_LIGHT_CTL_1 4 -#define TCL_PER_LIGHT_CTL_2 5 -#define TCL_PER_LIGHT_CTL_3 6 -#define TCL_CMD_1 7 -#define TCL_UCP_VERT_BLEND_CTL 8 -#define TCL_STATE_SIZE 9 - -#define MSL_CMD_0 0 -#define MSL_MATRIX_SELECT_0 1 -#define MSL_MATRIX_SELECT_1 2 -#define MSL_MATRIX_SELECT_2 3 -#define MSL_MATRIX_SELECT_3 4 -#define MSL_MATRIX_SELECT_4 5 -#define MSL_STATE_SIZE 6 - -#define TCG_CMD_0 0 -#define TCG_TEX_PROC_CTL_2 1 -#define TCG_TEX_PROC_CTL_3 2 -#define TCG_TEX_PROC_CTL_0 3 -#define TCG_TEX_PROC_CTL_1 4 -#define TCG_TEX_CYL_WRAP_CTL 5 -#define TCG_STATE_SIZE 6 - -#define MTL_CMD_0 0 -#define MTL_EMMISSIVE_RED 1 -#define MTL_EMMISSIVE_GREEN 2 -#define MTL_EMMISSIVE_BLUE 3 -#define MTL_EMMISSIVE_ALPHA 4 -#define MTL_AMBIENT_RED 5 -#define MTL_AMBIENT_GREEN 6 -#define MTL_AMBIENT_BLUE 7 -#define MTL_AMBIENT_ALPHA 8 -#define MTL_DIFFUSE_RED 9 -#define MTL_DIFFUSE_GREEN 10 -#define MTL_DIFFUSE_BLUE 11 -#define MTL_DIFFUSE_ALPHA 12 -#define MTL_SPECULAR_RED 13 -#define MTL_SPECULAR_GREEN 14 -#define MTL_SPECULAR_BLUE 15 -#define MTL_SPECULAR_ALPHA 16 -#define MTL_CMD_1 17 -#define MTL_SHININESS 18 -#define MTL_STATE_SIZE 19 - -#define VAP_CMD_0 0 -#define VAP_SE_VAP_CNTL 1 -#define VAP_STATE_SIZE 2 - -/* Replaces a lot of packet info from radeon - */ -#define VTX_CMD_0 0 -#define VTX_VTXFMT_0 1 -#define VTX_VTXFMT_1 2 -#define VTX_TCL_OUTPUT_VTXFMT_0 3 -#define VTX_TCL_OUTPUT_VTXFMT_1 4 -#define VTX_CMD_1 5 -#define VTX_TCL_OUTPUT_COMPSEL 6 -#define VTX_CMD_2 7 -#define VTX_STATE_CNTL 8 -#define VTX_STATE_SIZE 9 - -/* SPR - point sprite state - */ -#define SPR_CMD_0 0 -#define SPR_POINT_SPRITE_CNTL 1 -#define SPR_STATE_SIZE 2 - -#define PTP_CMD_0 0 -#define PTP_VPORT_SCALE_0 1 -#define PTP_VPORT_SCALE_1 2 -#define PTP_VPORT_SCALE_PTSIZE 3 -#define PTP_VPORT_SCALE_3 4 -#define PTP_CMD_1 5 -#define PTP_ATT_CONST_QUAD 6 -#define PTP_ATT_CONST_LIN 7 -#define PTP_ATT_CONST_CON 8 -#define PTP_ATT_CONST_3 9 -#define PTP_EYE_X 10 -#define PTP_EYE_Y 11 -#define PTP_EYE_Z 12 -#define PTP_EYE_3 13 -#define PTP_CLAMP_MIN 14 -#define PTP_CLAMP_MAX 15 -#define PTP_CLAMP_2 16 -#define PTP_CLAMP_3 17 -#define PTP_STATE_SIZE 18 - -#define VTX_COLOR(v,n) (((v)>>(R200_VTX_COLOR_0_SHIFT+(n)*2))&\ - R200_VTX_COLOR_MASK) - -/** - * Given the \c R200_SE_VTX_FMT_1 for the current vertex state, determine - * how many components are in texture coordinate \c n. - */ -#define VTX_TEXn_COUNT(v,n) (((v) >> (3 * n)) & 0x07) - -#define MAT_CMD_0 0 -#define MAT_ELT_0 1 -#define MAT_STATE_SIZE 17 - -#define GRD_CMD_0 0 -#define GRD_VERT_GUARD_CLIP_ADJ 1 -#define GRD_VERT_GUARD_DISCARD_ADJ 2 -#define GRD_HORZ_GUARD_CLIP_ADJ 3 -#define GRD_HORZ_GUARD_DISCARD_ADJ 4 -#define GRD_STATE_SIZE 5 - -/* position changes frequently when lighting in modelpos - separate - * out to new state item? - */ -#define LIT_CMD_0 0 -#define LIT_AMBIENT_RED 1 -#define LIT_AMBIENT_GREEN 2 -#define LIT_AMBIENT_BLUE 3 -#define LIT_AMBIENT_ALPHA 4 -#define LIT_DIFFUSE_RED 5 -#define LIT_DIFFUSE_GREEN 6 -#define LIT_DIFFUSE_BLUE 7 -#define LIT_DIFFUSE_ALPHA 8 -#define LIT_SPECULAR_RED 9 -#define LIT_SPECULAR_GREEN 10 -#define LIT_SPECULAR_BLUE 11 -#define LIT_SPECULAR_ALPHA 12 -#define LIT_POSITION_X 13 -#define LIT_POSITION_Y 14 -#define LIT_POSITION_Z 15 -#define LIT_POSITION_W 16 -#define LIT_DIRECTION_X 17 -#define LIT_DIRECTION_Y 18 -#define LIT_DIRECTION_Z 19 -#define LIT_DIRECTION_W 20 -#define LIT_ATTEN_QUADRATIC 21 -#define LIT_ATTEN_LINEAR 22 -#define LIT_ATTEN_CONST 23 -#define LIT_ATTEN_XXX 24 -#define LIT_CMD_1 25 -#define LIT_SPOT_DCD 26 -#define LIT_SPOT_DCM 27 -#define LIT_SPOT_EXPONENT 28 -#define LIT_SPOT_CUTOFF 29 -#define LIT_SPECULAR_THRESH 30 -#define LIT_RANGE_CUTOFF 31 /* ? */ -#define LIT_ATTEN_CONST_INV 32 -#define LIT_STATE_SIZE 33 - -/* Fog - */ -#define FOG_CMD_0 0 -#define FOG_R 1 -#define FOG_C 2 -#define FOG_D 3 -#define FOG_PAD 4 -#define FOG_STATE_SIZE 5 - -/* UCP - */ -#define UCP_CMD_0 0 -#define UCP_X 1 -#define UCP_Y 2 -#define UCP_Z 3 -#define UCP_W 4 -#define UCP_STATE_SIZE 5 - -/* GLT - Global ambient - */ -#define GLT_CMD_0 0 -#define GLT_RED 1 -#define GLT_GREEN 2 -#define GLT_BLUE 3 -#define GLT_ALPHA 4 -#define GLT_STATE_SIZE 5 - -/* EYE - */ -#define EYE_CMD_0 0 -#define EYE_X 1 -#define EYE_Y 2 -#define EYE_Z 3 -#define EYE_RESCALE_FACTOR 4 -#define EYE_STATE_SIZE 5 - -/* CST - constant state - */ -#define CST_CMD_0 0 -#define CST_PP_CNTL_X 1 -#define CST_CMD_1 2 -#define CST_RB3D_DEPTHXY_OFFSET 3 -#define CST_CMD_2 4 -#define CST_RE_AUX_SCISSOR_CNTL 5 -#define CST_CMD_4 6 -#define CST_SE_VAP_CNTL_STATUS 7 -#define CST_CMD_5 8 -#define CST_RE_POINTSIZE 9 -#define CST_CMD_6 10 -#define CST_SE_TCL_INPUT_VTX_0 11 -#define CST_SE_TCL_INPUT_VTX_1 12 -#define CST_SE_TCL_INPUT_VTX_2 13 -#define CST_SE_TCL_INPUT_VTX_3 14 -#define CST_STATE_SIZE 15 - -#define PRF_CMD_0 0 -#define PRF_PP_TRI_PERF 1 -#define PRF_PP_PERF_CNTL 2 -#define PRF_STATE_SIZE 3 - - -#define SCI_CMD_1 0 -#define SCI_XY_1 1 -#define SCI_CMD_2 2 -#define SCI_XY_2 3 -#define SCI_STATE_SIZE 4 - -#define R200_QUERYOBJ_CMD_0 0 -#define R200_QUERYOBJ_DATA_0 1 -#define R200_QUERYOBJ_CMDSIZE 2 - -#define STP_CMD_0 0 -#define STP_DATA_0 1 -#define STP_CMD_1 2 -#define STP_STATE_SIZE 35 - -struct r200_hw_state { - /* Hardware state, stored as cmdbuf commands: - * -- Need to doublebuffer for - * - reviving state after loss of context - * - eliding noop statechange loops? (except line stipple count) - */ - struct radeon_state_atom ctx; - struct radeon_state_atom set; - struct radeon_state_atom sci; - struct radeon_state_atom vte; - struct radeon_state_atom lin; - struct radeon_state_atom msk; - struct radeon_state_atom vpt; - struct radeon_state_atom vap; - struct radeon_state_atom vtx; - struct radeon_state_atom tcl; - struct radeon_state_atom msl; - struct radeon_state_atom tcg; - struct radeon_state_atom msc; - struct radeon_state_atom cst; - struct radeon_state_atom tam; - struct radeon_state_atom tf; - struct radeon_state_atom tex[6]; - struct radeon_state_atom cube[6]; - struct radeon_state_atom zbs; - struct radeon_state_atom mtl[2]; - struct radeon_state_atom mat[9]; - struct radeon_state_atom lit[8]; /* includes vec, scl commands */ - struct radeon_state_atom ucp[6]; - struct radeon_state_atom pix[6]; /* pixshader stages */ - struct radeon_state_atom eye; /* eye pos */ - struct radeon_state_atom grd; /* guard band clipping */ - struct radeon_state_atom fog; - struct radeon_state_atom glt; - struct radeon_state_atom prf; - struct radeon_state_atom afs[2]; - struct radeon_state_atom pvs; - struct radeon_state_atom vpi[2]; - struct radeon_state_atom vpp[2]; - struct radeon_state_atom atf; - struct radeon_state_atom spr; - struct radeon_state_atom ptp; - struct radeon_state_atom stp; -}; - -struct r200_state { - /* Derived state for internal purposes: - */ - struct r200_texture_state texture; - GLuint envneeded; -}; - -#define R200_CMD_BUF_SZ (16*1024) - -#define R200_ELT_BUF_SZ (16*1024) -/* r200_tcl.c - */ -struct r200_tcl_info { - GLuint hw_primitive; - - int elt_used; - -}; - - -/* r200_swtcl.c - */ -struct r200_swtcl_info { - - - radeon_point_func draw_point; - radeon_line_func draw_line; - radeon_tri_func draw_tri; - - /** - * Offset of the 4UB color data within a hardware (swtcl) vertex. - */ - GLuint coloroffset; - - /** - * Offset of the 3UB specular color data within a hardware (swtcl) vertex. - */ - GLuint specoffset; - - /** - * Should Mesa project vertex data or will the hardware do it? - */ - GLboolean needproj; -}; - - - - - /* A maximum total of 29 elements per vertex: 3 floats for position, 3 - * floats for normal, 4 floats for color, 4 bytes for secondary color, - * 3 floats for each texture unit (18 floats total). - * - * we maybe need add. 4 to prevent segfault if someone specifies - * GL_TEXTURE6/GL_TEXTURE7 (esp. for the codegen-path) (FIXME: ) - * - * The position data is never actually stored here, so 3 elements could be - * trimmed out of the buffer. - */ - -#define R200_MAX_VERTEX_SIZE ((3*6)+11) - -struct r200_context { - struct radeon_context radeon; - - /* Driver and hardware state management - */ - struct r200_hw_state hw; - struct r200_state state; - struct r200_vertex_program *curr_vp_hw; - - /* Vertex buffers - */ - struct radeon_ioctl ioctl; - struct radeon_store store; - - /* Clientdata textures; - */ - GLuint prefer_gart_client_texturing; - - /* TCL stuff - */ - GLmatrix TexGenMatrix[R200_MAX_TEXTURE_UNITS]; - GLboolean recheck_texgen[R200_MAX_TEXTURE_UNITS]; - GLboolean TexGenNeedNormals[R200_MAX_TEXTURE_UNITS]; - GLuint TexMatEnabled; - GLuint TexMatCompSel; - GLuint TexGenEnabled; - GLuint TexGenCompSel; - GLmatrix tmpmat; - - /* r200_tcl.c - */ - struct r200_tcl_info tcl; - - /* r200_swtcl.c - */ - struct r200_swtcl_info swtcl; - - GLboolean using_hyperz; - - struct ati_fragment_shader *afs_loaded; -}; - - -static inline r200ContextPtr -R200_CONTEXT(struct gl_context *ctx) -{ - return (r200ContextPtr) ctx; -} - - -extern void r200DestroyContext( __DRIcontext *driContextPriv ); -extern GLboolean r200CreateContext( gl_api api, - const struct gl_config *glVisual, - __DRIcontext *driContextPriv, - const struct __DriverContextConfig * - ctx_config, - unsigned *error, - void *sharedContextPrivate); -extern GLboolean r200MakeCurrent( __DRIcontext *driContextPriv, - __DRIdrawable *driDrawPriv, - __DRIdrawable *driReadPriv ); -extern GLboolean r200UnbindContext( __DRIcontext *driContextPriv ); - -extern void r200_init_texcopy_functions(struct dd_function_table *table); - -/* ================================================================ - * Debugging: - */ - -#define R200_DEBUG RADEON_DEBUG - - - -#endif /* __R200_CONTEXT_H__ */ diff --git a/src/mesa/drivers/dri/r200/r200_fragshader.c b/src/mesa/drivers/dri/r200/r200_fragshader.c deleted file mode 100644 index 77ebc854be5..00000000000 --- a/src/mesa/drivers/dri/r200/r200_fragshader.c +++ /dev/null @@ -1,550 +0,0 @@ -/************************************************************************** - * - * Copyright 2004 David Airlie - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL DAVID AIRLIE AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ - -#include "main/glheader.h" -#include "main/atifragshader.h" -#include "main/macros.h" -#include "main/enums.h" -#include "tnl/t_context.h" -#include "program/program.h" -#include "r200_context.h" -#include "r200_ioctl.h" -#include "r200_tex.h" - -#define SET_INST(inst, type) afs_cmd[((inst<<2) + (type<<1) + 1)] -#define SET_INST_2(inst, type) afs_cmd[((inst<<2) + (type<<1) + 2)] - -static void r200SetFragShaderArg( GLuint *afs_cmd, GLuint opnum, GLuint optype, - const struct atifragshader_src_register srcReg, - GLuint argPos, GLuint *tfactor ) -{ - const GLuint index = srcReg.Index; - const GLuint srcmod = srcReg.argMod; - const GLuint srcrep = srcReg.argRep; - GLuint reg0 = 0; - GLuint reg2 = 0; - GLuint useOddSrc = 0; - - switch(srcrep) { - case GL_RED: - reg2 |= R200_TXC_REPL_RED << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos)); - if (optype) - useOddSrc = 1; - break; - case GL_GREEN: - reg2 |= R200_TXC_REPL_GREEN << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos)); - if (optype) - useOddSrc = 1; - break; - case GL_BLUE: - if (!optype) - reg2 |= R200_TXC_REPL_BLUE << (R200_TXC_REPL_ARG_A_SHIFT + (2*argPos)); - else - useOddSrc = 1; - break; - case GL_ALPHA: - if (!optype) - useOddSrc = 1; - break; - } - - if (index >= GL_REG_0_ATI && index <= GL_REG_5_ATI) - reg0 |= (((index - GL_REG_0_ATI)*2) + 10 + useOddSrc) << (5*argPos); - else if (index >= GL_CON_0_ATI && index <= GL_CON_7_ATI) { - if ((*tfactor == 0) || (index == *tfactor)) { - reg0 |= (R200_TXC_ARG_A_TFACTOR_COLOR + useOddSrc) << (5*argPos); - reg2 |= (index - GL_CON_0_ATI) << R200_TXC_TFACTOR_SEL_SHIFT; - *tfactor = index; - } - else { - reg0 |= (R200_TXC_ARG_A_TFACTOR1_COLOR + useOddSrc) << (5*argPos); - reg2 |= (index - GL_CON_0_ATI) << R200_TXC_TFACTOR1_SEL_SHIFT; - } - } - else if (index == GL_PRIMARY_COLOR_EXT) { - reg0 |= (R200_TXC_ARG_A_DIFFUSE_COLOR + useOddSrc) << (5*argPos); - } - else if (index == GL_SECONDARY_INTERPOLATOR_ATI) { - reg0 |= (R200_TXC_ARG_A_SPECULAR_COLOR + useOddSrc) << (5*argPos); - } - /* GL_ZERO is a noop, for GL_ONE we set the complement */ - else if (index == GL_ONE) { - reg0 |= R200_TXC_COMP_ARG_A << (4*argPos); - } - - if (srcmod & GL_COMP_BIT_ATI) - reg0 ^= R200_TXC_COMP_ARG_A << (4*argPos); - if (srcmod & GL_BIAS_BIT_ATI) - reg0 |= R200_TXC_BIAS_ARG_A << (4*argPos); - if (srcmod & GL_2X_BIT_ATI) - reg0 |= R200_TXC_SCALE_ARG_A << (4*argPos); - if (srcmod & GL_NEGATE_BIT_ATI) - reg0 ^= R200_TXC_NEG_ARG_A << (4*argPos); - - SET_INST(opnum, optype) |= reg0; - SET_INST_2(opnum, optype) |= reg2; -} - -static GLuint dstmask_table[9] = -{ - /* first slot never used, GL_NONE translated to RGB by mesa and you can't get a 0 dstmask. */ - R200_TXC_OUTPUT_MASK_RGB, - R200_TXC_OUTPUT_MASK_R, - R200_TXC_OUTPUT_MASK_G, - R200_TXC_OUTPUT_MASK_RG, - R200_TXC_OUTPUT_MASK_B, - R200_TXC_OUTPUT_MASK_RB, - R200_TXC_OUTPUT_MASK_GB, - R200_TXC_OUTPUT_MASK_RGB, - R200_TXC_OUTPUT_MASK_RGB, /* alpha ops */ -}; - -static void r200UpdateFSArith( struct gl_context *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint *afs_cmd; - const struct ati_fragment_shader *shader = ctx->ATIFragmentShader.Current; - GLuint pass; - - R200_STATECHANGE( rmesa, afs[0] ); - R200_STATECHANGE( rmesa, afs[1] ); - - if (shader->NumPasses < 2) { - afs_cmd = (GLuint *) rmesa->hw.afs[1].cmd; - } - else { - afs_cmd = (GLuint *) rmesa->hw.afs[0].cmd; - } - for (pass = 0; pass < shader->NumPasses; pass++) { - GLuint opnum = 0; - GLuint pc; - for (pc = 0; pc < shader->numArithInstr[pass]; pc++) { - GLuint optype; - struct atifs_instruction *inst = &shader->Instructions[pass][pc]; - - SET_INST(opnum, 0) = 0; - SET_INST_2(opnum, 0) = 0; - SET_INST(opnum, 1) = 0; - SET_INST_2(opnum, 1) = 0; - - for (optype = 0; optype < 2; optype++) { - GLuint tfactor = 0; - - if (inst->Opcode[optype]) { - switch (inst->Opcode[optype]) { - /* these are all MADD in disguise - MADD is A * B + C - so for GL_ADD use arg B/C and make A complement 0 - for GL_SUB use arg B/C, negate C and make A complement 0 - for GL_MOV use arg C - for GL_MUL use arg A - for GL_MAD all good */ - case GL_SUB_ATI: - /* negate C */ - SET_INST(opnum, optype) |= R200_TXC_NEG_ARG_C; - FALLTHROUGH; - case GL_ADD_ATI: - r200SetFragShaderArg(afs_cmd, opnum, optype, - inst->SrcReg[optype][0], 1, &tfactor); - r200SetFragShaderArg(afs_cmd, opnum, optype, - inst->SrcReg[optype][1], 2, &tfactor); - /* A = complement 0 */ - SET_INST(opnum, optype) |= R200_TXC_COMP_ARG_A; - SET_INST(opnum, optype) |= R200_TXC_OP_MADD; - break; - case GL_MOV_ATI: - /* put arg0 in C */ - r200SetFragShaderArg(afs_cmd, opnum, optype, - inst->SrcReg[optype][0], 2, &tfactor); - SET_INST(opnum, optype) |= R200_TXC_OP_MADD; - break; - case GL_MAD_ATI: - r200SetFragShaderArg(afs_cmd, opnum, optype, - inst->SrcReg[optype][2], 2, &tfactor); - FALLTHROUGH; - case GL_MUL_ATI: - r200SetFragShaderArg(afs_cmd, opnum, optype, - inst->SrcReg[optype][0], 0, &tfactor); - r200SetFragShaderArg(afs_cmd, opnum, optype, - inst->SrcReg[optype][1], 1, &tfactor); - SET_INST(opnum, optype) |= R200_TXC_OP_MADD; - break; - case GL_LERP_ATI: - /* arg order is not native chip order, swap A and C */ - r200SetFragShaderArg(afs_cmd, opnum, optype, - inst->SrcReg[optype][0], 2, &tfactor); - r200SetFragShaderArg(afs_cmd, opnum, optype, - inst->SrcReg[optype][1], 1, &tfactor); - r200SetFragShaderArg(afs_cmd, opnum, optype, - inst->SrcReg[optype][2], 0, &tfactor); - SET_INST(opnum, optype) |= R200_TXC_OP_LERP; - break; - case GL_CND_ATI: - r200SetFragShaderArg(afs_cmd, opnum, optype, - inst->SrcReg[optype][0], 0, &tfactor); - r200SetFragShaderArg(afs_cmd, opnum, optype, - inst->SrcReg[optype][1], 1, &tfactor); - r200SetFragShaderArg(afs_cmd, opnum, optype, - inst->SrcReg[optype][2], 2, &tfactor); - SET_INST(opnum, optype) |= R200_TXC_OP_CONDITIONAL; - break; - case GL_CND0_ATI: - r200SetFragShaderArg(afs_cmd, opnum, optype, - inst->SrcReg[optype][0], 0, &tfactor); - r200SetFragShaderArg(afs_cmd, opnum, optype, - inst->SrcReg[optype][1], 1, &tfactor); - r200SetFragShaderArg(afs_cmd, opnum, optype, - inst->SrcReg[optype][2], 2, &tfactor); - SET_INST(opnum, optype) |= R200_TXC_OP_CND0; - break; - /* cannot specify dot ops as alpha ops directly */ - case GL_DOT2_ADD_ATI: - if (optype) - SET_INST_2(opnum, 1) |= R200_TXA_DOT_ALPHA; - else { - r200SetFragShaderArg(afs_cmd, opnum, 0, - inst->SrcReg[0][0], 0, &tfactor); - r200SetFragShaderArg(afs_cmd, opnum, 0, - inst->SrcReg[0][1], 1, &tfactor); - r200SetFragShaderArg(afs_cmd, opnum, 0, - inst->SrcReg[0][2], 2, &tfactor); - SET_INST(opnum, 0) |= R200_TXC_OP_DOT2_ADD; - } - break; - case GL_DOT3_ATI: - if (optype) - SET_INST_2(opnum, 1) |= R200_TXA_DOT_ALPHA; - else { - r200SetFragShaderArg(afs_cmd, opnum, 0, - inst->SrcReg[0][0], 0, &tfactor); - r200SetFragShaderArg(afs_cmd, opnum, 0, - inst->SrcReg[0][1], 1, &tfactor); - SET_INST(opnum, 0) |= R200_TXC_OP_DOT3; - } - break; - case GL_DOT4_ATI: - /* experimental verification: for dot4 setup of alpha args is needed - (dstmod is ignored, though, so dot2/dot3 should be safe) - the hardware apparently does R1*R2 + G1*G2 + B1*B2 + A3*A4 - but the API doesn't allow it */ - if (optype) - SET_INST_2(opnum, 1) |= R200_TXA_DOT_ALPHA; - else { - r200SetFragShaderArg(afs_cmd, opnum, 0, - inst->SrcReg[0][0], 0, &tfactor); - r200SetFragShaderArg(afs_cmd, opnum, 0, - inst->SrcReg[0][1], 1, &tfactor); - r200SetFragShaderArg(afs_cmd, opnum, 1, - inst->SrcReg[0][0], 0, &tfactor); - r200SetFragShaderArg(afs_cmd, opnum, 1, - inst->SrcReg[0][1], 1, &tfactor); - SET_INST(opnum, optype) |= R200_TXC_OP_DOT4; - } - break; - } - } - - /* destination */ - if (inst->DstReg[optype].Index) { - GLuint dstreg = inst->DstReg[optype].Index - GL_REG_0_ATI; - GLuint dstmask = inst->DstReg[optype].dstMask; - GLuint sat = inst->DstReg[optype].dstMod & GL_SATURATE_BIT_ATI; - GLuint dstmod = inst->DstReg[optype].dstMod; - - dstmod &= ~GL_SATURATE_BIT_ATI; - - SET_INST_2(opnum, optype) |= (dstreg + 1) << R200_TXC_OUTPUT_REG_SHIFT; - SET_INST_2(opnum, optype) |= dstmask_table[dstmask]; - - /* fglrx does clamp the last instructions to 0_1 it seems */ - /* this won't necessarily catch the last instruction - which writes to reg0 */ - if (sat || (pc == (shader->numArithInstr[pass] - 1) && - ((pass == 1) || (shader->NumPasses == 1)))) - SET_INST_2(opnum, optype) |= R200_TXC_CLAMP_0_1; - else - /*should we clamp or not? spec is vague, I would suppose yes but fglrx doesn't */ - SET_INST_2(opnum, optype) |= R200_TXC_CLAMP_8_8; -/* SET_INST_2(opnum, optype) |= R200_TXC_CLAMP_WRAP;*/ - switch(dstmod) { - case GL_2X_BIT_ATI: - SET_INST_2(opnum, optype) |= R200_TXC_SCALE_2X; - break; - case GL_4X_BIT_ATI: - SET_INST_2(opnum, optype) |= R200_TXC_SCALE_4X; - break; - case GL_8X_BIT_ATI: - SET_INST_2(opnum, optype) |= R200_TXC_SCALE_8X; - break; - case GL_HALF_BIT_ATI: - SET_INST_2(opnum, optype) |= R200_TXC_SCALE_INV2; - break; - case GL_QUARTER_BIT_ATI: - SET_INST_2(opnum, optype) |= R200_TXC_SCALE_INV4; - break; - case GL_EIGHTH_BIT_ATI: - SET_INST_2(opnum, optype) |= R200_TXC_SCALE_INV8; - break; - default: - break; - } - } - } -/* fprintf(stderr, "pass %d nr %d inst 0x%.8x 0x%.8x 0x%.8x 0x%.8x\n", - pass, opnum, SET_INST(opnum, 0), SET_INST_2(opnum, 0), - SET_INST(opnum, 1), SET_INST_2(opnum, 1));*/ - opnum++; - } - afs_cmd = (GLuint *) rmesa->hw.afs[1].cmd; - } - rmesa->afs_loaded = ctx->ATIFragmentShader.Current; -} - -static void r200UpdateFSRouting( struct gl_context *ctx ) { - r200ContextPtr rmesa = R200_CONTEXT(ctx); - const struct ati_fragment_shader *shader = ctx->ATIFragmentShader.Current; - GLuint reg; - - R200_STATECHANGE( rmesa, ctx ); - R200_STATECHANGE( rmesa, cst ); - - for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg++) { - if (shader->swizzlerq & (1 << (2 * reg))) - /* r coord */ - set_re_cntl_d3d( ctx, reg, 1); - /* q coord */ - else set_re_cntl_d3d( ctx, reg, 0); - } - - rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~(R200_MULTI_PASS_ENABLE | - R200_TEX_BLEND_ENABLE_MASK | - R200_TEX_ENABLE_MASK); - rmesa->hw.cst.cmd[CST_PP_CNTL_X] &= ~(R200_PPX_PFS_INST_ENABLE_MASK | - R200_PPX_TEX_ENABLE_MASK | - R200_PPX_OUTPUT_REG_MASK); - - /* first pass registers use slots 8 - 15 - but single pass shaders use slots 0 - 7 */ - if (shader->NumPasses < 2) { - rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= shader->numArithInstr[0] == 8 ? - 0xff << (R200_TEX_BLEND_0_ENABLE_SHIFT - 1) : - (0xff >> (8 - shader->numArithInstr[0])) << R200_TEX_BLEND_0_ENABLE_SHIFT; - } else { - rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_MULTI_PASS_ENABLE; - rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= shader->numArithInstr[1] == 8 ? - 0xff << (R200_TEX_BLEND_0_ENABLE_SHIFT - 1) : - (0xff >> (8 - shader->numArithInstr[1])) << R200_TEX_BLEND_0_ENABLE_SHIFT; - rmesa->hw.cst.cmd[CST_PP_CNTL_X] |= - (0xff >> (8 - shader->numArithInstr[0])) << R200_PPX_FPS_INST0_ENABLE_SHIFT; - } - - if (shader->NumPasses < 2) { - for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg++) { - struct gl_texture_object *texObj = ctx->Texture.Unit[reg]._Current; - R200_STATECHANGE( rmesa, tex[reg] ); - rmesa->hw.tex[reg].cmd[TEX_PP_TXMULTI_CTL] = 0; - if (shader->SetupInst[0][reg].Opcode) { - GLuint txformat = rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT] - & ~(R200_TXFORMAT_ST_ROUTE_MASK | R200_TXFORMAT_LOOKUP_DISABLE); - GLuint txformat_x = rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT_X] & ~R200_TEXCOORD_MASK; - txformat |= (shader->SetupInst[0][reg].src - GL_TEXTURE0_ARB) - << R200_TXFORMAT_ST_ROUTE_SHIFT; - /* fix up texcoords for proj/non-proj 2d (3d and cube are not defined when - using projection so don't have to worry there). - When passing coords, need R200_TEXCOORD_VOLUME, otherwise loose a coord */ - /* FIXME: someone might rely on default tex coords r/q, which we unfortunately - don't provide (we have the same problem without shaders) */ - if (shader->SetupInst[0][reg].Opcode == ATI_FRAGMENT_SHADER_PASS_OP) { - txformat |= R200_TXFORMAT_LOOKUP_DISABLE; - if (shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STR_ATI || - shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STQ_ATI) { - txformat_x |= R200_TEXCOORD_VOLUME; - } - else { - txformat_x |= R200_TEXCOORD_PROJ; - } - rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg; - } - else if (texObj && texObj->Target == GL_TEXTURE_3D) { - txformat_x |= R200_TEXCOORD_VOLUME; - } - else if (texObj && texObj->Target == GL_TEXTURE_CUBE_MAP) { - txformat_x |= R200_TEXCOORD_CUBIC_ENV; - } - else if (shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STR_ATI || - shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STQ_ATI) { - txformat_x |= R200_TEXCOORD_NONPROJ; - } - else { - txformat_x |= R200_TEXCOORD_PROJ; - } - rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT] = txformat; - rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT_X] = txformat_x; - /* enabling texturing when unit isn't correctly configured may not be safe */ - if (texObj) - rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg; - } - } - - } else { - /* setup 1st pass */ - for (reg = 0; reg < R200_MAX_TEXTURE_UNITS; reg++) { - struct gl_texture_object *texObj = ctx->Texture.Unit[reg]._Current; - R200_STATECHANGE( rmesa, tex[reg] ); - GLuint txformat_multi = 0; - if (shader->SetupInst[0][reg].Opcode) { - txformat_multi |= (shader->SetupInst[0][reg].src - GL_TEXTURE0_ARB) - << R200_PASS1_ST_ROUTE_SHIFT; - if (shader->SetupInst[0][reg].Opcode == ATI_FRAGMENT_SHADER_PASS_OP) { - txformat_multi |= R200_PASS1_TXFORMAT_LOOKUP_DISABLE; - if (shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STR_ATI || - shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STQ_ATI) { - txformat_multi |= R200_PASS1_TEXCOORD_VOLUME; - } - else { - txformat_multi |= R200_PASS1_TEXCOORD_PROJ; - } - rmesa->hw.cst.cmd[CST_PP_CNTL_X] |= R200_PPX_TEX_0_ENABLE << reg; - } - else if (texObj && texObj->Target == GL_TEXTURE_3D) { - txformat_multi |= R200_PASS1_TEXCOORD_VOLUME; - } - else if (texObj && texObj->Target == GL_TEXTURE_CUBE_MAP) { - txformat_multi |= R200_PASS1_TEXCOORD_CUBIC_ENV; - } - else if (shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STR_ATI || - shader->SetupInst[0][reg].swizzle == GL_SWIZZLE_STQ_ATI) { - txformat_multi |= R200_PASS1_TEXCOORD_NONPROJ; - } - else { - txformat_multi |= R200_PASS1_TEXCOORD_PROJ; - } - if (texObj) - rmesa->hw.cst.cmd[CST_PP_CNTL_X] |= R200_PPX_TEX_0_ENABLE << reg; - } - rmesa->hw.tex[reg].cmd[TEX_PP_TXMULTI_CTL] = txformat_multi; - } - - /* setup 2nd pass */ - for (reg=0; reg < R200_MAX_TEXTURE_UNITS; reg++) { - struct gl_texture_object *texObj = ctx->Texture.Unit[reg]._Current; - if (shader->SetupInst[1][reg].Opcode) { - GLuint coord = shader->SetupInst[1][reg].src; - GLuint txformat = rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT] - & ~(R200_TXFORMAT_ST_ROUTE_MASK | R200_TXFORMAT_LOOKUP_DISABLE); - GLuint txformat_x = rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT_X] & ~R200_TEXCOORD_MASK; - R200_STATECHANGE( rmesa, tex[reg] ); - if (shader->SetupInst[1][reg].Opcode == ATI_FRAGMENT_SHADER_PASS_OP) { - txformat |= R200_TXFORMAT_LOOKUP_DISABLE; - txformat_x |= R200_TEXCOORD_VOLUME; - if (shader->SetupInst[1][reg].swizzle == GL_SWIZZLE_STR_ATI || - shader->SetupInst[1][reg].swizzle == GL_SWIZZLE_STQ_ATI) { - txformat_x |= R200_TEXCOORD_VOLUME; - } - else { - txformat_x |= R200_TEXCOORD_PROJ; - } - rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg; - } - else if (texObj && texObj->Target == GL_TEXTURE_3D) { - txformat_x |= R200_TEXCOORD_VOLUME; - } - else if (texObj && texObj->Target == GL_TEXTURE_CUBE_MAP) { - txformat_x |= R200_TEXCOORD_CUBIC_ENV; - } - else if (shader->SetupInst[1][reg].swizzle == GL_SWIZZLE_STR_ATI || - shader->SetupInst[1][reg].swizzle == GL_SWIZZLE_STQ_ATI) { - txformat_x |= R200_TEXCOORD_NONPROJ; - } - else { - txformat_x |= R200_TEXCOORD_PROJ; - } - if (coord >= GL_REG_0_ATI) { - GLuint txformat_multi = rmesa->hw.tex[reg].cmd[TEX_PP_TXMULTI_CTL]; - txformat_multi |= (coord - GL_REG_0_ATI + 2) << R200_PASS2_COORDS_REG_SHIFT; - rmesa->hw.tex[reg].cmd[TEX_PP_TXMULTI_CTL] = txformat_multi; - rmesa->hw.cst.cmd[CST_PP_CNTL_X] |= 1 << - (R200_PPX_OUTPUT_REG_0_SHIFT + coord - GL_REG_0_ATI); - } else { - txformat |= (coord - GL_TEXTURE0_ARB) << R200_TXFORMAT_ST_ROUTE_SHIFT; - } - rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT_X] = txformat_x; - rmesa->hw.tex[reg].cmd[TEX_PP_TXFORMAT] = txformat; - if (texObj) - rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << reg; - } - } - } -} - -static void r200UpdateFSConstants( struct gl_context *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - const struct ati_fragment_shader *shader = ctx->ATIFragmentShader.Current; - GLuint i; - - /* update constants */ - R200_STATECHANGE(rmesa, atf); - for (i = 0; i < 8; i++) - { - GLubyte con_byte[4]; - if ((shader->LocalConstDef >> i) & 1) { - CLAMPED_FLOAT_TO_UBYTE(con_byte[0], shader->Constants[i][0]); - CLAMPED_FLOAT_TO_UBYTE(con_byte[1], shader->Constants[i][1]); - CLAMPED_FLOAT_TO_UBYTE(con_byte[2], shader->Constants[i][2]); - CLAMPED_FLOAT_TO_UBYTE(con_byte[3], shader->Constants[i][3]); - } - else { - CLAMPED_FLOAT_TO_UBYTE(con_byte[0], ctx->ATIFragmentShader.GlobalConstants[i][0]); - CLAMPED_FLOAT_TO_UBYTE(con_byte[1], ctx->ATIFragmentShader.GlobalConstants[i][1]); - CLAMPED_FLOAT_TO_UBYTE(con_byte[2], ctx->ATIFragmentShader.GlobalConstants[i][2]); - CLAMPED_FLOAT_TO_UBYTE(con_byte[3], ctx->ATIFragmentShader.GlobalConstants[i][3]); - } - rmesa->hw.atf.cmd[ATF_TFACTOR_0 + i] = radeonPackColor ( - 4, con_byte[0], con_byte[1], con_byte[2], con_byte[3] ); - } -} - -/* update routing, constants and arithmetic - * constants need to be updated always (globals can change, no separate notification) - * routing needs to be updated always too (non-shader code will overwrite state, plus - * some of the routing depends on what sort of texture is bound) - * for both of them, we need to update anyway because of disabling/enabling ati_fs which - * we'd need to track otherwise - * arithmetic is only updated if current shader changes (and probably the data should be - * stored in some DriverData object attached to the mesa atifs object, i.e. binding a - * shader wouldn't force us to "recompile" the shader). - */ -void r200UpdateFragmentShader( struct gl_context *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - r200UpdateFSConstants( ctx ); - r200UpdateFSRouting( ctx ); - if (rmesa->afs_loaded != ctx->ATIFragmentShader.Current) - r200UpdateFSArith( ctx ); -} diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.c b/src/mesa/drivers/dri/r200/r200_ioctl.c deleted file mode 100644 index b6643e1f9ea..00000000000 --- a/src/mesa/drivers/dri/r200/r200_ioctl.c +++ /dev/null @@ -1,88 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell <keithw@vmware.com> - */ - -#include <sched.h> -#include <errno.h> - -#include "main/glheader.h" - -#include "main/macros.h" -#include "main/context.h" -#include "swrast/swrast.h" - - - -#include "radeon_common.h" -#include "r200_context.h" -#include "r200_ioctl.h" -#include "radeon_reg.h" - -#define R200_TIMEOUT 512 -#define R200_IDLE_RETRY 16 - -/* ================================================================ - * Buffer clear - */ -static void r200Clear( struct gl_context *ctx, GLbitfield mask ) -{ - GLuint hwmask, swmask; - GLuint hwbits = BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT | - BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL | - BUFFER_BIT_COLOR0; - - radeonFlush( ctx, 0 ); - - hwmask = mask & hwbits; - swmask = mask & ~hwbits; - - if ( swmask ) { - if (R200_DEBUG & RADEON_FALLBACKS) - fprintf(stderr, "%s: swrast clear, mask: %x\n", __func__, swmask); - _swrast_Clear( ctx, swmask ); - } - - if ( !hwmask ) - return; - - radeonUserClear(ctx, hwmask); -} - - -void r200InitIoctlFuncs( struct dd_function_table *functions ) -{ - functions->Clear = r200Clear; - functions->Finish = radeonFinish; - functions->Flush = radeonFlush; -} - diff --git a/src/mesa/drivers/dri/r200/r200_ioctl.h b/src/mesa/drivers/dri/r200/r200_ioctl.h deleted file mode 100644 index d3cb1eae8f8..00000000000 --- a/src/mesa/drivers/dri/r200/r200_ioctl.h +++ /dev/null @@ -1,155 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell <keithw@vmware.com> - */ - -#ifndef __R200_IOCTL_H__ -#define __R200_IOCTL_H__ - -#include "radeon_bo_gem.h" -#include "radeon_cs_gem.h" - -#include "xf86drm.h" -#include "drm-uapi/drm.h" -#include "radeon_drm.h" - -extern void r200EmitMaxVtxIndex(r200ContextPtr rmesa, int count); -extern void r200EmitVertexAOS( r200ContextPtr rmesa, - GLuint vertex_size, - struct radeon_bo *bo, - GLuint offset ); - -extern void r200EmitVbufPrim( r200ContextPtr rmesa, - GLuint primitive, - GLuint vertex_nr ); - -extern void r200FlushElts(struct gl_context *ctx); - -extern GLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, - GLuint primitive, - GLuint min_nr ); - -extern void r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset); - -extern void r200InitIoctlFuncs( struct dd_function_table *functions ); - -void r200SetUpAtomList( r200ContextPtr rmesa ); - -/* ================================================================ - * Helper macros: - */ - -/* Close off the last primitive, if it exists. - */ -#define R200_NEWPRIM( rmesa ) \ -do { \ - if ( rmesa->radeon.dma.flush ) \ - rmesa->radeon.dma.flush( &rmesa->radeon.glCtx ); \ -} while (0) - -/* Can accommodate several state changes and primitive changes without - * actually firing the buffer. - */ -#define R200_STATECHANGE( rmesa, ATOM ) \ -do { \ - R200_NEWPRIM( rmesa ); \ - rmesa->hw.ATOM.dirty = GL_TRUE; \ - rmesa->radeon.hw.is_dirty = GL_TRUE; \ -} while (0) - -#define R200_SET_STATE( rmesa, ATOM, index, newvalue ) \ - do { \ - uint32_t __index = (index); \ - uint32_t __dword = (newvalue); \ - if (__dword != (rmesa)->hw.ATOM.cmd[__index]) { \ - R200_STATECHANGE( (rmesa), ATOM ); \ - (rmesa)->hw.ATOM.cmd[__index] = __dword; \ - } \ - } while(0) - -#define R200_DB_STATE( ATOM ) \ - memcpy( rmesa->hw.ATOM.lastcmd, rmesa->hw.ATOM.cmd, \ - rmesa->hw.ATOM.cmd_size * 4) - -static inline int R200_DB_STATECHANGE( - r200ContextPtr rmesa, - struct radeon_state_atom *atom ) -{ - if (memcmp(atom->cmd, atom->lastcmd, atom->cmd_size*4)) { - GLuint *tmp; - R200_NEWPRIM( rmesa ); - atom->dirty = GL_TRUE; - rmesa->radeon.hw.is_dirty = GL_TRUE; - tmp = atom->cmd; - atom->cmd = atom->lastcmd; - atom->lastcmd = tmp; - return 1; - } - else - return 0; -} - - -/* Command lengths. Note that any time you ensure ELTS_BUFSZ or VBUF_BUFSZ - * are available, you will also be adding an rmesa->state.max_state_size because - * r200EmitState is called from within r200EmitVbufPrim and r200FlushElts. - */ -#define AOS_BUFSZ(nr) ((3 + ((nr / 2) * 3) + ((nr & 1) * 2) + nr*2)) -#define VERT_AOS_BUFSZ (5) -#define ELTS_BUFSZ(nr) (12 + nr * 2) -#define VBUF_BUFSZ (3) -#define SCISSOR_BUFSZ (8) -#define INDEX_BUFSZ (8+2) - -static inline uint32_t cmdpacket3(int cmd_type) -{ - drm_radeon_cmd_header_t cmd; - - cmd.i = 0; - cmd.header.cmd_type = cmd_type; - - return (uint32_t)cmd.i; - -} - -#define OUT_BATCH_PACKET3(packet, num_extra) do { \ - OUT_BATCH(CP_PACKET2); \ - OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ - } while(0) - -#define OUT_BATCH_PACKET3_CLIP(packet, num_extra) do { \ - OUT_BATCH(CP_PACKET2); \ - OUT_BATCH(CP_PACKET3((packet), (num_extra))); \ - } while(0) - - -#endif /* __R200_IOCTL_H__ */ diff --git a/src/mesa/drivers/dri/r200/r200_maos.c b/src/mesa/drivers/dri/r200/r200_maos.c deleted file mode 100644 index 23e1c962a16..00000000000 --- a/src/mesa/drivers/dri/r200/r200_maos.c +++ /dev/null @@ -1,15 +0,0 @@ - - -/* Currently, can only use arrays, verts are not implemented, though - * verts are suspected to be faster. - * To get an idea how the verts path works, look at the radeon implementation. - */ -#include <string.h> - -#include "r200_context.h" -#define R200_MAOS_VERTS 0 -#if (R200_MAOS_VERTS) -#include "r200_maos_verts.c" -#else -#include "r200_maos_arrays.c" -#endif diff --git a/src/mesa/drivers/dri/r200/r200_maos.h b/src/mesa/drivers/dri/r200/r200_maos.h deleted file mode 100644 index 55c7a274120..00000000000 --- a/src/mesa/drivers/dri/r200/r200_maos.h +++ /dev/null @@ -1,42 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell <keithw@vmware.com> - */ - -#ifndef __R200_MAOS_H__ -#define __R200_MAOS_H__ - -#include "r200_context.h" - -extern void r200EmitArrays( struct gl_context *ctx, GLubyte *vimap_rev ); - -#endif diff --git a/src/mesa/drivers/dri/r200/r200_maos_arrays.c b/src/mesa/drivers/dri/r200/r200_maos_arrays.c deleted file mode 100644 index 717c2c3897d..00000000000 --- a/src/mesa/drivers/dri/r200/r200_maos_arrays.c +++ /dev/null @@ -1,196 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell <keithw@vmware.com> - */ - -#include "main/glheader.h" -#include "main/mtypes.h" - -#include "main/macros.h" -#include "main/state.h" - -#include "swrast_setup/swrast_setup.h" -#include "math/m_translate.h" -#include "tnl/tnl.h" -#include "tnl/t_context.h" - -#include "r200_context.h" -#include "r200_ioctl.h" -#include "r200_state.h" -#include "r200_swtcl.h" -#include "r200_maos.h" -#include "r200_tcl.h" - -#if defined(USE_X86_ASM) -#define COPY_DWORDS( dst, src, nr ) \ -do { \ - int __tmp; \ - __asm__ __volatile__( "rep ; movsl" \ - : "=%c" (__tmp), "=D" (dst), "=S" (__tmp) \ - : "0" (nr), \ - "D" ((long)dst), \ - "S" ((long)src) ); \ -} while (0) -#else -#define COPY_DWORDS( dst, src, nr ) \ -do { \ - int j; \ - for ( j = 0 ; j < nr ; j++ ) \ - dst[j] = ((int *)src)[j]; \ - dst += nr; \ -} while (0) -#endif - -/* Emit any changed arrays to new GART memory, re-emit a packet to - * update the arrays. - */ -void r200EmitArrays( struct gl_context *ctx, GLubyte *vimap_rev ) -{ - r200ContextPtr rmesa = R200_CONTEXT( ctx ); - struct vertex_buffer *VB = &TNL_CONTEXT( ctx )->vb; - GLuint nr = 0; - GLuint vfmt0 = 0, vfmt1 = 0; - GLuint count = VB->Count; - GLuint i, emitsize; - - // fprintf(stderr,"emit arrays\n"); - for ( i = 0; i < 15; i++ ) { - GLubyte attrib = vimap_rev[i]; - if (attrib != 255) { - switch (i) { - case 0: - emitsize = (VB->AttribPtr[attrib]->size); - switch (emitsize) { - case 4: - vfmt0 |= R200_VTX_W0; - FALLTHROUGH; - case 3: - vfmt0 |= R200_VTX_Z0; - break; - case 2: - break; - default: assert(0); - } - break; - case 1: - unreachable("r200: vertex weight attrib unsupported"); - break; - case 2: - assert(attrib == VERT_ATTRIB_NORMAL); - emitsize = 3; - vfmt0 |= R200_VTX_N0; - break; - case 3: - /* special handling to fix up fog. Will get us into trouble with vbos...*/ - assert(attrib == VERT_ATTRIB_FOG); - if (!rmesa->radeon.tcl.aos[i].bo) { - if (_mesa_arb_vertex_program_enabled(ctx)) - rcommon_emit_vector( ctx, - &(rmesa->radeon.tcl.aos[nr]), - (char *)VB->AttribPtr[attrib]->data, - 1, - VB->AttribPtr[attrib]->stride, - count); - else - rcommon_emit_vecfog( ctx, - &(rmesa->radeon.tcl.aos[nr]), - (char *)VB->AttribPtr[attrib]->data, - VB->AttribPtr[attrib]->stride, - count); - } - vfmt0 |= R200_VTX_DISCRETE_FOG; - goto after_emit; - break; - case 4: - case 5: - case 6: - case 7: - if (VB->AttribPtr[attrib]->size == 4 && - (VB->AttribPtr[attrib]->stride != 0 || - VB->AttribPtr[attrib]->data[0][3] != 1.0)) emitsize = 4; - else emitsize = 3; - if (emitsize == 4) - vfmt0 |= R200_VTX_FP_RGBA << (R200_VTX_COLOR_0_SHIFT + (i - 4) * 2); - else { - vfmt0 |= R200_VTX_FP_RGB << (R200_VTX_COLOR_0_SHIFT + (i - 4) * 2); - } - break; - case 8: - case 9: - case 10: - case 11: - case 12: - case 13: - emitsize = VB->AttribPtr[attrib]->size; - vfmt1 |= emitsize << (R200_VTX_TEX0_COMP_CNT_SHIFT + (i - 8) * 3); - break; - case 14: - emitsize = VB->AttribPtr[attrib]->size >= 2 ? VB->AttribPtr[attrib]->size : 2; - switch (emitsize) { - case 2: - vfmt0 |= R200_VTX_XY1; - FALLTHROUGH; - case 3: - vfmt0 |= R200_VTX_Z1; - FALLTHROUGH; - case 4: - vfmt0 |= R200_VTX_W1; - } - break; - default: - assert(0); - emitsize = 0; - } - if (!rmesa->radeon.tcl.aos[nr].bo) { - rcommon_emit_vector( ctx, - &(rmesa->radeon.tcl.aos[nr]), - (char *)VB->AttribPtr[attrib]->data, - emitsize, - VB->AttribPtr[attrib]->stride, - count ); - } -after_emit: - assert(nr < 12); - nr++; - } - } - - if (vfmt0 != rmesa->hw.vtx.cmd[VTX_VTXFMT_0] || - vfmt1 != rmesa->hw.vtx.cmd[VTX_VTXFMT_1]) { - R200_STATECHANGE( rmesa, vtx ); - rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = vfmt0; - rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = vfmt1; - } - - rmesa->radeon.tcl.aos_count = nr; -} - diff --git a/src/mesa/drivers/dri/r200/r200_reg.h b/src/mesa/drivers/dri/r200/r200_reg.h deleted file mode 100644 index e331be223b8..00000000000 --- a/src/mesa/drivers/dri/r200/r200_reg.h +++ /dev/null @@ -1,1597 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - -#ifndef _R200_REG_H_ -#define _R200_REG_H_ - -#define R200_PP_MISC 0x1c14 -#define R200_REF_ALPHA_MASK 0x000000ff -#define R200_ALPHA_TEST_FAIL (0 << 8) -#define R200_ALPHA_TEST_LESS (1 << 8) -#define R200_ALPHA_TEST_LEQUAL (2 << 8) -#define R200_ALPHA_TEST_EQUAL (3 << 8) -#define R200_ALPHA_TEST_GEQUAL (4 << 8) -#define R200_ALPHA_TEST_GREATER (5 << 8) -#define R200_ALPHA_TEST_NEQUAL (6 << 8) -#define R200_ALPHA_TEST_PASS (7 << 8) -#define R200_ALPHA_TEST_OP_MASK (7 << 8) -#define R200_CHROMA_FUNC_FAIL (0 << 16) -#define R200_CHROMA_FUNC_PASS (1 << 16) -#define R200_CHROMA_FUNC_NEQUAL (2 << 16) -#define R200_CHROMA_FUNC_EQUAL (3 << 16) -#define R200_CHROMA_KEY_NEAREST (0 << 18) -#define R200_CHROMA_KEY_ZERO (1 << 18) -#define R200_RIGHT_HAND_CUBE_D3D (0 << 24) -#define R200_RIGHT_HAND_CUBE_OGL (1 << 24) -#define R200_PP_FOG_COLOR 0x1c18 -#define R200_FOG_COLOR_MASK 0x00ffffff -#define R200_FOG_VERTEX (0 << 24) -#define R200_FOG_TABLE (1 << 24) -#define R200_FOG_USE_DEPTH (0 << 25) -#define R200_FOG_USE_W (1 << 25) -#define R200_FOG_USE_DIFFUSE_ALPHA (2 << 25) -#define R200_FOG_USE_SPEC_ALPHA (3 << 25) -#define R200_FOG_USE_VTX_FOG (4 << 25) -#define R200_FOG_USE_MASK (7 << 25) -#define R200_RE_SOLID_COLOR 0x1c1c -#define R200_RB3D_BLENDCNTL 0x1c20 -#define R200_COMB_FCN_MASK (7 << 12) -#define R200_COMB_FCN_ADD_CLAMP (0 << 12) -#define R200_COMB_FCN_ADD_NOCLAMP (1 << 12) -#define R200_COMB_FCN_SUB_CLAMP (2 << 12) -#define R200_COMB_FCN_SUB_NOCLAMP (3 << 12) -#define R200_COMB_FCN_MIN (4 << 12) -#define R200_COMB_FCN_MAX (5 << 12) -#define R200_COMB_FCN_RSUB_CLAMP (6 << 12) -#define R200_COMB_FCN_RSUB_NOCLAMP (7 << 12) -#define R200_BLEND_GL_ZERO (32) -#define R200_BLEND_GL_ONE (33) -#define R200_BLEND_GL_SRC_COLOR (34) -#define R200_BLEND_GL_ONE_MINUS_SRC_COLOR (35) -#define R200_BLEND_GL_DST_COLOR (36) -#define R200_BLEND_GL_ONE_MINUS_DST_COLOR (37) -#define R200_BLEND_GL_SRC_ALPHA (38) -#define R200_BLEND_GL_ONE_MINUS_SRC_ALPHA (39) -#define R200_BLEND_GL_DST_ALPHA (40) -#define R200_BLEND_GL_ONE_MINUS_DST_ALPHA (41) -#define R200_BLEND_GL_SRC_ALPHA_SATURATE (42) /* src factor only */ -#define R200_BLEND_GL_CONST_COLOR (43) -#define R200_BLEND_GL_ONE_MINUS_CONST_COLOR (44) -#define R200_BLEND_GL_CONST_ALPHA (45) -#define R200_BLEND_GL_ONE_MINUS_CONST_ALPHA (46) -#define R200_BLEND_MASK (63) -#define R200_SRC_BLEND_SHIFT (16) -#define R200_DST_BLEND_SHIFT (24) -#define R200_RB3D_DEPTHOFFSET 0x1c24 -#define R200_RB3D_DEPTHPITCH 0x1c28 -#define R200_DEPTHPITCH_MASK 0x00001ff8 -#define R200_DEPTH_HYPERZ (3 << 16) -#define R200_DEPTH_ENDIAN_NO_SWAP (0 << 18) -#define R200_DEPTH_ENDIAN_WORD_SWAP (1 << 18) -#define R200_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) -#define R200_RB3D_ZSTENCILCNTL 0x1c2c -#define R200_DEPTH_FORMAT_MASK (0xf << 0) -#define R200_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) -#define R200_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) -#define R200_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) -#define R200_DEPTH_FORMAT_32BIT_INT_Z (4 << 0) -#define R200_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) -#define R200_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) -#define R200_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) -#define R200_Z_TEST_NEVER (0 << 4) -#define R200_Z_TEST_LESS (1 << 4) -#define R200_Z_TEST_LEQUAL (2 << 4) -#define R200_Z_TEST_EQUAL (3 << 4) -#define R200_Z_TEST_GEQUAL (4 << 4) -#define R200_Z_TEST_GREATER (5 << 4) -#define R200_Z_TEST_NEQUAL (6 << 4) -#define R200_Z_TEST_ALWAYS (7 << 4) -#define R200_Z_TEST_MASK (7 << 4) -#define R200_Z_HIERARCHY_ENABLE (1 << 8) -#define R200_STENCIL_TEST_NEVER (0 << 12) -#define R200_STENCIL_TEST_LESS (1 << 12) -#define R200_STENCIL_TEST_LEQUAL (2 << 12) -#define R200_STENCIL_TEST_EQUAL (3 << 12) -#define R200_STENCIL_TEST_GEQUAL (4 << 12) -#define R200_STENCIL_TEST_GREATER (5 << 12) -#define R200_STENCIL_TEST_NEQUAL (6 << 12) -#define R200_STENCIL_TEST_ALWAYS (7 << 12) -#define R200_STENCIL_TEST_MASK (0x7 << 12) -#define R200_STENCIL_FAIL_KEEP (0 << 16) -#define R200_STENCIL_FAIL_ZERO (1 << 16) -#define R200_STENCIL_FAIL_REPLACE (2 << 16) -#define R200_STENCIL_FAIL_INC (3 << 16) -#define R200_STENCIL_FAIL_DEC (4 << 16) -#define R200_STENCIL_FAIL_INVERT (5 << 16) -#define R200_STENCIL_FAIL_INC_WRAP (6 << 16) -#define R200_STENCIL_FAIL_DEC_WRAP (7 << 16) -#define R200_STENCIL_FAIL_MASK (0x7 << 16) -#define R200_STENCIL_ZPASS_KEEP (0 << 20) -#define R200_STENCIL_ZPASS_ZERO (1 << 20) -#define R200_STENCIL_ZPASS_REPLACE (2 << 20) -#define R200_STENCIL_ZPASS_INC (3 << 20) -#define R200_STENCIL_ZPASS_DEC (4 << 20) -#define R200_STENCIL_ZPASS_INVERT (5 << 20) -#define R200_STENCIL_ZPASS_INC_WRAP (6 << 20) -#define R200_STENCIL_ZPASS_DEC_WRAP (7 << 20) -#define R200_STENCIL_ZPASS_MASK (0x7 << 20) -#define R200_STENCIL_ZFAIL_KEEP (0 << 24) -#define R200_STENCIL_ZFAIL_ZERO (1 << 24) -#define R200_STENCIL_ZFAIL_REPLACE (2 << 24) -#define R200_STENCIL_ZFAIL_INC (3 << 24) -#define R200_STENCIL_ZFAIL_DEC (4 << 24) -#define R200_STENCIL_ZFAIL_INVERT (5 << 24) -#define R200_STENCIL_ZFAIL_INC_WRAP (6 << 24) -#define R200_STENCIL_ZFAIL_DEC_WRAP (7 << 24) -#define R200_STENCIL_ZFAIL_MASK (0x7 << 24) -#define R200_Z_COMPRESSION_ENABLE (1 << 28) -#define R200_FORCE_Z_DIRTY (1 << 29) -#define R200_Z_WRITE_ENABLE (1 << 30) -#define R200_Z_DECOMPRESSION_ENABLE (1 << 31) -/*gap*/ -#define R200_PP_CNTL 0x1c38 -#define R200_TEX_0_ENABLE 0x00000010 -#define R200_TEX_1_ENABLE 0x00000020 -#define R200_TEX_2_ENABLE 0x00000040 -#define R200_TEX_3_ENABLE 0x00000080 -#define R200_TEX_4_ENABLE 0x00000100 -#define R200_TEX_5_ENABLE 0x00000200 -#define R200_TEX_ENABLE_MASK 0x000003f0 -#define R200_FILTER_ROUND_MODE_MASK 0x00000400 -#define R200_TEX_BLEND_7_ENABLE 0x00000800 -#define R200_TEX_BLEND_0_ENABLE 0x00001000 -#define R200_TEX_BLEND_1_ENABLE 0x00002000 -#define R200_TEX_BLEND_2_ENABLE 0x00004000 -#define R200_TEX_BLEND_3_ENABLE 0x00008000 -#define R200_TEX_BLEND_4_ENABLE 0x00010000 -#define R200_TEX_BLEND_5_ENABLE 0x00020000 -#define R200_TEX_BLEND_6_ENABLE 0x00040000 -#define R200_TEX_BLEND_ENABLE_MASK 0x0007f800 -#define R200_TEX_BLEND_0_ENABLE_SHIFT (12) -#define R200_MULTI_PASS_ENABLE 0x00080000 -#define R200_SPECULAR_ENABLE 0x00200000 -#define R200_FOG_ENABLE 0x00400000 -#define R200_ALPHA_TEST_ENABLE 0x00800000 -#define R200_ANTI_ALIAS_NONE 0x00000000 -#define R200_ANTI_ALIAS_LINE 0x01000000 -#define R200_ANTI_ALIAS_POLY 0x02000000 -#define R200_ANTI_ALIAS_MASK 0x03000000 -#define R200_RB3D_CNTL 0x1c3c -#define R200_ALPHA_BLEND_ENABLE (1 << 0) -#define R200_PLANE_MASK_ENABLE (1 << 1) -#define R200_DITHER_ENABLE (1 << 2) -#define R200_ROUND_ENABLE (1 << 3) -#define R200_SCALE_DITHER_ENABLE (1 << 4) -#define R200_DITHER_INIT (1 << 5) -#define R200_ROP_ENABLE (1 << 6) -#define R200_STENCIL_ENABLE (1 << 7) -#define R200_Z_ENABLE (1 << 8) -#define R200_DEPTH_XZ_OFFEST_ENABLE (1 << 9) -#define R200_COLOR_FORMAT_ARGB1555 (3 << 10) -#define R200_COLOR_FORMAT_RGB565 (4 << 10) -#define R200_COLOR_FORMAT_ARGB8888 (6 << 10) -#define R200_COLOR_FORMAT_RGB332 (7 << 10) -#define R200_COLOR_FORMAT_Y8 (8 << 10) -#define R200_COLOR_FORMAT_RGB8 (9 << 10) -#define R200_COLOR_FORMAT_YUV422_VYUY (11 << 10) -#define R200_COLOR_FORMAT_YUV422_YVYU (12 << 10) -#define R200_COLOR_FORMAT_aYUV444 (14 << 10) -#define R200_COLOR_FORMAT_ARGB4444 (15 << 10) -#define R200_CLRCMP_FLIP_ENABLE (1 << 14) -#define R200_SEPARATE_ALPHA_ENABLE (1 << 16) -#define R200_RB3D_COLOROFFSET 0x1c40 -#define R200_COLOROFFSET_MASK 0xfffffff0 -#define R200_RE_WIDTH_HEIGHT 0x1c44 -#define R200_RE_WIDTH_SHIFT 0 -#define R200_RE_HEIGHT_SHIFT 16 -#define R200_RB3D_COLORPITCH 0x1c48 -#define R200_COLORPITCH_MASK 0x000001ff8 -#define R200_COLOR_TILE_ENABLE (1 << 16) -#define R200_COLOR_MICROTILE_ENABLE (1 << 17) -#define R200_COLOR_ENDIAN_NO_SWAP (0 << 18) -#define R200_COLOR_ENDIAN_WORD_SWAP (1 << 18) -#define R200_COLOR_ENDIAN_DWORD_SWAP (2 << 18) -#define R200_SE_CNTL 0x1c4c -#define R200_FFACE_CULL_CW (0 << 0) -#define R200_FFACE_CULL_CCW (1 << 0) -#define R200_FFACE_CULL_DIR_MASK (1 << 0) -#define R200_BFACE_CULL (0 << 1) -#define R200_BFACE_SOLID (3 << 1) -#define R200_FFACE_CULL (0 << 3) -#define R200_FFACE_SOLID (3 << 3) -#define R200_FFACE_CULL_MASK (3 << 3) -#define R200_FLAT_SHADE_VTX_0 (0 << 6) -#define R200_FLAT_SHADE_VTX_1 (1 << 6) -#define R200_FLAT_SHADE_VTX_2 (2 << 6) -#define R200_FLAT_SHADE_VTX_LAST (3 << 6) -#define R200_DIFFUSE_SHADE_SOLID (0 << 8) -#define R200_DIFFUSE_SHADE_FLAT (1 << 8) -#define R200_DIFFUSE_SHADE_GOURAUD (2 << 8) -#define R200_DIFFUSE_SHADE_MASK (3 << 8) -#define R200_ALPHA_SHADE_SOLID (0 << 10) -#define R200_ALPHA_SHADE_FLAT (1 << 10) -#define R200_ALPHA_SHADE_GOURAUD (2 << 10) -#define R200_ALPHA_SHADE_MASK (3 << 10) -#define R200_SPECULAR_SHADE_SOLID (0 << 12) -#define R200_SPECULAR_SHADE_FLAT (1 << 12) -#define R200_SPECULAR_SHADE_GOURAUD (2 << 12) -#define R200_SPECULAR_SHADE_MASK (3 << 12) -#define R200_FOG_SHADE_SOLID (0 << 14) -#define R200_FOG_SHADE_FLAT (1 << 14) -#define R200_FOG_SHADE_GOURAUD (2 << 14) -#define R200_FOG_SHADE_MASK (3 << 14) -#define R200_ZBIAS_ENABLE_POINT (1 << 16) -#define R200_ZBIAS_ENABLE_LINE (1 << 17) -#define R200_ZBIAS_ENABLE_TRI (1 << 18) -#define R200_WIDELINE_ENABLE (1 << 20) -#define R200_DISC_FOG_SHADE_SOLID (0 << 24) -#define R200_DISC_FOG_SHADE_FLAT (1 << 24) -#define R200_DISC_FOG_SHADE_GOURAUD (2 << 24) -#define R200_DISC_FOG_SHADE_MASK (3 << 24) -#define R200_VTX_PIX_CENTER_D3D (0 << 27) -#define R200_VTX_PIX_CENTER_OGL (1 << 27) -#define R200_ROUND_MODE_TRUNC (0 << 28) -#define R200_ROUND_MODE_ROUND (1 << 28) -#define R200_ROUND_MODE_ROUND_EVEN (2 << 28) -#define R200_ROUND_MODE_ROUND_ODD (3 << 28) -#define R200_ROUND_PREC_16TH_PIX (0 << 30) -#define R200_ROUND_PREC_8TH_PIX (1 << 30) -#define R200_ROUND_PREC_4TH_PIX (2 << 30) -#define R200_ROUND_PREC_HALF_PIX (3 << 30) -#define R200_RE_CNTL 0x1c50 -#define R200_STIPPLE_ENABLE 0x1 -#define R200_SCISSOR_ENABLE 0x2 -#define R200_PATTERN_ENABLE 0x4 -#define R200_PERSPECTIVE_ENABLE 0x8 -#define R200_POINT_SMOOTH 0x20 -#define R200_VTX_STQ0_D3D 0x00010000 -#define R200_VTX_STQ1_D3D 0x00040000 -#define R200_VTX_STQ2_D3D 0x00100000 -#define R200_VTX_STQ3_D3D 0x00400000 -#define R200_VTX_STQ4_D3D 0x01000000 -#define R200_VTX_STQ5_D3D 0x04000000 -/* gap */ -#define R200_RE_STIPPLE_ADDR 0x1cc8 -#define R200_RE_STIPPLE_DATA 0x1ccc -#define R200_RE_LINE_PATTERN 0x1cd0 -#define R200_LINE_PATTERN_MASK 0x0000ffff -#define R200_LINE_REPEAT_COUNT_SHIFT 16 -#define R200_LINE_PATTERN_START_SHIFT 24 -#define R200_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) -#define R200_LINE_PATTERN_BIG_BIT_ORDER (1 << 28) -#define R200_LINE_PATTERN_AUTO_RESET (1 << 29) -#define R200_RE_LINE_STATE 0x1cd4 -#define R200_LINE_CURRENT_PTR_SHIFT 0 -#define R200_LINE_CURRENT_COUNT_SHIFT 8 -#define R200_RE_SCISSOR_TL_0 0x1cd8 -#define R200_RE_SCISSOR_BR_0 0x1cdc -#define R200_RE_SCISSOR_TL_1 0x1ce0 -#define R200_RE_SCISSOR_BR_1 0x1ce4 -#define R200_RE_SCISSOR_TL_2 0x1ce8 -#define R200_RE_SCISSOR_BR_2 0x1cec -/* gap */ -#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 -#define R200_DEPTHX_SHIFT 0 -#define R200_DEPTHY_SHIFT 16 -/* gap */ -#define R200_RB3D_STENCILREFMASK 0x1d7c -#define R200_STENCIL_REF_SHIFT 0 -#define R200_STENCIL_REF_MASK (0xff << 0) -#define R200_STENCIL_MASK_SHIFT 16 -#define R200_STENCIL_VALUE_MASK (0xff << 16) -#define R200_STENCIL_WRITEMASK_SHIFT 24 -#define R200_STENCIL_WRITE_MASK (0xff << 24) -#define R200_RB3D_ROPCNTL 0x1d80 -#define R200_ROP_MASK (15 << 8) -#define R200_ROP_CLEAR (0 << 8) -#define R200_ROP_NOR (1 << 8) -#define R200_ROP_AND_INVERTED (2 << 8) -#define R200_ROP_COPY_INVERTED (3 << 8) -#define R200_ROP_AND_REVERSE (4 << 8) -#define R200_ROP_INVERT (5 << 8) -#define R200_ROP_XOR (6 << 8) -#define R200_ROP_NAND (7 << 8) -#define R200_ROP_AND (8 << 8) -#define R200_ROP_EQUIV (9 << 8) -#define R200_ROP_NOOP (10 << 8) -#define R200_ROP_OR_INVERTED (11 << 8) -#define R200_ROP_COPY (12 << 8) -#define R200_ROP_OR_REVERSE (13 << 8) -#define R200_ROP_OR (14 << 8) -#define R200_ROP_SET (15 << 8) -#define R200_RB3D_PLANEMASK 0x1d84 -/* gap */ -#define R200_SE_VPORT_XSCALE 0x1d98 -#define R200_SE_VPORT_XOFFSET 0x1d9c -#define R200_SE_VPORT_YSCALE 0x1da0 -#define R200_SE_VPORT_YOFFSET 0x1da4 -#define R200_SE_VPORT_ZSCALE 0x1da8 -#define R200_SE_VPORT_ZOFFSET 0x1dac -#define R200_SE_ZBIAS_FACTOR 0x1db0 -#define R200_SE_ZBIAS_CONSTANT 0x1db4 -#define R200_SE_LINE_WIDTH 0x1db8 -#define R200_LINE_WIDTH_SHIFT 0x00000000 -#define R200_MINPOINTSIZE_SHIFT 0x00000010 -/* gap */ -#define R200_SE_VAP_CNTL 0x2080 -#define R200_VAP_TCL_ENABLE 0x00000001 -#define R200_VAP_PROG_VTX_SHADER_ENABLE 0x00000004 -#define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010 -#define R200_VAP_FORCE_W_TO_ONE 0x00010000 -#define R200_VAP_D3D_TEX_DEFAULT 0x00020000 -#define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18 -#define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000 -#define R200_SE_VF_CNTL 0x2084 -#define R200_VF_PRIM_NONE 0x00000000 -#define R200_VF_PRIM_POINTS 0x00000001 -#define R200_VF_PRIM_LINES 0x00000002 -#define R200_VF_PRIM_LINE_STRIP 0x00000003 -#define R200_VF_PRIM_TRIANGLES 0x00000004 -#define R200_VF_PRIM_TRIANGLE_FAN 0x00000005 -#define R200_VF_PRIM_TRIANGLE_STRIP 0x00000006 -#define R200_VF_PRIM_RECT_LIST 0x00000008 -#define R200_VF_PRIM_3VRT_POINTS 0x00000009 -#define R200_VF_PRIM_3VRT_LINES 0x0000000a -#define R200_VF_PRIM_POINT_SPRITES 0x0000000b -#define R200_VF_PRIM_LINE_LOOP 0x0000000c -#define R200_VF_PRIM_QUADS 0x0000000d -#define R200_VF_PRIM_QUAD_STRIP 0x0000000e -#define R200_VF_PRIM_POLYGON 0x0000000f -#define R200_VF_PRIM_MASK 0x0000000f -#define R200_VF_PRIM_WALK_IND 0x00000010 -#define R200_VF_PRIM_WALK_LIST 0x00000020 -#define R200_VF_PRIM_WALK_RING 0x00000030 -#define R200_VF_PRIM_WALK_MASK 0x00000030 -#define R200_VF_COLOR_ORDER_RGBA 0x00000040 -#define R200_VF_TCL_OUTPUT_VTX_ENABLE 0x00000200 -#define R200_VF_INDEX_SZ_4 0x00000800 -#define R200_VF_VERTEX_NUMBER_MASK 0xffff0000 -#define R200_VF_VERTEX_NUMBER_SHIFT 16 -#define R200_SE_VTX_FMT_0 0x2088 -#define R200_VTX_XY 0 /* always have xy */ -#define R200_VTX_Z0 (1<<0) -#define R200_VTX_W0 (1<<1) -#define R200_VTX_WEIGHT_COUNT_SHIFT (2) -#define R200_VTX_PV_MATRIX_SEL (1<<5) -#define R200_VTX_N0 (1<<6) -#define R200_VTX_POINT_SIZE (1<<7) -#define R200_VTX_DISCRETE_FOG (1<<8) -#define R200_VTX_SHININESS_0 (1<<9) -#define R200_VTX_SHININESS_1 (1<<10) -#define R200_VTX_COLOR_NOT_PRESENT 0 -#define R200_VTX_PK_RGBA 1 -#define R200_VTX_FP_RGB 2 -#define R200_VTX_FP_RGBA 3 -#define R200_VTX_COLOR_MASK 3 -#define R200_VTX_COLOR_0_SHIFT 11 -#define R200_VTX_COLOR_1_SHIFT 13 -#define R200_VTX_COLOR_2_SHIFT 15 -#define R200_VTX_COLOR_3_SHIFT 17 -#define R200_VTX_COLOR_4_SHIFT 19 -#define R200_VTX_COLOR_5_SHIFT 21 -#define R200_VTX_COLOR_6_SHIFT 23 -#define R200_VTX_COLOR_7_SHIFT 25 -#define R200_VTX_XY1 (1<<28) -#define R200_VTX_Z1 (1<<29) -#define R200_VTX_W1 (1<<30) -#define R200_VTX_N1 (1<<31) -#define R200_SE_VTX_FMT_1 0x208c -#define R200_VTX_TEX0_COMP_CNT_SHIFT 0 -#define R200_VTX_TEX1_COMP_CNT_SHIFT 3 -#define R200_VTX_TEX2_COMP_CNT_SHIFT 6 -#define R200_VTX_TEX3_COMP_CNT_SHIFT 9 -#define R200_VTX_TEX4_COMP_CNT_SHIFT 12 -#define R200_VTX_TEX5_COMP_CNT_SHIFT 15 -#define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090 -#define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094 -/* gap */ -#define R200_SE_VTE_CNTL 0x20b0 -#define R200_VPORT_X_SCALE_ENA 0x00000001 -#define R200_VPORT_X_OFFSET_ENA 0x00000002 -#define R200_VPORT_Y_SCALE_ENA 0x00000004 -#define R200_VPORT_Y_OFFSET_ENA 0x00000008 -#define R200_VPORT_Z_SCALE_ENA 0x00000010 -#define R200_VPORT_Z_OFFSET_ENA 0x00000020 -#define R200_VTX_XY_FMT 0x00000100 -#define R200_VTX_Z_FMT 0x00000200 -#define R200_VTX_W0_FMT 0x00000400 -#define R200_VTX_W0_NORMALIZE 0x00000800 -#define R200_VTX_ST_DENORMALIZED 0x00001000 -/* gap */ -#define R200_SE_VTX_NUM_ARRAYS 0x20c0 -#define R200_SE_VTX_AOS_ATTR01 0x20c4 -#define R200_SE_VTX_AOS_ADDR0 0x20c8 -#define R200_SE_VTX_AOS_ADDR1 0x20cc -#define R200_SE_VTX_AOS_ATTR23 0x20d0 -#define R200_SE_VTX_AOS_ADDR2 0x20d4 -#define R200_SE_VTX_AOS_ADDR3 0x20d8 -#define R200_SE_VTX_AOS_ATTR45 0x20dc -#define R200_SE_VTX_AOS_ADDR4 0x20e0 -#define R200_SE_VTX_AOS_ADDR5 0x20e4 -#define R200_SE_VTX_AOS_ATTR67 0x20e8 -#define R200_SE_VTX_AOS_ADDR6 0x20ec -#define R200_SE_VTX_AOS_ADDR7 0x20f0 -#define R200_SE_VTX_AOS_ATTR89 0x20f4 -#define R200_SE_VTX_AOS_ADDR8 0x20f8 -#define R200_SE_VTX_AOS_ADDR9 0x20fc -#define R200_SE_VTX_AOS_ATTR1011 0x2100 -#define R200_SE_VTX_AOS_ADDR10 0x2104 -#define R200_SE_VTX_AOS_ADDR11 0x2108 -#define R200_SE_VF_MAX_VTX_INDX 0x210c -#define R200_SE_VF_MIN_VTX_INDX 0x2110 -/* gap */ -#define R200_SE_VAP_CNTL_STATUS 0x2140 -#define R200_VC_NO_SWAP (0 << 0) -#define R200_VC_16BIT_SWAP (1 << 0) -#define R200_VC_32BIT_SWAP (2 << 0) -/* gap */ -#define R200_SE_VTX_STATE_CNTL 0x2180 -#define R200_VSC_COLOR_0_ASSEMBLY_CNTL_SHIFT 0x00000000 -#define R200_VSC_COLOR_1_ASSEMBLY_CNTL_SHIFT 0x00000002 -#define R200_VSC_COLOR_2_ASSEMBLY_CNTL_SHIFT 0x00000004 -#define R200_VSC_COLOR_3_ASSEMBLY_CNTL_SHIFT 0x00000006 -#define R200_VSC_COLOR_4_ASSEMBLY_CNTL_SHIFT 0x00000008 -#define R200_VSC_COLOR_5_ASSEMBLY_CNTL_SHIFT 0x0000000a -#define R200_VSC_COLOR_6_ASSEMBLY_CNTL_SHIFT 0x0000000c -#define R200_VSC_COLOR_7_ASSEMBLY_CNTL_SHIFT 0x0000000e -#define R200_VSC_UPDATE_USER_COLOR_0_ENABLE 0x00010000 -#define R200_VSC_UPDATE_USER_COLOR_1_ENABLE 0x00020000 -/* gap */ -#define R200_SE_TCL_VECTOR_INDX_REG 0x2200 -# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 -# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 -#define R200_SE_TCL_VECTOR_DATA_REG 0x2204 -#define R200_SE_TCL_SCALAR_INDX_REG 0x2208 -# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 -#define R200_SE_TCL_SCALAR_DATA_REG 0x220c -/* gap */ -#define R200_SE_TCL_MATRIX_SEL_0 0x2230 -#define R200_MODELVIEW_0_SHIFT (0) -#define R200_MODELVIEW_1_SHIFT (8) -#define R200_MODELVIEW_2_SHIFT (16) -#define R200_MODELVIEW_3_SHIFT (24) -#define R200_SE_TCL_MATRIX_SEL_1 0x2234 -#define R200_IT_MODELVIEW_0_SHIFT (0) -#define R200_IT_MODELVIEW_1_SHIFT (8) -#define R200_IT_MODELVIEW_2_SHIFT (16) -#define R200_IT_MODELVIEW_3_SHIFT (24) -#define R200_SE_TCL_MATRIX_SEL_2 0x2238 -#define R200_MODELPROJECT_0_SHIFT (0) -#define R200_MODELPROJECT_1_SHIFT (8) -#define R200_MODELPROJECT_2_SHIFT (16) -#define R200_MODELPROJECT_3_SHIFT (24) -#define R200_SE_TCL_MATRIX_SEL_3 0x223c -#define R200_TEXMAT_0_SHIFT 0 -#define R200_TEXMAT_1_SHIFT 8 -#define R200_TEXMAT_2_SHIFT 16 -#define R200_TEXMAT_3_SHIFT 24 -#define R200_SE_TCL_MATRIX_SEL_4 0x2240 -#define R200_TEXMAT_4_SHIFT 0 -#define R200_TEXMAT_5_SHIFT 8 -/* gap */ -#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 -#define R200_OUTPUT_XYZW (1<<0) -#define R200_OUTPUT_COLOR_0 (1<<8) -#define R200_OUTPUT_COLOR_1 (1<<9) -#define R200_OUTPUT_TEX_0 (1<<16) -#define R200_OUTPUT_TEX_1 (1<<17) -#define R200_OUTPUT_TEX_2 (1<<18) -#define R200_OUTPUT_TEX_3 (1<<19) -#define R200_OUTPUT_TEX_4 (1<<20) -#define R200_OUTPUT_TEX_5 (1<<21) -#define R200_OUTPUT_TEX_MASK (0x3f<<16) -#define R200_OUTPUT_DISCRETE_FOG (1<<24) -#define R200_OUTPUT_PT_SIZE (1<<25) -#define R200_FORCE_INORDER_PROC (1<<31) -#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 -#define R200_VERTEX_POSITION_ADDR__SHIFT 0x00000000 -#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1 0x2258 -#define R200_VTX_COLOR_0_ADDR__SHIFT 0x00000000 -#define R200_VTX_COLOR_1_ADDR__SHIFT 0x00000008 -#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2 0x225c -#define R200_VTX_TEX_0_ADDR__SHIFT 0x00000000 -#define R200_VTX_TEX_1_ADDR__SHIFT 0x00000008 -#define R200_VTX_TEX_2_ADDR__SHIFT 0x00000010 -#define R200_VTX_TEX_3_ADDR__SHIFT 0x00000018 -#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3 0x2260 -#define R200_VTX_TEX_4_ADDR__SHIFT 0x00000000 -#define R200_VTX_TEX_5_ADDR__SHIFT 0x00000008 - -/* gap */ -#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 -#define R200_LIGHTING_ENABLE (1<<0) -#define R200_LIGHT_IN_MODELSPACE (1<<1) -#define R200_LOCAL_VIEWER (1<<2) -#define R200_NORMALIZE_NORMALS (1<<3) -#define R200_RESCALE_NORMALS (1<<4) -#define R200_SPECULAR_LIGHTS (1<<5) -#define R200_DIFFUSE_SPECULAR_COMBINE (1<<6) -#define R200_LIGHT_ALPHA (1<<7) -#define R200_LOCAL_LIGHT_VEC_GL (1<<8) -#define R200_LIGHT_NO_NORMAL_AMBIENT_ONLY (1<<9) -#define R200_LIGHT_TWOSIDE (1<<10) -#define R200_FRONT_SHININESS_SOURCE_SHIFT (0xb) -#define R200_BACK_SHININESS_SOURCE_SHIFT (0xd) -#define R200_LM0_SOURCE_MATERIAL_0 (0) -#define R200_LM0_SOURCE_MATERIAL_1 (1) -#define R200_LM0_SOURCE_VERTEX_SHININESS_0 (2) -#define R200_LM0_SOURCE_VERTEX_SHININESS_1 (3) -#define R200_SE_TCL_LIGHT_MODEL_CTL_1 0x226c -#define R200_LM1_SOURCE_LIGHT_PREMULT (0) -#define R200_LM1_SOURCE_MATERIAL_0 (1) -#define R200_LM1_SOURCE_VERTEX_COLOR_0 (2) -#define R200_LM1_SOURCE_VERTEX_COLOR_1 (3) -#define R200_LM1_SOURCE_VERTEX_COLOR_2 (4) -#define R200_LM1_SOURCE_VERTEX_COLOR_3 (5) -#define R200_LM1_SOURCE_VERTEX_COLOR_4 (6) -#define R200_LM1_SOURCE_VERTEX_COLOR_5 (7) -#define R200_LM1_SOURCE_VERTEX_COLOR_6 (8) -#define R200_LM1_SOURCE_VERTEX_COLOR_7 (9) -#define R200_LM1_SOURCE_MATERIAL_1 (0xf) -#define R200_FRONT_EMISSIVE_SOURCE_SHIFT (0) -#define R200_FRONT_AMBIENT_SOURCE_SHIFT (4) -#define R200_FRONT_DIFFUSE_SOURCE_SHIFT (8) -#define R200_FRONT_SPECULAR_SOURCE_SHIFT (12) -#define R200_BACK_EMISSIVE_SOURCE_SHIFT (16) -#define R200_BACK_AMBIENT_SOURCE_SHIFT (20) -#define R200_BACK_DIFFUSE_SOURCE_SHIFT (24) -#define R200_BACK_SPECULAR_SOURCE_SHIFT (28) -#define R200_SE_TCL_PER_LIGHT_CTL_0 0x2270 -#define R200_LIGHT_0_ENABLE (1<<0) -#define R200_LIGHT_0_ENABLE_AMBIENT (1<<1) -#define R200_LIGHT_0_ENABLE_SPECULAR (1<<2) -#define R200_LIGHT_0_IS_LOCAL (1<<3) -#define R200_LIGHT_0_IS_SPOT (1<<4) -#define R200_LIGHT_0_DUAL_CONE (1<<5) -#define R200_LIGHT_0_ENABLE_RANGE_ATTEN (1<<6) -#define R200_LIGHT_0_CONSTANT_RANGE_ATTEN (1<<7) -#define R200_LIGHT_1_ENABLE (1<<16) -#define R200_LIGHT_1_ENABLE_AMBIENT (1<<17) -#define R200_LIGHT_1_ENABLE_SPECULAR (1<<18) -#define R200_LIGHT_1_IS_LOCAL (1<<19) -#define R200_LIGHT_1_IS_SPOT (1<<20) -#define R200_LIGHT_1_DUAL_CONE (1<<21) -#define R200_LIGHT_1_ENABLE_RANGE_ATTEN (1<<22) -#define R200_LIGHT_1_CONSTANT_RANGE_ATTEN (1<<23) -#define R200_LIGHT_0_SHIFT (0) -#define R200_LIGHT_1_SHIFT (16) -#define R200_SE_TCL_PER_LIGHT_CTL_1 0x2274 -#define R200_LIGHT_2_SHIFT (0) -#define R200_LIGHT_3_SHIFT (16) -#define R200_SE_TCL_PER_LIGHT_CTL_2 0x2278 -#define R200_LIGHT_4_SHIFT (0) -#define R200_LIGHT_5_SHIFT (16) -#define R200_SE_TCL_PER_LIGHT_CTL_3 0x227c -#define R200_LIGHT_6_SHIFT (0) -#define R200_LIGHT_7_SHIFT (16) -/* gap */ -#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 -#define R200_TEXGEN_COMP_MASK (0xf) -#define R200_TEXGEN_COMP_S (0x1) -#define R200_TEXGEN_COMP_T (0x2) -#define R200_TEXGEN_COMP_R (0x4) -#define R200_TEXGEN_COMP_Q (0x8) -#define R200_TEXGEN_0_COMP_MASK_SHIFT (0) -#define R200_TEXGEN_1_COMP_MASK_SHIFT (4) -#define R200_TEXGEN_2_COMP_MASK_SHIFT (8) -#define R200_TEXGEN_3_COMP_MASK_SHIFT (12) -#define R200_TEXGEN_4_COMP_MASK_SHIFT (16) -#define R200_TEXGEN_5_COMP_MASK_SHIFT (20) -#define R200_SE_TCL_TEX_PROC_CTL_3 0x22ac -#define R200_TEXGEN_0_INPUT_TEX_SHIFT (0) -#define R200_TEXGEN_1_INPUT_TEX_SHIFT (4) -#define R200_TEXGEN_2_INPUT_TEX_SHIFT (8) -#define R200_TEXGEN_3_INPUT_TEX_SHIFT (12) -#define R200_TEXGEN_4_INPUT_TEX_SHIFT (16) -#define R200_TEXGEN_5_INPUT_TEX_SHIFT (20) -#define R200_SE_TCL_TEX_PROC_CTL_0 0x22b0 -#define R200_TEXGEN_TEXMAT_0_ENABLE (1<<0) -#define R200_TEXGEN_TEXMAT_1_ENABLE (1<<1) -#define R200_TEXGEN_TEXMAT_2_ENABLE (1<<2) -#define R200_TEXGEN_TEXMAT_3_ENABLE (1<<3) -#define R200_TEXGEN_TEXMAT_4_ENABLE (1<<4) -#define R200_TEXGEN_TEXMAT_5_ENABLE (1<<5) -#define R200_TEXMAT_0_ENABLE (1<<8) -#define R200_TEXMAT_1_ENABLE (1<<9) -#define R200_TEXMAT_2_ENABLE (1<<10) -#define R200_TEXMAT_3_ENABLE (1<<11) -#define R200_TEXMAT_4_ENABLE (1<<12) -#define R200_TEXMAT_5_ENABLE (1<<13) -#define R200_TEXGEN_FORCE_W_TO_ONE (1<<16) -#define R200_SE_TCL_TEX_PROC_CTL_1 0x22b4 -#define R200_TEXGEN_INPUT_MASK (0xf) -#define R200_TEXGEN_INPUT_TEXCOORD_0 (0) -#define R200_TEXGEN_INPUT_TEXCOORD_1 (1) -#define R200_TEXGEN_INPUT_TEXCOORD_2 (2) -#define R200_TEXGEN_INPUT_TEXCOORD_3 (3) -#define R200_TEXGEN_INPUT_TEXCOORD_4 (4) -#define R200_TEXGEN_INPUT_TEXCOORD_5 (5) -#define R200_TEXGEN_INPUT_OBJ (8) -#define R200_TEXGEN_INPUT_EYE (9) -#define R200_TEXGEN_INPUT_EYE_NORMAL (0xa) -#define R200_TEXGEN_INPUT_EYE_REFLECT (0xb) -#define R200_TEXGEN_INPUT_SPHERE (0xd) -#define R200_TEXGEN_0_INPUT_SHIFT (0) -#define R200_TEXGEN_1_INPUT_SHIFT (4) -#define R200_TEXGEN_2_INPUT_SHIFT (8) -#define R200_TEXGEN_3_INPUT_SHIFT (12) -#define R200_TEXGEN_4_INPUT_SHIFT (16) -#define R200_TEXGEN_5_INPUT_SHIFT (20) -#define R200_SE_TC_TEX_CYL_WRAP_CTL 0x22b8 -/* gap */ -#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 -#define R200_UCP_IN_CLIP_SPACE (1<<0) -#define R200_UCP_IN_MODEL_SPACE (1<<1) -#define R200_UCP_ENABLE_0 (1<<2) -#define R200_UCP_ENABLE_1 (1<<3) -#define R200_UCP_ENABLE_2 (1<<4) -#define R200_UCP_ENABLE_3 (1<<5) -#define R200_UCP_ENABLE_4 (1<<6) -#define R200_UCP_ENABLE_5 (1<<7) -#define R200_TCL_FOG_MASK (3<<8) -#define R200_TCL_FOG_DISABLE (0<<8) -#define R200_TCL_FOG_EXP (1<<8) -#define R200_TCL_FOG_EXP2 (2<<8) -#define R200_TCL_FOG_LINEAR (3<<8) -#define R200_RNG_BASED_FOG (1<<10) -#define R200_CLIP_DISABLE (1<<11) -#define R200_CULL_FRONT_IS_CW (0<<28) -#define R200_CULL_FRONT_IS_CCW (1<<28) -#define R200_CULL_FRONT (1<<29) -#define R200_CULL_BACK (1<<30) -#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 -#define R200_PS_MULT_PVATTENCONST (0<<0) -#define R200_PS_MULT_PVATTEN (1<<0) -#define R200_PS_MULT_ATTENCONST (2<<0) -#define R200_PS_MULT_PVCONST (3<<0) -#define R200_PS_MULT_CONST (4<<0) -#define R200_PS_MULT_MASK (7<<0) -#define R200_PS_LIN_ATT_ZERO (1<<3) -#define R200_PS_USE_MODEL_EYE_VEC (1<<4) -#define R200_PS_ATT_ALPHA (1<<5) -#define R200_PS_UCP_MODE_MASK (3<<6) -#define R200_PS_GEN_TEX_0 (1<<8) -#define R200_PS_GEN_TEX_1 (1<<9) -#define R200_PS_GEN_TEX_2 (1<<10) -#define R200_PS_GEN_TEX_3 (1<<11) -#define R200_PS_GEN_TEX_4 (1<<12) -#define R200_PS_GEN_TEX_5 (1<<13) -#define R200_PS_GEN_TEX_0_SHIFT (8) -#define R200_PS_GEN_TEX_MASK (0x3f<<8) -#define R200_PS_SE_SEL_STATE (1<<16) -/* gap */ -/* taken from r300, see comments there */ -#define R200_VAP_PVS_CNTL_1 0x22d0 -# define R200_PVS_CNTL_1_PROGRAM_START_SHIFT 0 -# define R200_PVS_CNTL_1_POS_END_SHIFT 10 -# define R200_PVS_CNTL_1_PROGRAM_END_SHIFT 20 -/* Addresses are relative to the vertex program parameters area. */ -#define R200_VAP_PVS_CNTL_2 0x22d4 -# define R200_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0 -# define R200_PVS_CNTL_2_PARAM_COUNT_SHIFT 16 -/* gap */ - -#define R200_SE_VTX_ST_POS_0_X_4 0x2300 -#define R200_SE_VTX_ST_POS_0_Y_4 0x2304 -#define R200_SE_VTX_ST_POS_0_Z_4 0x2308 -#define R200_SE_VTX_ST_POS_0_W_4 0x230c -#define R200_SE_VTX_ST_NORM_0_X 0x2310 -#define R200_SE_VTX_ST_NORM_0_Y 0x2314 -#define R200_SE_VTX_ST_NORM_0_Z 0x2318 -#define R200_SE_VTX_ST_PVMS 0x231c -#define R200_SE_VTX_ST_CLR_0_R 0x2320 -#define R200_SE_VTX_ST_CLR_0_G 0x2324 -#define R200_SE_VTX_ST_CLR_0_B 0x2328 -#define R200_SE_VTX_ST_CLR_0_A 0x232c -#define R200_SE_VTX_ST_CLR_1_R 0x2330 -#define R200_SE_VTX_ST_CLR_1_G 0x2334 -#define R200_SE_VTX_ST_CLR_1_B 0x2338 -#define R200_SE_VTX_ST_CLR_1_A 0x233c -#define R200_SE_VTX_ST_CLR_2_R 0x2340 -#define R200_SE_VTX_ST_CLR_2_G 0x2344 -#define R200_SE_VTX_ST_CLR_2_B 0x2348 -#define R200_SE_VTX_ST_CLR_2_A 0x234c -#define R200_SE_VTX_ST_CLR_3_R 0x2350 -#define R200_SE_VTX_ST_CLR_3_G 0x2354 -#define R200_SE_VTX_ST_CLR_3_B 0x2358 -#define R200_SE_VTX_ST_CLR_3_A 0x235c -#define R200_SE_VTX_ST_CLR_4_R 0x2360 -#define R200_SE_VTX_ST_CLR_4_G 0x2364 -#define R200_SE_VTX_ST_CLR_4_B 0x2368 -#define R200_SE_VTX_ST_CLR_4_A 0x236c -#define R200_SE_VTX_ST_CLR_5_R 0x2370 -#define R200_SE_VTX_ST_CLR_5_G 0x2374 -#define R200_SE_VTX_ST_CLR_5_B 0x2378 -#define R200_SE_VTX_ST_CLR_5_A 0x237c -#define R200_SE_VTX_ST_CLR_6_R 0x2380 -#define R200_SE_VTX_ST_CLR_6_G 0x2384 -#define R200_SE_VTX_ST_CLR_6_B 0x2388 -#define R200_SE_VTX_ST_CLR_6_A 0x238c -#define R200_SE_VTX_ST_CLR_7_R 0x2390 -#define R200_SE_VTX_ST_CLR_7_G 0x2394 -#define R200_SE_VTX_ST_CLR_7_B 0x2398 -#define R200_SE_VTX_ST_CLR_7_A 0x239c -#define R200_SE_VTX_ST_TEX_0_S 0x23a0 -#define R200_SE_VTX_ST_TEX_0_T 0x23a4 -#define R200_SE_VTX_ST_TEX_0_R 0x23a8 -#define R200_SE_VTX_ST_TEX_0_Q 0x23ac -#define R200_SE_VTX_ST_TEX_1_S 0x23b0 -#define R200_SE_VTX_ST_TEX_1_T 0x23b4 -#define R200_SE_VTX_ST_TEX_1_R 0x23b8 -#define R200_SE_VTX_ST_TEX_1_Q 0x23bc -#define R200_SE_VTX_ST_TEX_2_S 0x23c0 -#define R200_SE_VTX_ST_TEX_2_T 0x23c4 -#define R200_SE_VTX_ST_TEX_2_R 0x23c8 -#define R200_SE_VTX_ST_TEX_2_Q 0x23cc -#define R200_SE_VTX_ST_TEX_3_S 0x23d0 -#define R200_SE_VTX_ST_TEX_3_T 0x23d4 -#define R200_SE_VTX_ST_TEX_3_R 0x23d8 -#define R200_SE_VTX_ST_TEX_3_Q 0x23dc -#define R200_SE_VTX_ST_TEX_4_S 0x23e0 -#define R200_SE_VTX_ST_TEX_4_T 0x23e4 -#define R200_SE_VTX_ST_TEX_4_R 0x23e8 -#define R200_SE_VTX_ST_TEX_4_Q 0x23ec -#define R200_SE_VTX_ST_TEX_5_S 0x23f0 -#define R200_SE_VTX_ST_TEX_5_T 0x23f4 -#define R200_SE_VTX_ST_TEX_5_R 0x23f8 -#define R200_SE_VTX_ST_TEX_5_Q 0x23fc -#define R200_SE_VTX_ST_PNT_SPRT_SZ 0x2400 -#define R200_SE_VTX_ST_DISC_FOG 0x2404 -#define R200_SE_VTX_ST_SHININESS_0 0x2408 -#define R200_SE_VTX_ST_SHININESS_1 0x240c -#define R200_SE_VTX_ST_BLND_WT_0 0x2410 -#define R200_SE_VTX_ST_BLND_WT_1 0x2414 -#define R200_SE_VTX_ST_BLND_WT_2 0x2418 -#define R200_SE_VTX_ST_BLND_WT_3 0x241c -#define R200_SE_VTX_ST_POS_1_X 0x2420 -#define R200_SE_VTX_ST_POS_1_Y 0x2424 -#define R200_SE_VTX_ST_POS_1_Z 0x2428 -#define R200_SE_VTX_ST_POS_1_W 0x242c -#define R200_SE_VTX_ST_NORM_1_X 0x2430 -#define R200_SE_VTX_ST_NORM_1_Y 0x2434 -#define R200_SE_VTX_ST_NORM_1_Z 0x2438 -#define R200_SE_VTX_ST_USR_CLR_0_R 0x2440 -#define R200_SE_VTX_ST_USR_CLR_0_G 0x2444 -#define R200_SE_VTX_ST_USR_CLR_0_B 0x2448 -#define R200_SE_VTX_ST_USR_CLR_0_A 0x244c -#define R200_SE_VTX_ST_USR_CLR_1_R 0x2450 -#define R200_SE_VTX_ST_USR_CLR_1_G 0x2454 -#define R200_SE_VTX_ST_USR_CLR_1_B 0x2458 -#define R200_SE_VTX_ST_USR_CLR_1_A 0x245c -#define R200_SE_VTX_ST_CLR_0_PKD 0x2460 -#define R200_SE_VTX_ST_CLR_1_PKD 0x2464 -#define R200_SE_VTX_ST_CLR_2_PKD 0x2468 -#define R200_SE_VTX_ST_CLR_3_PKD 0x246c -#define R200_SE_VTX_ST_CLR_4_PKD 0x2470 -#define R200_SE_VTX_ST_CLR_5_PKD 0x2474 -#define R200_SE_VTX_ST_CLR_6_PKD 0x2478 -#define R200_SE_VTX_ST_CLR_7_PKD 0x247c -#define R200_SE_VTX_ST_POS_0_X_2 0x2480 -#define R200_SE_VTX_ST_POS_0_Y_2 0x2484 -#define R200_SE_VTX_ST_PAR_CLR_LD 0x2488 -#define R200_SE_VTX_ST_USR_CLR_PKD 0x248c -#define R200_SE_VTX_ST_POS_0_X_3 0x2490 -#define R200_SE_VTX_ST_POS_0_Y_3 0x2494 -#define R200_SE_VTX_ST_POS_0_Z_3 0x2498 -#define R200_SE_VTX_ST_END_OF_PKT 0x249c -/* gap */ -#define R200_RE_POINTSIZE 0x2648 -#define R200_POINTSIZE_SHIFT 0 -#define R200_MAXPOINTSIZE_SHIFT 16 -/* gap */ -#define R200_RE_TOP_LEFT 0x26c0 -#define R200_RE_LEFT_SHIFT 0 -#define R200_RE_TOP_SHIFT 16 -#define R200_RE_MISC 0x26c4 -#define R200_STIPPLE_COORD_MASK 0x1f -#define R200_STIPPLE_X_OFFSET_SHIFT 0 -#define R200_STIPPLE_X_OFFSET_MASK (0x1f << 0) -#define R200_STIPPLE_Y_OFFSET_SHIFT 8 -#define R200_STIPPLE_Y_OFFSET_MASK (0x1f << 8) -#define R200_STIPPLE_LITTLE_BIT_ORDER (0 << 16) -#define R200_STIPPLE_BIG_BIT_ORDER (1 << 16) -/* gap */ -#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 -#define R200_EXCLUSIVE_SCISSOR_0 0x01000000 -#define R200_EXCLUSIVE_SCISSOR_1 0x02000000 -#define R200_EXCLUSIVE_SCISSOR_2 0x04000000 -#define R200_SCISSOR_ENABLE_0 0x10000000 -#define R200_SCISSOR_ENABLE_1 0x20000000 -#define R200_SCISSOR_ENABLE_2 0x40000000 -/* gap */ -#define R200_PP_TXFILTER_0 0x2c00 -#define R200_MAG_FILTER_NEAREST (0 << 0) -#define R200_MAG_FILTER_LINEAR (1 << 0) -#define R200_MAG_FILTER_MASK (1 << 0) -#define R200_MIN_FILTER_NEAREST (0 << 1) -#define R200_MIN_FILTER_LINEAR (1 << 1) -#define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) -#define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) -#define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) -#define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) -#define R200_MIN_FILTER_ANISO_NEAREST (8 << 1) -#define R200_MIN_FILTER_ANISO_LINEAR (9 << 1) -#define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) -#define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) -#define R200_MIN_FILTER_MASK (15 << 1) -#define R200_MAX_ANISO_1_TO_1 (0 << 5) -#define R200_MAX_ANISO_2_TO_1 (1 << 5) -#define R200_MAX_ANISO_4_TO_1 (2 << 5) -#define R200_MAX_ANISO_8_TO_1 (3 << 5) -#define R200_MAX_ANISO_16_TO_1 (4 << 5) -#define R200_MAX_ANISO_MASK (7 << 5) -#define R200_MAX_MIP_LEVEL_MASK (0x0f << 16) -#define R200_MAX_MIP_LEVEL_SHIFT 16 -#define R200_YUV_TO_RGB (1 << 20) -#define R200_YUV_TEMPERATURE_COOL (0 << 21) -#define R200_YUV_TEMPERATURE_HOT (1 << 21) -#define R200_YUV_TEMPERATURE_MASK (1 << 21) -#define R200_WRAPEN_S (1 << 22) -#define R200_CLAMP_S_WRAP (0 << 23) -#define R200_CLAMP_S_MIRROR (1 << 23) -#define R200_CLAMP_S_CLAMP_LAST (2 << 23) -#define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) -#define R200_CLAMP_S_CLAMP_BORDER (4 << 23) -#define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) -#define R200_CLAMP_S_CLAMP_GL (6 << 23) -#define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) -#define R200_CLAMP_S_MASK (7 << 23) -#define R200_WRAPEN_T (1 << 26) -#define R200_CLAMP_T_WRAP (0 << 27) -#define R200_CLAMP_T_MIRROR (1 << 27) -#define R200_CLAMP_T_CLAMP_LAST (2 << 27) -#define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) -#define R200_CLAMP_T_CLAMP_BORDER (4 << 27) -#define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) -#define R200_CLAMP_T_CLAMP_GL (6 << 27) -#define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) -#define R200_CLAMP_T_MASK (7 << 27) -#define R200_KILL_LT_ZERO (1 << 30) -#define R200_BORDER_MODE_OGL (0 << 31) -#define R200_BORDER_MODE_D3D (1 << 31) -#define R200_PP_TXFORMAT_0 0x2c04 -#define R200_TXFORMAT_I8 (0 << 0) -#define R200_TXFORMAT_AI88 (1 << 0) -#define R200_TXFORMAT_RGB332 (2 << 0) -#define R200_TXFORMAT_ARGB1555 (3 << 0) -#define R200_TXFORMAT_RGB565 (4 << 0) -#define R200_TXFORMAT_ARGB4444 (5 << 0) -#define R200_TXFORMAT_ARGB8888 (6 << 0) -#define R200_TXFORMAT_RGBA8888 (7 << 0) -#define R200_TXFORMAT_Y8 (8 << 0) -#define R200_TXFORMAT_AVYU4444 (9 << 0) -#define R200_TXFORMAT_VYUY422 (10 << 0) -#define R200_TXFORMAT_YVYU422 (11 << 0) -#define R200_TXFORMAT_DXT1 (12 << 0) -#define R200_TXFORMAT_DXT23 (14 << 0) -#define R200_TXFORMAT_DXT45 (15 << 0) -#define R200_TXFORMAT_DVDU88 (18 << 0) -#define R200_TXFORMAT_LDVDU655 (19 << 0) -#define R200_TXFORMAT_LDVDU8888 (20 << 0) -#define R200_TXFORMAT_GR1616 (21 << 0) -#define R200_TXFORMAT_ABGR8888 (22 << 0) -#define R200_TXFORMAT_BGR111110 (23 << 0) -#define R200_TXFORMAT_FORMAT_MASK (31 << 0) -#define R200_TXFORMAT_FORMAT_SHIFT 0 -#define R200_TXFORMAT_APPLE_YUV (1 << 5) -#define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) -#define R200_TXFORMAT_NON_POWER2 (1 << 7) -#define R200_TXFORMAT_WIDTH_MASK (15 << 8) -#define R200_TXFORMAT_WIDTH_SHIFT 8 -#define R200_TXFORMAT_HEIGHT_MASK (15 << 12) -#define R200_TXFORMAT_HEIGHT_SHIFT 12 -#define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */ -#define R200_TXFORMAT_F5_WIDTH_SHIFT 16 -#define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20) -#define R200_TXFORMAT_F5_HEIGHT_SHIFT 20 -#define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) -#define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) -#define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) -#define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24) -#define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24) -#define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24) -#define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24) -#define R200_TXFORMAT_ST_ROUTE_SHIFT 24 -#define R200_TXFORMAT_LOOKUP_DISABLE (1 << 27) -#define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) -#define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) -#define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) -#define R200_PP_TXFORMAT_X_0 0x2c08 -#define R200_DEPTH_LOG2_MASK (0xf << 0) -#define R200_DEPTH_LOG2_SHIFT 0 -#define R200_VOLUME_FILTER_SHIFT 4 -#define R200_VOLUME_FILTER_MASK (1 << 4) -#define R200_VOLUME_FILTER_NEAREST (0 << 4) -#define R200_VOLUME_FILTER_LINEAR (1 << 4) -#define R200_WRAPEN_Q (1 << 8) -#define R200_CLAMP_Q_WRAP (0 << 9) -#define R200_CLAMP_Q_MIRROR (1 << 9) -#define R200_CLAMP_Q_CLAMP_LAST (2 << 9) -#define R200_CLAMP_Q_MIRROR_CLAMP_LAST (3 << 9) -#define R200_CLAMP_Q_CLAMP_BORDER (4 << 9) -#define R200_CLAMP_Q_MIRROR_CLAMP_BORDER (5 << 9) -#define R200_CLAMP_Q_CLAMP_GL (6 << 9) -#define R200_CLAMP_Q_MIRROR_CLAMP_GL (7 << 9) -#define R200_CLAMP_Q_MASK (7 << 9) -#define R200_MIN_MIP_LEVEL_MASK (0x0f << 12) -#define R200_MIN_MIP_LEVEL_SHIFT 12 -#define R200_TEXCOORD_NONPROJ (0 << 16) -#define R200_TEXCOORD_CUBIC_ENV (1 << 16) -#define R200_TEXCOORD_VOLUME (2 << 16) -#define R200_TEXCOORD_PROJ (3 << 16) -#define R200_TEXCOORD_DEPTH (4 << 16) -#define R200_TEXCOORD_1D_PROJ (5 << 16) -#define R200_TEXCOORD_1D (6 << 16) -#define R200_TEXCOORD_ZERO (7 << 16) -#define R200_TEXCOORD_MASK (7 << 16) -#define R200_LOD_BIAS_MASK (0xfff80000) -#define R200_LOD_BIAS_FIXED_ONE (0x08000000) -#define R200_LOD_BIAS_CORRECTION (0x00600000) -#define R200_LOD_BIAS_SHIFT 19 -#define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */ -#define R200_PP_TX_WIDTHMASK_SHIFT 0 -#define R200_PP_TX_HEIGHTMASK_SHIFT 16 - -#define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */ -#define R200_PP_BORDER_COLOR_0 0x2c14 -#define R200_PP_CUBIC_FACES_0 0x2c18 -#define R200_FACE_WIDTH_1_SHIFT 0 -#define R200_FACE_HEIGHT_1_SHIFT 4 -#define R200_FACE_WIDTH_1_MASK (0xf << 0) -#define R200_FACE_HEIGHT_1_MASK (0xf << 4) -#define R200_FACE_WIDTH_2_SHIFT 8 -#define R200_FACE_HEIGHT_2_SHIFT 12 -#define R200_FACE_WIDTH_2_MASK (0xf << 8) -#define R200_FACE_HEIGHT_2_MASK (0xf << 12) -#define R200_FACE_WIDTH_3_SHIFT 16 -#define R200_FACE_HEIGHT_3_SHIFT 20 -#define R200_FACE_WIDTH_3_MASK (0xf << 16) -#define R200_FACE_HEIGHT_3_MASK (0xf << 20) -#define R200_FACE_WIDTH_4_SHIFT 24 -#define R200_FACE_HEIGHT_4_SHIFT 28 -#define R200_FACE_WIDTH_4_MASK (0xf << 24) -#define R200_FACE_HEIGHT_4_MASK (0xf << 28) -#define R200_PP_TXMULTI_CTL_0 0x2c1c /* name from ddx, rest RE... */ -#define R200_PASS1_TXFORMAT_LOOKUP_DISABLE (1 << 0) -#define R200_PASS1_TEXCOORD_NONPROJ (0 << 1) -#define R200_PASS1_TEXCOORD_CUBIC_ENV (1 << 1) -#define R200_PASS1_TEXCOORD_VOLUME (2 << 1) -#define R200_PASS1_TEXCOORD_PROJ (3 << 1) -#define R200_PASS1_TEXCOORD_DEPTH (4 << 1) -#define R200_PASS1_TEXCOORD_1D_PROJ (5 << 1) -#define R200_PASS1_TEXCOORD_1D (6 << 1) /* pass1 texcoords only */ -#define R200_PASS1_TEXCOORD_ZERO (7 << 1) /* verifed for 2d targets! */ -#define R200_PASS1_TEXCOORD_MASK (7 << 1) /* assumed same values as for pass2 */ -#define R200_PASS1_ST_ROUTE_STQ0 (0 << 4) -#define R200_PASS1_ST_ROUTE_STQ1 (1 << 4) -#define R200_PASS1_ST_ROUTE_STQ2 (2 << 4) -#define R200_PASS1_ST_ROUTE_STQ3 (3 << 4) -#define R200_PASS1_ST_ROUTE_STQ4 (4 << 4) -#define R200_PASS1_ST_ROUTE_STQ5 (5 << 4) -#define R200_PASS1_ST_ROUTE_MASK (7 << 4) -#define R200_PASS1_ST_ROUTE_SHIFT (4) -#define R200_PASS2_COORDS_REG_0 (2 << 24) -#define R200_PASS2_COORDS_REG_1 (3 << 24) -#define R200_PASS2_COORDS_REG_2 (4 << 24) -#define R200_PASS2_COORDS_REG_3 (5 << 24) -#define R200_PASS2_COORDS_REG_4 (6 << 24) -#define R200_PASS2_COORDS_REG_5 (7 << 24) -#define R200_PASS2_COORDS_REG_MASK (0x7 << 24) -#define R200_PASS2_COORDS_REG_SHIFT (24) -#define R200_PP_TXFILTER_1 0x2c20 -#define R200_PP_TXFORMAT_1 0x2c24 -#define R200_PP_TXFORMAT_X_1 0x2c28 -#define R200_PP_TXSIZE_1 0x2c2c -#define R200_PP_TXPITCH_1 0x2c30 -#define R200_PP_BORDER_COLOR_1 0x2c34 -#define R200_PP_CUBIC_FACES_1 0x2c38 -#define R200_PP_TXMULTI_CTL_1 0x2c3c -#define R200_PP_TXFILTER_2 0x2c40 -#define R200_PP_TXFORMAT_2 0x2c44 -#define R200_PP_TXSIZE_2 0x2c4c -#define R200_PP_TXFORMAT_X_2 0x2c48 -#define R200_PP_TXPITCH_2 0x2c50 -#define R200_PP_BORDER_COLOR_2 0x2c54 -#define R200_PP_CUBIC_FACES_2 0x2c58 -#define R200_PP_TXMULTI_CTL_2 0x2c5c -#define R200_PP_TXFILTER_3 0x2c60 -#define R200_PP_TXFORMAT_3 0x2c64 -#define R200_PP_TXSIZE_3 0x2c6c -#define R200_PP_TXFORMAT_X_3 0x2c68 -#define R200_PP_TXPITCH_3 0x2c70 -#define R200_PP_BORDER_COLOR_3 0x2c74 -#define R200_PP_CUBIC_FACES_3 0x2c78 -#define R200_PP_TXMULTI_CTL_3 0x2c7c -#define R200_PP_TXFILTER_4 0x2c80 -#define R200_PP_TXFORMAT_4 0x2c84 -#define R200_PP_TXSIZE_4 0x2c8c -#define R200_PP_TXFORMAT_X_4 0x2c88 -#define R200_PP_TXPITCH_4 0x2c90 -#define R200_PP_BORDER_COLOR_4 0x2c94 -#define R200_PP_CUBIC_FACES_4 0x2c98 -#define R200_PP_TXMULTI_CTL_4 0x2c9c -#define R200_PP_TXFILTER_5 0x2ca0 -#define R200_PP_TXFORMAT_5 0x2ca4 -#define R200_PP_TXSIZE_5 0x2cac -#define R200_PP_TXFORMAT_X_5 0x2ca8 -#define R200_PP_TXPITCH_5 0x2cb0 -#define R200_PP_BORDER_COLOR_5 0x2cb4 -#define R200_PP_CUBIC_FACES_5 0x2cb8 -#define R200_PP_TXMULTI_CTL_5 0x2cbc -/* gap */ -#define R200_PP_CNTL_X 0x2cc4 /* Reveree engineered from fglrx */ -#define R200_PPX_TEX_0_ENABLE (1 << 0) -#define R200_PPX_TEX_1_ENABLE (1 << 1) -#define R200_PPX_TEX_2_ENABLE (1 << 2) -#define R200_PPX_TEX_3_ENABLE (1 << 3) -#define R200_PPX_TEX_4_ENABLE (1 << 4) -#define R200_PPX_TEX_5_ENABLE (1 << 5) -#define R200_PPX_TEX_ENABLE_MASK (0x3f << 0) -#define R200_PPX_OUTPUT_REG_0 (1 << 6) -#define R200_PPX_OUTPUT_REG_1 (1 << 7) -#define R200_PPX_OUTPUT_REG_2 (1 << 8) -#define R200_PPX_OUTPUT_REG_3 (1 << 9) -#define R200_PPX_OUTPUT_REG_4 (1 << 10) -#define R200_PPX_OUTPUT_REG_5 (1 << 11) -#define R200_PPX_OUTPUT_REG_MASK (0x3f << 6) -#define R200_PPX_OUTPUT_REG_0_SHIFT (6) -#define R200_PPX_PFS_INST0_ENABLE (1 << 12) -#define R200_PPX_PFS_INST1_ENABLE (1 << 13) -#define R200_PPX_PFS_INST2_ENABLE (1 << 14) -#define R200_PPX_PFS_INST3_ENABLE (1 << 15) -#define R200_PPX_PFS_INST4_ENABLE (1 << 16) -#define R200_PPX_PFS_INST5_ENABLE (1 << 17) -#define R200_PPX_PFS_INST6_ENABLE (1 << 18) -#define R200_PPX_PFS_INST7_ENABLE (1 << 19) -#define R200_PPX_PFS_INST_ENABLE_MASK (0xff << 12) -#define R200_PPX_FPS_INST0_ENABLE_SHIFT (12) -/* gap */ -#define R200_PP_TRI_PERF 0x2cf8 -#define R200_TRI_CUTOFF_MASK (0x1f << 0) -#define R200_PP_PERF_CNTL 0x2cfc -#define R200_PP_TXOFFSET_0 0x2d00 -#define R200_TXO_ENDIAN_NO_SWAP (0 << 0) -#define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) -#define R200_TXO_ENDIAN_WORD_SWAP (2 << 0) -#define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0) -#define R200_TXO_MACRO_TILE (1 << 2) -#define R200_TXO_MICRO_TILE (1 << 3) -#define R200_TXO_OFFSET_MASK 0xffffffe0 -#define R200_TXO_OFFSET_SHIFT 5 -#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 -#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 -#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c -#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 -#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 -#define R200_PP_TXOFFSET_1 0x2d18 -#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c -#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 -#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 -#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 -#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c -#define R200_PP_TXOFFSET_2 0x2d30 -#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 -#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 -#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c -#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 -#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 -#define R200_PP_TXOFFSET_3 0x2d48 -#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c -#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 -#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 -#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 -#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c -#define R200_PP_TXOFFSET_4 0x2d60 -#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 -#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 -#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c -#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 -#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 -#define R200_PP_TXOFFSET_5 0x2d78 -#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c -#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 -#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 -#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 -#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c -/* gap */ -#define R200_PP_TAM_DEBUG3 0x2d9c -/* gap */ -#define R200_PP_TFACTOR_0 0x2ee0 -#define R200_PP_TFACTOR_1 0x2ee4 -#define R200_PP_TFACTOR_2 0x2ee8 -#define R200_PP_TFACTOR_3 0x2eec -#define R200_PP_TFACTOR_4 0x2ef0 -#define R200_PP_TFACTOR_5 0x2ef4 -#define R200_PP_TFACTOR_6 0x2ef8 -#define R200_PP_TFACTOR_7 0x2efc -#define R200_PP_TXCBLEND_0 0x2f00 -#define R200_TXC_ARG_A_ZERO (0) -#define R200_TXC_ARG_A_CURRENT_COLOR (2) -#define R200_TXC_ARG_A_CURRENT_ALPHA (3) -#define R200_TXC_ARG_A_DIFFUSE_COLOR (4) -#define R200_TXC_ARG_A_DIFFUSE_ALPHA (5) -#define R200_TXC_ARG_A_SPECULAR_COLOR (6) -#define R200_TXC_ARG_A_SPECULAR_ALPHA (7) -#define R200_TXC_ARG_A_TFACTOR_COLOR (8) -#define R200_TXC_ARG_A_TFACTOR_ALPHA (9) -#define R200_TXC_ARG_A_R0_COLOR (10) -#define R200_TXC_ARG_A_R0_ALPHA (11) -#define R200_TXC_ARG_A_R1_COLOR (12) -#define R200_TXC_ARG_A_R1_ALPHA (13) -#define R200_TXC_ARG_A_R2_COLOR (14) -#define R200_TXC_ARG_A_R2_ALPHA (15) -#define R200_TXC_ARG_A_R3_COLOR (16) -#define R200_TXC_ARG_A_R3_ALPHA (17) -#define R200_TXC_ARG_A_R4_COLOR (18) -#define R200_TXC_ARG_A_R4_ALPHA (19) -#define R200_TXC_ARG_A_R5_COLOR (20) -#define R200_TXC_ARG_A_R5_ALPHA (21) -#define R200_TXC_ARG_A_TFACTOR1_COLOR (26) -#define R200_TXC_ARG_A_TFACTOR1_ALPHA (27) -#define R200_TXC_ARG_A_MASK (31 << 0) -#define R200_TXC_ARG_A_SHIFT 0 -#define R200_TXC_ARG_B_ZERO (0<<5) -#define R200_TXC_ARG_B_CURRENT_COLOR (2<<5) -#define R200_TXC_ARG_B_CURRENT_ALPHA (3<<5) -#define R200_TXC_ARG_B_DIFFUSE_COLOR (4<<5) -#define R200_TXC_ARG_B_DIFFUSE_ALPHA (5<<5) -#define R200_TXC_ARG_B_SPECULAR_COLOR (6<<5) -#define R200_TXC_ARG_B_SPECULAR_ALPHA (7<<5) -#define R200_TXC_ARG_B_TFACTOR_COLOR (8<<5) -#define R200_TXC_ARG_B_TFACTOR_ALPHA (9<<5) -#define R200_TXC_ARG_B_R0_COLOR (10<<5) -#define R200_TXC_ARG_B_R0_ALPHA (11<<5) -#define R200_TXC_ARG_B_R1_COLOR (12<<5) -#define R200_TXC_ARG_B_R1_ALPHA (13<<5) -#define R200_TXC_ARG_B_R2_COLOR (14<<5) -#define R200_TXC_ARG_B_R2_ALPHA (15<<5) -#define R200_TXC_ARG_B_R3_COLOR (16<<5) -#define R200_TXC_ARG_B_R3_ALPHA (17<<5) -#define R200_TXC_ARG_B_R4_COLOR (18<<5) -#define R200_TXC_ARG_B_R4_ALPHA (19<<5) -#define R200_TXC_ARG_B_R5_COLOR (20<<5) -#define R200_TXC_ARG_B_R5_ALPHA (21<<5) -#define R200_TXC_ARG_B_TFACTOR1_COLOR (26<<5) -#define R200_TXC_ARG_B_TFACTOR1_ALPHA (27<<5) -#define R200_TXC_ARG_B_MASK (31 << 5) -#define R200_TXC_ARG_B_SHIFT 5 -#define R200_TXC_ARG_C_ZERO (0<<10) -#define R200_TXC_ARG_C_CURRENT_COLOR (2<<10) -#define R200_TXC_ARG_C_CURRENT_ALPHA (3<<10) -#define R200_TXC_ARG_C_DIFFUSE_COLOR (4<<10) -#define R200_TXC_ARG_C_DIFFUSE_ALPHA (5<<10) -#define R200_TXC_ARG_C_SPECULAR_COLOR (6<<10) -#define R200_TXC_ARG_C_SPECULAR_ALPHA (7<<10) -#define R200_TXC_ARG_C_TFACTOR_COLOR (8<<10) -#define R200_TXC_ARG_C_TFACTOR_ALPHA (9<<10) -#define R200_TXC_ARG_C_R0_COLOR (10<<10) -#define R200_TXC_ARG_C_R0_ALPHA (11<<10) -#define R200_TXC_ARG_C_R1_COLOR (12<<10) -#define R200_TXC_ARG_C_R1_ALPHA (13<<10) -#define R200_TXC_ARG_C_R2_COLOR (14<<10) -#define R200_TXC_ARG_C_R2_ALPHA (15<<10) -#define R200_TXC_ARG_C_R3_COLOR (16<<10) -#define R200_TXC_ARG_C_R3_ALPHA (17<<10) -#define R200_TXC_ARG_C_R4_COLOR (18<<10) -#define R200_TXC_ARG_C_R4_ALPHA (19<<10) -#define R200_TXC_ARG_C_R5_COLOR (20<<10) -#define R200_TXC_ARG_C_R5_ALPHA (21<<10) -#define R200_TXC_ARG_C_TFACTOR1_COLOR (26<<10) -#define R200_TXC_ARG_C_TFACTOR1_ALPHA (27<<10) -#define R200_TXC_ARG_C_MASK (31 << 10) -#define R200_TXC_ARG_C_SHIFT 10 -#define R200_TXC_COMP_ARG_A (1 << 16) -#define R200_TXC_COMP_ARG_A_SHIFT (16) -#define R200_TXC_BIAS_ARG_A (1 << 17) -#define R200_TXC_SCALE_ARG_A (1 << 18) -#define R200_TXC_NEG_ARG_A (1 << 19) -#define R200_TXC_COMP_ARG_B (1 << 20) -#define R200_TXC_COMP_ARG_B_SHIFT (20) -#define R200_TXC_BIAS_ARG_B (1 << 21) -#define R200_TXC_SCALE_ARG_B (1 << 22) -#define R200_TXC_NEG_ARG_B (1 << 23) -#define R200_TXC_COMP_ARG_C (1 << 24) -#define R200_TXC_COMP_ARG_C_SHIFT (24) -#define R200_TXC_BIAS_ARG_C (1 << 25) -#define R200_TXC_SCALE_ARG_C (1 << 26) -#define R200_TXC_NEG_ARG_C (1 << 27) -#define R200_TXC_OP_MADD (0 << 28) -#define R200_TXC_OP_CND0 (2 << 28) -#define R200_TXC_OP_LERP (3 << 28) -#define R200_TXC_OP_DOT3 (4 << 28) -#define R200_TXC_OP_DOT4 (5 << 28) -#define R200_TXC_OP_CONDITIONAL (6 << 28) -#define R200_TXC_OP_DOT2_ADD (7 << 28) -#define R200_TXC_OP_MASK (7 << 28) -#define R200_PP_TXCBLEND2_0 0x2f04 -#define R200_TXC_TFACTOR_SEL_SHIFT 0 -#define R200_TXC_TFACTOR_SEL_MASK 0x7 -#define R200_TXC_TFACTOR1_SEL_SHIFT 4 -#define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4) -#define R200_TXC_SCALE_SHIFT 8 -#define R200_TXC_SCALE_MASK (7 << 8) -#define R200_TXC_SCALE_1X (0 << 8) -#define R200_TXC_SCALE_2X (1 << 8) -#define R200_TXC_SCALE_4X (2 << 8) -#define R200_TXC_SCALE_8X (3 << 8) -#define R200_TXC_SCALE_INV2 (5 << 8) -#define R200_TXC_SCALE_INV4 (6 << 8) -#define R200_TXC_SCALE_INV8 (7 << 8) -#define R200_TXC_CLAMP_SHIFT 12 -#define R200_TXC_CLAMP_MASK (3 << 12) -#define R200_TXC_CLAMP_WRAP (0 << 12) -#define R200_TXC_CLAMP_0_1 (1 << 12) -#define R200_TXC_CLAMP_8_8 (2 << 12) -#define R200_TXC_OUTPUT_REG_SHIFT 16 -#define R200_TXC_OUTPUT_REG_MASK (7 << 16) -#define R200_TXC_OUTPUT_REG_NONE (0 << 16) -#define R200_TXC_OUTPUT_REG_R0 (1 << 16) -#define R200_TXC_OUTPUT_REG_R1 (2 << 16) -#define R200_TXC_OUTPUT_REG_R2 (3 << 16) -#define R200_TXC_OUTPUT_REG_R3 (4 << 16) -#define R200_TXC_OUTPUT_REG_R4 (5 << 16) -#define R200_TXC_OUTPUT_REG_R5 (6 << 16) -#define R200_TXC_OUTPUT_MASK_MASK (7 << 20) -#define R200_TXC_OUTPUT_MASK_RGB (0 << 20) -#define R200_TXC_OUTPUT_MASK_RG (1 << 20) -#define R200_TXC_OUTPUT_MASK_RB (2 << 20) -#define R200_TXC_OUTPUT_MASK_R (3 << 20) -#define R200_TXC_OUTPUT_MASK_GB (4 << 20) -#define R200_TXC_OUTPUT_MASK_G (5 << 20) -#define R200_TXC_OUTPUT_MASK_B (6 << 20) -#define R200_TXC_OUTPUT_MASK_NONE (7 << 20) -#define R200_TXC_OUTPUT_ROTATE_RGB (0 << 24) -#define R200_TXC_OUTPUT_ROTATE_ARG (1 << 24) -#define R200_TXC_OUTPUT_ROTATE_GBA (2 << 24) -#define R200_TXC_OUTPUT_ROTATE_RGA (3 << 24) -#define R200_TXC_REPL_NORMAL 0 -#define R200_TXC_REPL_RED 1 -#define R200_TXC_REPL_GREEN 2 -#define R200_TXC_REPL_BLUE 3 -#define R200_TXC_REPL_ARG_A_SHIFT 26 -#define R200_TXC_REPL_ARG_A_MASK (3 << 26) -#define R200_TXC_REPL_ARG_B_SHIFT 28 -#define R200_TXC_REPL_ARG_B_MASK (3 << 28) -#define R200_TXC_REPL_ARG_C_SHIFT 30 -#define R200_TXC_REPL_ARG_C_MASK (3 << 30) -#define R200_PP_TXABLEND_0 0x2f08 -#define R200_TXA_ARG_A_ZERO (0) -#define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */ -#define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */ -#define R200_TXA_ARG_A_DIFFUSE_ALPHA (4) -#define R200_TXA_ARG_A_DIFFUSE_BLUE (5) -#define R200_TXA_ARG_A_SPECULAR_ALPHA (6) -#define R200_TXA_ARG_A_SPECULAR_BLUE (7) -#define R200_TXA_ARG_A_TFACTOR_ALPHA (8) -#define R200_TXA_ARG_A_TFACTOR_BLUE (9) -#define R200_TXA_ARG_A_R0_ALPHA (10) -#define R200_TXA_ARG_A_R0_BLUE (11) -#define R200_TXA_ARG_A_R1_ALPHA (12) -#define R200_TXA_ARG_A_R1_BLUE (13) -#define R200_TXA_ARG_A_R2_ALPHA (14) -#define R200_TXA_ARG_A_R2_BLUE (15) -#define R200_TXA_ARG_A_R3_ALPHA (16) -#define R200_TXA_ARG_A_R3_BLUE (17) -#define R200_TXA_ARG_A_R4_ALPHA (18) -#define R200_TXA_ARG_A_R4_BLUE (19) -#define R200_TXA_ARG_A_R5_ALPHA (20) -#define R200_TXA_ARG_A_R5_BLUE (21) -#define R200_TXA_ARG_A_TFACTOR1_ALPHA (26) -#define R200_TXA_ARG_A_TFACTOR1_BLUE (27) -#define R200_TXA_ARG_A_MASK (31 << 0) -#define R200_TXA_ARG_A_SHIFT 0 -#define R200_TXA_ARG_B_ZERO (0<<5) -#define R200_TXA_ARG_B_CURRENT_ALPHA (2<<5) /* guess */ -#define R200_TXA_ARG_B_CURRENT_BLUE (3<<5) /* guess */ -#define R200_TXA_ARG_B_DIFFUSE_ALPHA (4<<5) -#define R200_TXA_ARG_B_DIFFUSE_BLUE (5<<5) -#define R200_TXA_ARG_B_SPECULAR_ALPHA (6<<5) -#define R200_TXA_ARG_B_SPECULAR_BLUE (7<<5) -#define R200_TXA_ARG_B_TFACTOR_ALPHA (8<<5) -#define R200_TXA_ARG_B_TFACTOR_BLUE (9<<5) -#define R200_TXA_ARG_B_R0_ALPHA (10<<5) -#define R200_TXA_ARG_B_R0_BLUE (11<<5) -#define R200_TXA_ARG_B_R1_ALPHA (12<<5) -#define R200_TXA_ARG_B_R1_BLUE (13<<5) -#define R200_TXA_ARG_B_R2_ALPHA (14<<5) -#define R200_TXA_ARG_B_R2_BLUE (15<<5) -#define R200_TXA_ARG_B_R3_ALPHA (16<<5) -#define R200_TXA_ARG_B_R3_BLUE (17<<5) -#define R200_TXA_ARG_B_R4_ALPHA (18<<5) -#define R200_TXA_ARG_B_R4_BLUE (19<<5) -#define R200_TXA_ARG_B_R5_ALPHA (20<<5) -#define R200_TXA_ARG_B_R5_BLUE (21<<5) -#define R200_TXA_ARG_B_TFACTOR1_ALPHA (26<<5) -#define R200_TXA_ARG_B_TFACTOR1_BLUE (27<<5) -#define R200_TXA_ARG_B_MASK (31 << 5) -#define R200_TXA_ARG_B_SHIFT 5 -#define R200_TXA_ARG_C_ZERO (0<<10) -#define R200_TXA_ARG_C_CURRENT_ALPHA (2<<10) /* guess */ -#define R200_TXA_ARG_C_CURRENT_BLUE (3<<10) /* guess */ -#define R200_TXA_ARG_C_DIFFUSE_ALPHA (4<<10) -#define R200_TXA_ARG_C_DIFFUSE_BLUE (5<<10) -#define R200_TXA_ARG_C_SPECULAR_ALPHA (6<<10) -#define R200_TXA_ARG_C_SPECULAR_BLUE (7<<10) -#define R200_TXA_ARG_C_TFACTOR_ALPHA (8<<10) -#define R200_TXA_ARG_C_TFACTOR_BLUE (9<<10) -#define R200_TXA_ARG_C_R0_ALPHA (10<<10) -#define R200_TXA_ARG_C_R0_BLUE (11<<10) -#define R200_TXA_ARG_C_R1_ALPHA (12<<10) -#define R200_TXA_ARG_C_R1_BLUE (13<<10) -#define R200_TXA_ARG_C_R2_ALPHA (14<<10) -#define R200_TXA_ARG_C_R2_BLUE (15<<10) -#define R200_TXA_ARG_C_R3_ALPHA (16<<10) -#define R200_TXA_ARG_C_R3_BLUE (17<<10) -#define R200_TXA_ARG_C_R4_ALPHA (18<<10) -#define R200_TXA_ARG_C_R4_BLUE (19<<10) -#define R200_TXA_ARG_C_R5_ALPHA (20<<10) -#define R200_TXA_ARG_C_R5_BLUE (21<<10) -#define R200_TXA_ARG_C_TFACTOR1_ALPHA (26<<10) -#define R200_TXA_ARG_C_TFACTOR1_BLUE (27<<10) -#define R200_TXA_ARG_C_MASK (31 << 10) -#define R200_TXA_ARG_C_SHIFT 10 -#define R200_TXA_COMP_ARG_A (1 << 16) -#define R200_TXA_COMP_ARG_A_SHIFT (16) -#define R200_TXA_BIAS_ARG_A (1 << 17) -#define R200_TXA_SCALE_ARG_A (1 << 18) -#define R200_TXA_NEG_ARG_A (1 << 19) -#define R200_TXA_COMP_ARG_B (1 << 20) -#define R200_TXA_COMP_ARG_B_SHIFT (20) -#define R200_TXA_BIAS_ARG_B (1 << 21) -#define R200_TXA_SCALE_ARG_B (1 << 22) -#define R200_TXA_NEG_ARG_B (1 << 23) -#define R200_TXA_COMP_ARG_C (1 << 24) -#define R200_TXA_COMP_ARG_C_SHIFT (24) -#define R200_TXA_BIAS_ARG_C (1 << 25) -#define R200_TXA_SCALE_ARG_C (1 << 26) -#define R200_TXA_NEG_ARG_C (1 << 27) -#define R200_TXA_OP_MADD (0 << 28) -#define R200_TXA_OP_CND0 (2 << 28) -#define R200_TXA_OP_LERP (3 << 28) -#define R200_TXA_OP_CONDITIONAL (6 << 28) -#define R200_TXA_OP_MASK (7 << 28) -#define R200_PP_TXABLEND2_0 0x2f0c -#define R200_TXA_TFACTOR_SEL_SHIFT 0 -#define R200_TXA_TFACTOR_SEL_MASK 0x7 -#define R200_TXA_TFACTOR1_SEL_SHIFT 4 -#define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4) -#define R200_TXA_SCALE_SHIFT 8 -#define R200_TXA_SCALE_MASK (7 << 8) -#define R200_TXA_SCALE_1X (0 << 8) -#define R200_TXA_SCALE_2X (1 << 8) -#define R200_TXA_SCALE_4X (2 << 8) -#define R200_TXA_SCALE_8X (3 << 8) -#define R200_TXA_SCALE_INV2 (5 << 8) -#define R200_TXA_SCALE_INV4 (6 << 8) -#define R200_TXA_SCALE_INV8 (7 << 8) -#define R200_TXA_CLAMP_SHIFT 12 -#define R200_TXA_CLAMP_MASK (3 << 12) -#define R200_TXA_CLAMP_WRAP (0 << 12) -#define R200_TXA_CLAMP_0_1 (1 << 12) -#define R200_TXA_CLAMP_8_8 (2 << 12) -#define R200_TXA_OUTPUT_REG_SHIFT 16 -#define R200_TXA_OUTPUT_REG_MASK (7 << 16) -#define R200_TXA_OUTPUT_REG_NONE (0 << 16) -#define R200_TXA_OUTPUT_REG_R0 (1 << 16) -#define R200_TXA_OUTPUT_REG_R1 (2 << 16) -#define R200_TXA_OUTPUT_REG_R2 (3 << 16) -#define R200_TXA_OUTPUT_REG_R3 (4 << 16) -#define R200_TXA_OUTPUT_REG_R4 (5 << 16) -#define R200_TXA_OUTPUT_REG_R5 (6 << 16) -#define R200_TXA_DOT_ALPHA (1 << 20) -#define R200_TXA_REPL_NORMAL 0 -#define R200_TXA_REPL_RED 1 -#define R200_TXA_REPL_GREEN 2 -#define R200_TXA_REPL_ARG_A_SHIFT 26 -#define R200_TXA_REPL_ARG_A_MASK (3 << 26) -#define R200_TXA_REPL_ARG_B_SHIFT 28 -#define R200_TXA_REPL_ARG_B_MASK (3 << 28) -#define R200_TXA_REPL_ARG_C_SHIFT 30 -#define R200_TXA_REPL_ARG_C_MASK (3 << 30) -#define R200_PP_TXCBLEND_1 0x2f10 -#define R200_PP_TXCBLEND2_1 0x2f14 -#define R200_PP_TXABLEND_1 0x2f18 -#define R200_PP_TXABLEND2_1 0x2f1c -#define R200_PP_TXCBLEND_2 0x2f20 -#define R200_PP_TXCBLEND2_2 0x2f24 -#define R200_PP_TXABLEND_2 0x2f28 -#define R200_PP_TXABLEND2_2 0x2f2c -#define R200_PP_TXCBLEND_3 0x2f30 -#define R200_PP_TXCBLEND2_3 0x2f34 -#define R200_PP_TXABLEND_3 0x2f38 -#define R200_PP_TXABLEND2_3 0x2f3c -#define R200_PP_TXCBLEND_4 0x2f40 -#define R200_PP_TXCBLEND2_4 0x2f44 -#define R200_PP_TXABLEND_4 0x2f48 -#define R200_PP_TXABLEND2_4 0x2f4c -#define R200_PP_TXCBLEND_5 0x2f50 -#define R200_PP_TXCBLEND2_5 0x2f54 -#define R200_PP_TXABLEND_5 0x2f58 -#define R200_PP_TXABLEND2_5 0x2f5c -#define R200_PP_TXCBLEND_6 0x2f60 -#define R200_PP_TXCBLEND2_6 0x2f64 -#define R200_PP_TXABLEND_6 0x2f68 -#define R200_PP_TXABLEND2_6 0x2f6c -#define R200_PP_TXCBLEND_7 0x2f70 -#define R200_PP_TXCBLEND2_7 0x2f74 -#define R200_PP_TXABLEND_7 0x2f78 -#define R200_PP_TXABLEND2_7 0x2f7c -#define R200_PP_TXCBLEND_8 0x2f80 -#define R200_PP_TXCBLEND2_8 0x2f84 -#define R200_PP_TXABLEND_8 0x2f88 -#define R200_PP_TXABLEND2_8 0x2f8c -#define R200_PP_TXCBLEND_9 0x2f90 -#define R200_PP_TXCBLEND2_9 0x2f94 -#define R200_PP_TXABLEND_9 0x2f98 -#define R200_PP_TXABLEND2_9 0x2f9c -#define R200_PP_TXCBLEND_10 0x2fa0 -#define R200_PP_TXCBLEND2_10 0x2fa4 -#define R200_PP_TXABLEND_10 0x2fa8 -#define R200_PP_TXABLEND2_10 0x2fac -#define R200_PP_TXCBLEND_11 0x2fb0 -#define R200_PP_TXCBLEND2_11 0x2fb4 -#define R200_PP_TXABLEND_11 0x2fb8 -#define R200_PP_TXABLEND2_11 0x2fbc -#define R200_PP_TXCBLEND_12 0x2fc0 -#define R200_PP_TXCBLEND2_12 0x2fc4 -#define R200_PP_TXABLEND_12 0x2fc8 -#define R200_PP_TXABLEND2_12 0x2fcc -#define R200_PP_TXCBLEND_13 0x2fd0 -#define R200_PP_TXCBLEND2_13 0x2fd4 -#define R200_PP_TXABLEND_13 0x2fd8 -#define R200_PP_TXABLEND2_13 0x2fdc -#define R200_PP_TXCBLEND_14 0x2fe0 -#define R200_PP_TXCBLEND2_14 0x2fe4 -#define R200_PP_TXABLEND_14 0x2fe8 -#define R200_PP_TXABLEND2_14 0x2fec -#define R200_PP_TXCBLEND_15 0x2ff0 -#define R200_PP_TXCBLEND2_15 0x2ff4 -#define R200_PP_TXABLEND_15 0x2ff8 -#define R200_PP_TXABLEND2_15 0x2ffc -/* gap */ -#define R200_RB3D_BLENDCOLOR 0x3218 /* ARGB 8888 */ -#define R200_RB3D_ABLENDCNTL 0x321C /* see BLENDCTL */ -#define R200_RB3D_CBLENDCNTL 0x3220 /* see BLENDCTL */ - - -/* - * Offsets in TCL vector state. NOTE: Hardwiring matrix positions. - * Multiple contexts could collaberate to eliminate state bouncing. - */ -#define R200_VS_LIGHT_AMBIENT_ADDR 0x00000028 -#define R200_VS_LIGHT_DIFFUSE_ADDR 0x00000030 -#define R200_VS_LIGHT_SPECULAR_ADDR 0x00000038 -#define R200_VS_LIGHT_DIRPOS_ADDR 0x00000040 -#define R200_VS_LIGHT_HWVSPOT_ADDR 0x00000048 -#define R200_VS_LIGHT_ATTENUATION_ADDR 0x00000050 -#define R200_VS_SPOT_DUAL_CONE 0x00000058 -#define R200_VS_GLOBAL_AMBIENT_ADDR 0x0000005C -#define R200_VS_FOG_PARAM_ADDR 0x0000005D -#define R200_VS_EYE_VECTOR_ADDR 0x0000005E -#define R200_VS_UCP_ADDR 0x00000060 -#define R200_VS_PNT_SPRITE_VPORT_SCALE 0x00000068 -#define R200_VS_MATRIX_0_MV 0x00000080 -#define R200_VS_MATRIX_1_INV_MV 0x00000084 -#define R200_VS_MATRIX_2_MVP 0x00000088 -#define R200_VS_MATRIX_3_TEX0 0x0000008C -#define R200_VS_MATRIX_4_TEX1 0x00000090 -#define R200_VS_MATRIX_5_TEX2 0x00000094 -#define R200_VS_MATRIX_6_TEX3 0x00000098 -#define R200_VS_MATRIX_7_TEX4 0x0000009C -#define R200_VS_MATRIX_8_TEX5 0x000000A0 -#define R200_VS_MAT_0_EMISS 0x000000B0 -#define R200_VS_MAT_0_AMB 0x000000B1 -#define R200_VS_MAT_0_DIF 0x000000B2 -#define R200_VS_MAT_0_SPEC 0x000000B3 -#define R200_VS_MAT_1_EMISS 0x000000B4 -#define R200_VS_MAT_1_AMB 0x000000B5 -#define R200_VS_MAT_1_DIF 0x000000B6 -#define R200_VS_MAT_1_SPEC 0x000000B7 -#define R200_VS_EYE2CLIP_MTX 0x000000B8 -#define R200_VS_PNT_SPRITE_ATT_CONST 0x000000BC -#define R200_VS_PNT_SPRITE_EYE_IN_MODEL 0x000000BD -#define R200_VS_PNT_SPRITE_CLAMP 0x000000BE -#define R200_VS_MAX 0x000001C0 - -#define R200_PVS_PROG0 0x00000080 -#define R200_PVS_PROG1 0x00000180 -#define R200_PVS_PARAM0 0x00000000 -#define R200_PVS_PARAM1 0x00000100 - -/* - * Offsets in TCL scalar state - */ -#define R200_SS_LIGHT_DCD_ADDR 0x00000000 -#define R200_SS_LIGHT_DCM_ADDR 0x00000008 -#define R200_SS_LIGHT_SPOT_EXPONENT_ADDR 0x00000010 -#define R200_SS_LIGHT_SPOT_CUTOFF_ADDR 0x00000018 -#define R200_SS_LIGHT_SPECULAR_THRESH_ADDR 0x00000020 -#define R200_SS_LIGHT_RANGE_CUTOFF_SQRD 0x00000028 -#define R200_SS_LIGHT_RANGE_ATT_CONST 0x00000030 -#define R200_SS_VERT_GUARD_CLIP_ADJ_ADDR 0x00000080 -#define R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR 0x00000081 -#define R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR 0x00000082 -#define R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 0x00000083 -#define R200_SS_MAT_0_SHININESS 0x00000100 -#define R200_SS_MAT_1_SHININESS 0x00000101 - - -/* - * Matrix indices - */ -#define R200_MTX_MV 0 -#define R200_MTX_IMV 1 -#define R200_MTX_MVP 2 -#define R200_MTX_TEX0 3 -#define R200_MTX_TEX1 4 -#define R200_MTX_TEX2 5 -#define R200_MTX_TEX3 6 -#define R200_MTX_TEX4 7 -#define R200_MTX_TEX5 8 - -/* Color formats for 2d packets - */ -#define R200_CP_COLOR_FORMAT_CI8 2 -#define R200_CP_COLOR_FORMAT_ARGB1555 3 -#define R200_CP_COLOR_FORMAT_RGB565 4 -#define R200_CP_COLOR_FORMAT_ARGB8888 6 -#define R200_CP_COLOR_FORMAT_RGB332 7 -#define R200_CP_COLOR_FORMAT_RGB8 9 -#define R200_CP_COLOR_FORMAT_ARGB4444 15 - - -/* - * CP type-3 packets - */ -#define R200_CP_CMD_NOP 0xC0001000 -#define R200_CP_CMD_NEXT_CHAR 0xC0001900 -#define R200_CP_CMD_PLY_NEXTSCAN 0xC0001D00 -#define R200_CP_CMD_SET_SCISSORS 0xC0001E00 -#define R200_CP_CMD_LOAD_MICROCODE 0xC0002400 -#define R200_CP_CMD_WAIT_FOR_IDLE 0xC0002600 -#define R200_CP_CMD_3D_DRAW_VBUF 0xC0002800 -#define R200_CP_CMD_3D_DRAW_IMMD 0xC0002900 -#define R200_CP_CMD_3D_DRAW_INDX 0xC0002A00 -#define R200_CP_CMD_LOAD_PALETTE 0xC0002C00 -#define R200_CP_CMD_3D_LOAD_VBPNTR 0xC0002F00 -#define R200_CP_CMD_INDX_BUFFER 0xC0003300 -#define R200_CP_CMD_3D_DRAW_VBUF_2 0xC0003400 -#define R200_CP_CMD_3D_DRAW_IMMD_2 0xC0003500 -#define R200_CP_CMD_3D_DRAW_INDX_2 0xC0003600 -#define R200_CP_CMD_PAINT 0xC0009100 -#define R200_CP_CMD_BITBLT 0xC0009200 -#define R200_CP_CMD_SMALLTEXT 0xC0009300 -#define R200_CP_CMD_HOSTDATA_BLT 0xC0009400 -#define R200_CP_CMD_POLYLINE 0xC0009500 -#define R200_CP_CMD_POLYSCANLINES 0xC0009800 -#define R200_CP_CMD_PAINT_MULTI 0xC0009A00 -#define R200_CP_CMD_BITBLT_MULTI 0xC0009B00 -#define R200_CP_CMD_TRANS_BITBLT 0xC0009C00 - -#endif - diff --git a/src/mesa/drivers/dri/r200/r200_sanity.c b/src/mesa/drivers/dri/r200/r200_sanity.c deleted file mode 100644 index 8bef63e413a..00000000000 --- a/src/mesa/drivers/dri/r200/r200_sanity.c +++ /dev/null @@ -1,1453 +0,0 @@ -/************************************************************************** - -Copyright 2002 ATI Technologies Inc., Ontario, Canada, and - VMware, Inc. - -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -ATI, VMWARE AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell <keithw@vmware.com> - * - */ - -#include <errno.h> - -#include "main/glheader.h" - - -#include "r200_context.h" -#include "r200_sanity.h" -#include "radeon_reg.h" -#include "r200_reg.h" - -/* Set this '1' to get more verbiage. - */ -#define MORE_VERBOSE 1 - -#if MORE_VERBOSE -#define VERBOSE (R200_DEBUG & RADEON_VERBOSE) -#define NORMAL (1) -#else -#define VERBOSE 0 -#define NORMAL (R200_DEBUG & RADEON_VERBOSE) -#endif - - -/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in - * 1.3 cmdbuffers allow all previous state to be updated as well as - * the tcl scalar and vector areas. - */ -static struct { - int start; - int len; - const char *name; -} packet[RADEON_MAX_STATE_PACKETS] = { - { RADEON_PP_MISC,7,"RADEON_PP_MISC" }, - { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" }, - { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" }, - { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" }, - { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" }, - { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" }, - { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" }, - { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" }, - { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" }, - { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" }, - { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" }, - { RADEON_RE_MISC,1,"RADEON_RE_MISC" }, - { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" }, - { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" }, - { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" }, - { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" }, - { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" }, - { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" }, - { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" }, - { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" }, - { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" }, - { R200_PP_TXCBLEND_0, 4, "R200_EMIT_PP_TXCBLEND_0" }, - { R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" }, - { R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" }, - { R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" }, - { R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" }, - { R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" }, - { R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" }, - { R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" }, - { R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" }, - { R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" }, - { R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" }, - { R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" }, - { R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" }, - { R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" }, - { R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" }, - { R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" }, - { R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" }, - { R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" }, - { R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" }, - { R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" }, - { R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" }, - { R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" }, - { R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" }, - { R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" }, - { R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" }, - { R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" }, - { R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" }, - { R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" }, - { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" }, - { R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" }, - { R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" }, - { R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" }, - { R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" }, - { R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" }, - { R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" }, - { R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" }, - { R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" }, - { R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" }, - { R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" }, - { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" }, - { R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */ - { R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */ - { R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1" }, - { R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1" }, - { R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2" }, - { R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2" }, - { R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3" }, - { R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3" }, - { R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4" }, - { R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" }, - { R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" }, - { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" }, - { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" }, - { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" }, - { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" }, - { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" }, - { R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL" }, - { RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0" }, - { RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0" }, - { RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1" }, - { RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0" }, - { RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2" }, - { RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" }, - { R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF" }, - { R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */ - { R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"}, - { R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, - { R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, - { R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, - { R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, - { R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, - { R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, - { R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, - { R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"}, -}; - -struct reg_names { - int idx; - const char *name; -}; - -static struct reg_names reg_names[] = { - { R200_PP_MISC, "R200_PP_MISC" }, - { R200_PP_FOG_COLOR, "R200_PP_FOG_COLOR" }, - { R200_RE_SOLID_COLOR, "R200_RE_SOLID_COLOR" }, - { R200_RB3D_BLENDCNTL, "R200_RB3D_BLENDCNTL" }, - { R200_RB3D_DEPTHOFFSET, "R200_RB3D_DEPTHOFFSET" }, - { R200_RB3D_DEPTHPITCH, "R200_RB3D_DEPTHPITCH" }, - { R200_RB3D_ZSTENCILCNTL, "R200_RB3D_ZSTENCILCNTL" }, - { R200_PP_CNTL, "R200_PP_CNTL" }, - { R200_RB3D_CNTL, "R200_RB3D_CNTL" }, - { R200_RB3D_COLOROFFSET, "R200_RB3D_COLOROFFSET" }, - { R200_RE_WIDTH_HEIGHT, "R200_RE_WIDTH_HEIGHT" }, - { R200_RB3D_COLORPITCH, "R200_RB3D_COLORPITCH" }, - { R200_SE_CNTL, "R200_SE_CNTL" }, - { R200_RE_CNTL, "R200_RE_CNTL" }, - { R200_RE_MISC, "R200_RE_MISC" }, - { R200_RE_STIPPLE_ADDR, "R200_RE_STIPPLE_ADDR" }, - { R200_RE_STIPPLE_DATA, "R200_RE_STIPPLE_DATA" }, - { R200_RE_LINE_PATTERN, "R200_RE_LINE_PATTERN" }, - { R200_RE_LINE_STATE, "R200_RE_LINE_STATE" }, - { R200_RE_SCISSOR_TL_0, "R200_RE_SCISSOR_TL_0" }, - { R200_RE_SCISSOR_BR_0, "R200_RE_SCISSOR_BR_0" }, - { R200_RE_SCISSOR_TL_1, "R200_RE_SCISSOR_TL_1" }, - { R200_RE_SCISSOR_BR_1, "R200_RE_SCISSOR_BR_1" }, - { R200_RE_SCISSOR_TL_2, "R200_RE_SCISSOR_TL_2" }, - { R200_RE_SCISSOR_BR_2, "R200_RE_SCISSOR_BR_2" }, - { R200_RB3D_DEPTHXY_OFFSET, "R200_RB3D_DEPTHXY_OFFSET" }, - { R200_RB3D_STENCILREFMASK, "R200_RB3D_STENCILREFMASK" }, - { R200_RB3D_ROPCNTL, "R200_RB3D_ROPCNTL" }, - { R200_RB3D_PLANEMASK, "R200_RB3D_PLANEMASK" }, - { R200_SE_VPORT_XSCALE, "R200_SE_VPORT_XSCALE" }, - { R200_SE_VPORT_XOFFSET, "R200_SE_VPORT_XOFFSET" }, - { R200_SE_VPORT_YSCALE, "R200_SE_VPORT_YSCALE" }, - { R200_SE_VPORT_YOFFSET, "R200_SE_VPORT_YOFFSET" }, - { R200_SE_VPORT_ZSCALE, "R200_SE_VPORT_ZSCALE" }, - { R200_SE_VPORT_ZOFFSET, "R200_SE_VPORT_ZOFFSET" }, - { R200_SE_ZBIAS_FACTOR, "R200_SE_ZBIAS_FACTOR" }, - { R200_SE_ZBIAS_CONSTANT, "R200_SE_ZBIAS_CONSTANT" }, - { R200_SE_LINE_WIDTH, "R200_SE_LINE_WIDTH" }, - { R200_SE_VAP_CNTL, "R200_SE_VAP_CNTL" }, - { R200_SE_VF_CNTL, "R200_SE_VF_CNTL" }, - { R200_SE_VTX_FMT_0, "R200_SE_VTX_FMT_0" }, - { R200_SE_VTX_FMT_1, "R200_SE_VTX_FMT_1" }, - { R200_SE_TCL_OUTPUT_VTX_FMT_0, "R200_SE_TCL_OUTPUT_VTX_FMT_0" }, - { R200_SE_TCL_OUTPUT_VTX_FMT_1, "R200_SE_TCL_OUTPUT_VTX_FMT_1" }, - { R200_SE_VTE_CNTL, "R200_SE_VTE_CNTL" }, - { R200_SE_VTX_NUM_ARRAYS, "R200_SE_VTX_NUM_ARRAYS" }, - { R200_SE_VTX_AOS_ATTR01, "R200_SE_VTX_AOS_ATTR01" }, - { R200_SE_VTX_AOS_ADDR0, "R200_SE_VTX_AOS_ADDR0" }, - { R200_SE_VTX_AOS_ADDR1, "R200_SE_VTX_AOS_ADDR1" }, - { R200_SE_VTX_AOS_ATTR23, "R200_SE_VTX_AOS_ATTR23" }, - { R200_SE_VTX_AOS_ADDR2, "R200_SE_VTX_AOS_ADDR2" }, - { R200_SE_VTX_AOS_ADDR3, "R200_SE_VTX_AOS_ADDR3" }, - { R200_SE_VTX_AOS_ATTR45, "R200_SE_VTX_AOS_ATTR45" }, - { R200_SE_VTX_AOS_ADDR4, "R200_SE_VTX_AOS_ADDR4" }, - { R200_SE_VTX_AOS_ADDR5, "R200_SE_VTX_AOS_ADDR5" }, - { R200_SE_VTX_AOS_ATTR67, "R200_SE_VTX_AOS_ATTR67" }, - { R200_SE_VTX_AOS_ADDR6, "R200_SE_VTX_AOS_ADDR6" }, - { R200_SE_VTX_AOS_ADDR7, "R200_SE_VTX_AOS_ADDR7" }, - { R200_SE_VTX_AOS_ATTR89, "R200_SE_VTX_AOS_ATTR89" }, - { R200_SE_VTX_AOS_ADDR8, "R200_SE_VTX_AOS_ADDR8" }, - { R200_SE_VTX_AOS_ADDR9, "R200_SE_VTX_AOS_ADDR9" }, - { R200_SE_VTX_AOS_ATTR1011, "R200_SE_VTX_AOS_ATTR1011" }, - { R200_SE_VTX_AOS_ADDR10, "R200_SE_VTX_AOS_ADDR10" }, - { R200_SE_VTX_AOS_ADDR11, "R200_SE_VTX_AOS_ADDR11" }, - { R200_SE_VF_MAX_VTX_INDX, "R200_SE_VF_MAX_VTX_INDX" }, - { R200_SE_VF_MIN_VTX_INDX, "R200_SE_VF_MIN_VTX_INDX" }, - { R200_SE_VTX_STATE_CNTL, "R200_SE_VTX_STATE_CNTL" }, - { R200_SE_TCL_VECTOR_INDX_REG, "R200_SE_TCL_VECTOR_INDX_REG" }, - { R200_SE_TCL_VECTOR_DATA_REG, "R200_SE_TCL_VECTOR_DATA_REG" }, - { R200_SE_TCL_SCALAR_INDX_REG, "R200_SE_TCL_SCALAR_INDX_REG" }, - { R200_SE_TCL_SCALAR_DATA_REG, "R200_SE_TCL_SCALAR_DATA_REG" }, - { R200_SE_TCL_MATRIX_SEL_0, "R200_SE_TCL_MATRIX_SEL_0" }, - { R200_SE_TCL_MATRIX_SEL_1, "R200_SE_TCL_MATRIX_SEL_1" }, - { R200_SE_TCL_MATRIX_SEL_2, "R200_SE_TCL_MATRIX_SEL_2" }, - { R200_SE_TCL_MATRIX_SEL_3, "R200_SE_TCL_MATRIX_SEL_3" }, - { R200_SE_TCL_MATRIX_SEL_4, "R200_SE_TCL_MATRIX_SEL_4" }, - { R200_SE_TCL_LIGHT_MODEL_CTL_0, "R200_SE_TCL_LIGHT_MODEL_CTL_0" }, - { R200_SE_TCL_LIGHT_MODEL_CTL_1, "R200_SE_TCL_LIGHT_MODEL_CTL_1" }, - { R200_SE_TCL_PER_LIGHT_CTL_0, "R200_SE_TCL_PER_LIGHT_CTL_0" }, - { R200_SE_TCL_PER_LIGHT_CTL_1, "R200_SE_TCL_PER_LIGHT_CTL_1" }, - { R200_SE_TCL_PER_LIGHT_CTL_2, "R200_SE_TCL_PER_LIGHT_CTL_2" }, - { R200_SE_TCL_PER_LIGHT_CTL_3, "R200_SE_TCL_PER_LIGHT_CTL_3" }, - { R200_SE_TCL_TEX_PROC_CTL_2, "R200_SE_TCL_TEX_PROC_CTL_2" }, - { R200_SE_TCL_TEX_PROC_CTL_3, "R200_SE_TCL_TEX_PROC_CTL_3" }, - { R200_SE_TCL_TEX_PROC_CTL_0, "R200_SE_TCL_TEX_PROC_CTL_0" }, - { R200_SE_TCL_TEX_PROC_CTL_1, "R200_SE_TCL_TEX_PROC_CTL_1" }, - { R200_SE_TC_TEX_CYL_WRAP_CTL, "R200_SE_TC_TEX_CYL_WRAP_CTL" }, - { R200_SE_TCL_UCP_VERT_BLEND_CTL, "R200_SE_TCL_UCP_VERT_BLEND_CTL" }, - { R200_SE_TCL_POINT_SPRITE_CNTL, "R200_SE_TCL_POINT_SPRITE_CNTL" }, - { R200_SE_VTX_ST_POS_0_X_4, "R200_SE_VTX_ST_POS_0_X_4" }, - { R200_SE_VTX_ST_POS_0_Y_4, "R200_SE_VTX_ST_POS_0_Y_4" }, - { R200_SE_VTX_ST_POS_0_Z_4, "R200_SE_VTX_ST_POS_0_Z_4" }, - { R200_SE_VTX_ST_POS_0_W_4, "R200_SE_VTX_ST_POS_0_W_4" }, - { R200_SE_VTX_ST_NORM_0_X, "R200_SE_VTX_ST_NORM_0_X" }, - { R200_SE_VTX_ST_NORM_0_Y, "R200_SE_VTX_ST_NORM_0_Y" }, - { R200_SE_VTX_ST_NORM_0_Z, "R200_SE_VTX_ST_NORM_0_Z" }, - { R200_SE_VTX_ST_PVMS, "R200_SE_VTX_ST_PVMS" }, - { R200_SE_VTX_ST_CLR_0_R, "R200_SE_VTX_ST_CLR_0_R" }, - { R200_SE_VTX_ST_CLR_0_G, "R200_SE_VTX_ST_CLR_0_G" }, - { R200_SE_VTX_ST_CLR_0_B, "R200_SE_VTX_ST_CLR_0_B" }, - { R200_SE_VTX_ST_CLR_0_A, "R200_SE_VTX_ST_CLR_0_A" }, - { R200_SE_VTX_ST_CLR_1_R, "R200_SE_VTX_ST_CLR_1_R" }, - { R200_SE_VTX_ST_CLR_1_G, "R200_SE_VTX_ST_CLR_1_G" }, - { R200_SE_VTX_ST_CLR_1_B, "R200_SE_VTX_ST_CLR_1_B" }, - { R200_SE_VTX_ST_CLR_1_A, "R200_SE_VTX_ST_CLR_1_A" }, - { R200_SE_VTX_ST_CLR_2_R, "R200_SE_VTX_ST_CLR_2_R" }, - { R200_SE_VTX_ST_CLR_2_G, "R200_SE_VTX_ST_CLR_2_G" }, - { R200_SE_VTX_ST_CLR_2_B, "R200_SE_VTX_ST_CLR_2_B" }, - { R200_SE_VTX_ST_CLR_2_A, "R200_SE_VTX_ST_CLR_2_A" }, - { R200_SE_VTX_ST_CLR_3_R, "R200_SE_VTX_ST_CLR_3_R" }, - { R200_SE_VTX_ST_CLR_3_G, "R200_SE_VTX_ST_CLR_3_G" }, - { R200_SE_VTX_ST_CLR_3_B, "R200_SE_VTX_ST_CLR_3_B" }, - { R200_SE_VTX_ST_CLR_3_A, "R200_SE_VTX_ST_CLR_3_A" }, - { R200_SE_VTX_ST_CLR_4_R, "R200_SE_VTX_ST_CLR_4_R" }, - { R200_SE_VTX_ST_CLR_4_G, "R200_SE_VTX_ST_CLR_4_G" }, - { R200_SE_VTX_ST_CLR_4_B, "R200_SE_VTX_ST_CLR_4_B" }, - { R200_SE_VTX_ST_CLR_4_A, "R200_SE_VTX_ST_CLR_4_A" }, - { R200_SE_VTX_ST_CLR_5_R, "R200_SE_VTX_ST_CLR_5_R" }, - { R200_SE_VTX_ST_CLR_5_G, "R200_SE_VTX_ST_CLR_5_G" }, - { R200_SE_VTX_ST_CLR_5_B, "R200_SE_VTX_ST_CLR_5_B" }, - { R200_SE_VTX_ST_CLR_5_A, "R200_SE_VTX_ST_CLR_5_A" }, - { R200_SE_VTX_ST_CLR_6_R, "R200_SE_VTX_ST_CLR_6_R" }, - { R200_SE_VTX_ST_CLR_6_G, "R200_SE_VTX_ST_CLR_6_G" }, - { R200_SE_VTX_ST_CLR_6_B, "R200_SE_VTX_ST_CLR_6_B" }, - { R200_SE_VTX_ST_CLR_6_A, "R200_SE_VTX_ST_CLR_6_A" }, - { R200_SE_VTX_ST_CLR_7_R, "R200_SE_VTX_ST_CLR_7_R" }, - { R200_SE_VTX_ST_CLR_7_G, "R200_SE_VTX_ST_CLR_7_G" }, - { R200_SE_VTX_ST_CLR_7_B, "R200_SE_VTX_ST_CLR_7_B" }, - { R200_SE_VTX_ST_CLR_7_A, "R200_SE_VTX_ST_CLR_7_A" }, - { R200_SE_VTX_ST_TEX_0_S, "R200_SE_VTX_ST_TEX_0_S" }, - { R200_SE_VTX_ST_TEX_0_T, "R200_SE_VTX_ST_TEX_0_T" }, - { R200_SE_VTX_ST_TEX_0_R, "R200_SE_VTX_ST_TEX_0_R" }, - { R200_SE_VTX_ST_TEX_0_Q, "R200_SE_VTX_ST_TEX_0_Q" }, - { R200_SE_VTX_ST_TEX_1_S, "R200_SE_VTX_ST_TEX_1_S" }, - { R200_SE_VTX_ST_TEX_1_T, "R200_SE_VTX_ST_TEX_1_T" }, - { R200_SE_VTX_ST_TEX_1_R, "R200_SE_VTX_ST_TEX_1_R" }, - { R200_SE_VTX_ST_TEX_1_Q, "R200_SE_VTX_ST_TEX_1_Q" }, - { R200_SE_VTX_ST_TEX_2_S, "R200_SE_VTX_ST_TEX_2_S" }, - { R200_SE_VTX_ST_TEX_2_T, "R200_SE_VTX_ST_TEX_2_T" }, - { R200_SE_VTX_ST_TEX_2_R, "R200_SE_VTX_ST_TEX_2_R" }, - { R200_SE_VTX_ST_TEX_2_Q, "R200_SE_VTX_ST_TEX_2_Q" }, - { R200_SE_VTX_ST_TEX_3_S, "R200_SE_VTX_ST_TEX_3_S" }, - { R200_SE_VTX_ST_TEX_3_T, "R200_SE_VTX_ST_TEX_3_T" }, - { R200_SE_VTX_ST_TEX_3_R, "R200_SE_VTX_ST_TEX_3_R" }, - { R200_SE_VTX_ST_TEX_3_Q, "R200_SE_VTX_ST_TEX_3_Q" }, - { R200_SE_VTX_ST_TEX_4_S, "R200_SE_VTX_ST_TEX_4_S" }, - { R200_SE_VTX_ST_TEX_4_T, "R200_SE_VTX_ST_TEX_4_T" }, - { R200_SE_VTX_ST_TEX_4_R, "R200_SE_VTX_ST_TEX_4_R" }, - { R200_SE_VTX_ST_TEX_4_Q, "R200_SE_VTX_ST_TEX_4_Q" }, - { R200_SE_VTX_ST_TEX_5_S, "R200_SE_VTX_ST_TEX_5_S" }, - { R200_SE_VTX_ST_TEX_5_T, "R200_SE_VTX_ST_TEX_5_T" }, - { R200_SE_VTX_ST_TEX_5_R, "R200_SE_VTX_ST_TEX_5_R" }, - { R200_SE_VTX_ST_TEX_5_Q, "R200_SE_VTX_ST_TEX_5_Q" }, - { R200_SE_VTX_ST_PNT_SPRT_SZ, "R200_SE_VTX_ST_PNT_SPRT_SZ" }, - { R200_SE_VTX_ST_DISC_FOG, "R200_SE_VTX_ST_DISC_FOG" }, - { R200_SE_VTX_ST_SHININESS_0, "R200_SE_VTX_ST_SHININESS_0" }, - { R200_SE_VTX_ST_SHININESS_1, "R200_SE_VTX_ST_SHININESS_1" }, - { R200_SE_VTX_ST_BLND_WT_0, "R200_SE_VTX_ST_BLND_WT_0" }, - { R200_SE_VTX_ST_BLND_WT_1, "R200_SE_VTX_ST_BLND_WT_1" }, - { R200_SE_VTX_ST_BLND_WT_2, "R200_SE_VTX_ST_BLND_WT_2" }, - { R200_SE_VTX_ST_BLND_WT_3, "R200_SE_VTX_ST_BLND_WT_3" }, - { R200_SE_VTX_ST_POS_1_X, "R200_SE_VTX_ST_POS_1_X" }, - { R200_SE_VTX_ST_POS_1_Y, "R200_SE_VTX_ST_POS_1_Y" }, - { R200_SE_VTX_ST_POS_1_Z, "R200_SE_VTX_ST_POS_1_Z" }, - { R200_SE_VTX_ST_POS_1_W, "R200_SE_VTX_ST_POS_1_W" }, - { R200_SE_VTX_ST_NORM_1_X, "R200_SE_VTX_ST_NORM_1_X" }, - { R200_SE_VTX_ST_NORM_1_Y, "R200_SE_VTX_ST_NORM_1_Y" }, - { R200_SE_VTX_ST_NORM_1_Z, "R200_SE_VTX_ST_NORM_1_Z" }, - { R200_SE_VTX_ST_USR_CLR_0_R, "R200_SE_VTX_ST_USR_CLR_0_R" }, - { R200_SE_VTX_ST_USR_CLR_0_G, "R200_SE_VTX_ST_USR_CLR_0_G" }, - { R200_SE_VTX_ST_USR_CLR_0_B, "R200_SE_VTX_ST_USR_CLR_0_B" }, - { R200_SE_VTX_ST_USR_CLR_0_A, "R200_SE_VTX_ST_USR_CLR_0_A" }, - { R200_SE_VTX_ST_USR_CLR_1_R, "R200_SE_VTX_ST_USR_CLR_1_R" }, - { R200_SE_VTX_ST_USR_CLR_1_G, "R200_SE_VTX_ST_USR_CLR_1_G" }, - { R200_SE_VTX_ST_USR_CLR_1_B, "R200_SE_VTX_ST_USR_CLR_1_B" }, - { R200_SE_VTX_ST_USR_CLR_1_A, "R200_SE_VTX_ST_USR_CLR_1_A" }, - { R200_SE_VTX_ST_CLR_0_PKD, "R200_SE_VTX_ST_CLR_0_PKD" }, - { R200_SE_VTX_ST_CLR_1_PKD, "R200_SE_VTX_ST_CLR_1_PKD" }, - { R200_SE_VTX_ST_CLR_2_PKD, "R200_SE_VTX_ST_CLR_2_PKD" }, - { R200_SE_VTX_ST_CLR_3_PKD, "R200_SE_VTX_ST_CLR_3_PKD" }, - { R200_SE_VTX_ST_CLR_4_PKD, "R200_SE_VTX_ST_CLR_4_PKD" }, - { R200_SE_VTX_ST_CLR_5_PKD, "R200_SE_VTX_ST_CLR_5_PKD" }, - { R200_SE_VTX_ST_CLR_6_PKD, "R200_SE_VTX_ST_CLR_6_PKD" }, - { R200_SE_VTX_ST_CLR_7_PKD, "R200_SE_VTX_ST_CLR_7_PKD" }, - { R200_SE_VTX_ST_POS_0_X_2, "R200_SE_VTX_ST_POS_0_X_2" }, - { R200_SE_VTX_ST_POS_0_Y_2, "R200_SE_VTX_ST_POS_0_Y_2" }, - { R200_SE_VTX_ST_PAR_CLR_LD, "R200_SE_VTX_ST_PAR_CLR_LD" }, - { R200_SE_VTX_ST_USR_CLR_PKD, "R200_SE_VTX_ST_USR_CLR_PKD" }, - { R200_SE_VTX_ST_POS_0_X_3, "R200_SE_VTX_ST_POS_0_X_3" }, - { R200_SE_VTX_ST_POS_0_Y_3, "R200_SE_VTX_ST_POS_0_Y_3" }, - { R200_SE_VTX_ST_POS_0_Z_3, "R200_SE_VTX_ST_POS_0_Z_3" }, - { R200_SE_VTX_ST_END_OF_PKT, "R200_SE_VTX_ST_END_OF_PKT" }, - { R200_RE_POINTSIZE, "R200_RE_POINTSIZE" }, - { R200_RE_TOP_LEFT, "R200_RE_TOP_LEFT" }, - { R200_RE_AUX_SCISSOR_CNTL, "R200_RE_AUX_SCISSOR_CNTL" }, - { R200_PP_TXFILTER_0, "R200_PP_TXFILTER_0" }, - { R200_PP_TXFORMAT_0, "R200_PP_TXFORMAT_0" }, - { R200_PP_TXSIZE_0, "R200_PP_TXSIZE_0" }, - { R200_PP_TXFORMAT_X_0, "R200_PP_TXFORMAT_X_0" }, - { R200_PP_TXPITCH_0, "R200_PP_TXPITCH_0" }, - { R200_PP_BORDER_COLOR_0, "R200_PP_BORDER_COLOR_0" }, - { R200_PP_CUBIC_FACES_0, "R200_PP_CUBIC_FACES_0" }, - { R200_PP_TXMULTI_CTL_0, "R200_PP_TXMULTI_CTL_0" }, - { R200_PP_TXFILTER_1, "R200_PP_TXFILTER_1" }, - { R200_PP_TXFORMAT_1, "R200_PP_TXFORMAT_1" }, - { R200_PP_TXSIZE_1, "R200_PP_TXSIZE_1" }, - { R200_PP_TXFORMAT_X_1, "R200_PP_TXFORMAT_X_1" }, - { R200_PP_TXPITCH_1, "R200_PP_TXPITCH_1" }, - { R200_PP_BORDER_COLOR_1, "R200_PP_BORDER_COLOR_1" }, - { R200_PP_CUBIC_FACES_1, "R200_PP_CUBIC_FACES_1" }, - { R200_PP_TXMULTI_CTL_1, "R200_PP_TXMULTI_CTL_1" }, - { R200_PP_TXFILTER_2, "R200_PP_TXFILTER_2" }, - { R200_PP_TXFORMAT_2, "R200_PP_TXFORMAT_2" }, - { R200_PP_TXSIZE_2, "R200_PP_TXSIZE_2" }, - { R200_PP_TXFORMAT_X_2, "R200_PP_TXFORMAT_X_2" }, - { R200_PP_TXPITCH_2, "R200_PP_TXPITCH_2" }, - { R200_PP_BORDER_COLOR_2, "R200_PP_BORDER_COLOR_2" }, - { R200_PP_CUBIC_FACES_2, "R200_PP_CUBIC_FACES_2" }, - { R200_PP_TXMULTI_CTL_2, "R200_PP_TXMULTI_CTL_2" }, - { R200_PP_TXFILTER_3, "R200_PP_TXFILTER_3" }, - { R200_PP_TXFORMAT_3, "R200_PP_TXFORMAT_3" }, - { R200_PP_TXSIZE_3, "R200_PP_TXSIZE_3" }, - { R200_PP_TXFORMAT_X_3, "R200_PP_TXFORMAT_X_3" }, - { R200_PP_TXPITCH_3, "R200_PP_TXPITCH_3" }, - { R200_PP_BORDER_COLOR_3, "R200_PP_BORDER_COLOR_3" }, - { R200_PP_CUBIC_FACES_3, "R200_PP_CUBIC_FACES_3" }, - { R200_PP_TXMULTI_CTL_3, "R200_PP_TXMULTI_CTL_3" }, - { R200_PP_TXFILTER_4, "R200_PP_TXFILTER_4" }, - { R200_PP_TXFORMAT_4, "R200_PP_TXFORMAT_4" }, - { R200_PP_TXSIZE_4, "R200_PP_TXSIZE_4" }, - { R200_PP_TXFORMAT_X_4, "R200_PP_TXFORMAT_X_4" }, - { R200_PP_TXPITCH_4, "R200_PP_TXPITCH_4" }, - { R200_PP_BORDER_COLOR_4, "R200_PP_BORDER_COLOR_4" }, - { R200_PP_CUBIC_FACES_4, "R200_PP_CUBIC_FACES_4" }, - { R200_PP_TXMULTI_CTL_4, "R200_PP_TXMULTI_CTL_4" }, - { R200_PP_TXFILTER_5, "R200_PP_TXFILTER_5" }, - { R200_PP_TXFORMAT_5, "R200_PP_TXFORMAT_5" }, - { R200_PP_TXSIZE_5, "R200_PP_TXSIZE_5" }, - { R200_PP_TXFORMAT_X_5, "R200_PP_TXFORMAT_X_5" }, - { R200_PP_TXPITCH_5, "R200_PP_TXPITCH_5" }, - { R200_PP_BORDER_COLOR_5, "R200_PP_BORDER_COLOR_5" }, - { R200_PP_CUBIC_FACES_5, "R200_PP_CUBIC_FACES_5" }, - { R200_PP_TXMULTI_CTL_5, "R200_PP_TXMULTI_CTL_5" }, - { R200_PP_TXOFFSET_0, "R200_PP_TXOFFSET_0" }, - { R200_PP_CUBIC_OFFSET_F1_0, "R200_PP_CUBIC_OFFSET_F1_0" }, - { R200_PP_CUBIC_OFFSET_F2_0, "R200_PP_CUBIC_OFFSET_F2_0" }, - { R200_PP_CUBIC_OFFSET_F3_0, "R200_PP_CUBIC_OFFSET_F3_0" }, - { R200_PP_CUBIC_OFFSET_F4_0, "R200_PP_CUBIC_OFFSET_F4_0" }, - { R200_PP_CUBIC_OFFSET_F5_0, "R200_PP_CUBIC_OFFSET_F5_0" }, - { R200_PP_TXOFFSET_1, "R200_PP_TXOFFSET_1" }, - { R200_PP_CUBIC_OFFSET_F1_1, "R200_PP_CUBIC_OFFSET_F1_1" }, - { R200_PP_CUBIC_OFFSET_F2_1, "R200_PP_CUBIC_OFFSET_F2_1" }, - { R200_PP_CUBIC_OFFSET_F3_1, "R200_PP_CUBIC_OFFSET_F3_1" }, - { R200_PP_CUBIC_OFFSET_F4_1, "R200_PP_CUBIC_OFFSET_F4_1" }, - { R200_PP_CUBIC_OFFSET_F5_1, "R200_PP_CUBIC_OFFSET_F5_1" }, - { R200_PP_TXOFFSET_2, "R200_PP_TXOFFSET_2" }, - { R200_PP_CUBIC_OFFSET_F1_2, "R200_PP_CUBIC_OFFSET_F1_2" }, - { R200_PP_CUBIC_OFFSET_F2_2, "R200_PP_CUBIC_OFFSET_F2_2" }, - { R200_PP_CUBIC_OFFSET_F3_2, "R200_PP_CUBIC_OFFSET_F3_2" }, - { R200_PP_CUBIC_OFFSET_F4_2, "R200_PP_CUBIC_OFFSET_F4_2" }, - { R200_PP_CUBIC_OFFSET_F5_2, "R200_PP_CUBIC_OFFSET_F5_2" }, - { R200_PP_TXOFFSET_3, "R200_PP_TXOFFSET_3" }, - { R200_PP_CUBIC_OFFSET_F1_3, "R200_PP_CUBIC_OFFSET_F1_3" }, - { R200_PP_CUBIC_OFFSET_F2_3, "R200_PP_CUBIC_OFFSET_F2_3" }, - { R200_PP_CUBIC_OFFSET_F3_3, "R200_PP_CUBIC_OFFSET_F3_3" }, - { R200_PP_CUBIC_OFFSET_F4_3, "R200_PP_CUBIC_OFFSET_F4_3" }, - { R200_PP_CUBIC_OFFSET_F5_3, "R200_PP_CUBIC_OFFSET_F5_3" }, - { R200_PP_TXOFFSET_4, "R200_PP_TXOFFSET_4" }, - { R200_PP_CUBIC_OFFSET_F1_4, "R200_PP_CUBIC_OFFSET_F1_4" }, - { R200_PP_CUBIC_OFFSET_F2_4, "R200_PP_CUBIC_OFFSET_F2_4" }, - { R200_PP_CUBIC_OFFSET_F3_4, "R200_PP_CUBIC_OFFSET_F3_4" }, - { R200_PP_CUBIC_OFFSET_F4_4, "R200_PP_CUBIC_OFFSET_F4_4" }, - { R200_PP_CUBIC_OFFSET_F5_4, "R200_PP_CUBIC_OFFSET_F5_4" }, - { R200_PP_TXOFFSET_5, "R200_PP_TXOFFSET_5" }, - { R200_PP_CUBIC_OFFSET_F1_5, "R200_PP_CUBIC_OFFSET_F1_5" }, - { R200_PP_CUBIC_OFFSET_F2_5, "R200_PP_CUBIC_OFFSET_F2_5" }, - { R200_PP_CUBIC_OFFSET_F3_5, "R200_PP_CUBIC_OFFSET_F3_5" }, - { R200_PP_CUBIC_OFFSET_F4_5, "R200_PP_CUBIC_OFFSET_F4_5" }, - { R200_PP_CUBIC_OFFSET_F5_5, "R200_PP_CUBIC_OFFSET_F5_5" }, - { R200_PP_TAM_DEBUG3, "R200_PP_TAM_DEBUG3" }, - { R200_PP_TFACTOR_0, "R200_PP_TFACTOR_0" }, - { R200_PP_TFACTOR_1, "R200_PP_TFACTOR_1" }, - { R200_PP_TFACTOR_2, "R200_PP_TFACTOR_2" }, - { R200_PP_TFACTOR_3, "R200_PP_TFACTOR_3" }, - { R200_PP_TFACTOR_4, "R200_PP_TFACTOR_4" }, - { R200_PP_TFACTOR_5, "R200_PP_TFACTOR_5" }, - { R200_PP_TFACTOR_6, "R200_PP_TFACTOR_6" }, - { R200_PP_TFACTOR_7, "R200_PP_TFACTOR_7" }, - { R200_PP_TXCBLEND_0, "R200_PP_TXCBLEND_0" }, - { R200_PP_TXCBLEND2_0, "R200_PP_TXCBLEND2_0" }, - { R200_PP_TXABLEND_0, "R200_PP_TXABLEND_0" }, - { R200_PP_TXABLEND2_0, "R200_PP_TXABLEND2_0" }, - { R200_PP_TXCBLEND_1, "R200_PP_TXCBLEND_1" }, - { R200_PP_TXCBLEND2_1, "R200_PP_TXCBLEND2_1" }, - { R200_PP_TXABLEND_1, "R200_PP_TXABLEND_1" }, - { R200_PP_TXABLEND2_1, "R200_PP_TXABLEND2_1" }, - { R200_PP_TXCBLEND_2, "R200_PP_TXCBLEND_2" }, - { R200_PP_TXCBLEND2_2, "R200_PP_TXCBLEND2_2" }, - { R200_PP_TXABLEND_2, "R200_PP_TXABLEND_2" }, - { R200_PP_TXABLEND2_2, "R200_PP_TXABLEND2_2" }, - { R200_PP_TXCBLEND_3, "R200_PP_TXCBLEND_3" }, - { R200_PP_TXCBLEND2_3, "R200_PP_TXCBLEND2_3" }, - { R200_PP_TXABLEND_3, "R200_PP_TXABLEND_3" }, - { R200_PP_TXABLEND2_3, "R200_PP_TXABLEND2_3" }, - { R200_PP_TXCBLEND_4, "R200_PP_TXCBLEND_4" }, - { R200_PP_TXCBLEND2_4, "R200_PP_TXCBLEND2_4" }, - { R200_PP_TXABLEND_4, "R200_PP_TXABLEND_4" }, - { R200_PP_TXABLEND2_4, "R200_PP_TXABLEND2_4" }, - { R200_PP_TXCBLEND_5, "R200_PP_TXCBLEND_5" }, - { R200_PP_TXCBLEND2_5, "R200_PP_TXCBLEND2_5" }, - { R200_PP_TXABLEND_5, "R200_PP_TXABLEND_5" }, - { R200_PP_TXABLEND2_5, "R200_PP_TXABLEND2_5" }, - { R200_PP_TXCBLEND_6, "R200_PP_TXCBLEND_6" }, - { R200_PP_TXCBLEND2_6, "R200_PP_TXCBLEND2_6" }, - { R200_PP_TXABLEND_6, "R200_PP_TXABLEND_6" }, - { R200_PP_TXABLEND2_6, "R200_PP_TXABLEND2_6" }, - { R200_PP_TXCBLEND_7, "R200_PP_TXCBLEND_7" }, - { R200_PP_TXCBLEND2_7, "R200_PP_TXCBLEND2_7" }, - { R200_PP_TXABLEND_7, "R200_PP_TXABLEND_7" }, - { R200_PP_TXABLEND2_7, "R200_PP_TXABLEND2_7" }, - { R200_RB3D_BLENDCOLOR, "R200_RB3D_BLENDCOLOR" }, - { R200_RB3D_ABLENDCNTL, "R200_RB3D_ABLENDCNTL" }, - { R200_RB3D_CBLENDCNTL, "R200_RB3D_CBLENDCNTL" }, - { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" }, - { R200_PP_CNTL_X, "R200_PP_CNTL_X" }, - { R200_SE_VAP_CNTL_STATUS, "R200_SE_VAP_CNTL_STATUS" }, - { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" }, - { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_1" }, - { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_2" }, - { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3" }, - { R200_PP_TRI_PERF, "R200_PP_TRI_PERF" }, - { R200_PP_PERF_CNTL, "R200_PP_PERF_CNTL" }, - { R200_PP_TXCBLEND_8, "R200_PP_TXCBLEND_8" }, - { R200_PP_TXCBLEND2_8, "R200_PP_TXCBLEND2_8" }, - { R200_PP_TXABLEND_8, "R200_PP_TXABLEND_8" }, - { R200_PP_TXABLEND2_8, "R200_PP_TXABLEND2_8" }, - { R200_PP_TXCBLEND_9, "R200_PP_TXCBLEND_9" }, - { R200_PP_TXCBLEND2_9, "R200_PP_TXCBLEND2_9" }, - { R200_PP_TXABLEND_9, "R200_PP_TXABLEND_9" }, - { R200_PP_TXABLEND2_9, "R200_PP_TXABLEND2_9" }, - { R200_PP_TXCBLEND_10, "R200_PP_TXCBLEND_10" }, - { R200_PP_TXCBLEND2_10, "R200_PP_TXCBLEND2_10" }, - { R200_PP_TXABLEND_10, "R200_PP_TXABLEND_10" }, - { R200_PP_TXABLEND2_10, "R200_PP_TXABLEND2_10" }, - { R200_PP_TXCBLEND_11, "R200_PP_TXCBLEND_11" }, - { R200_PP_TXCBLEND2_11, "R200_PP_TXCBLEND2_11" }, - { R200_PP_TXABLEND_11, "R200_PP_TXABLEND_11" }, - { R200_PP_TXABLEND2_11, "R200_PP_TXABLEND2_11" }, - { R200_PP_TXCBLEND_12, "R200_PP_TXCBLEND_12" }, - { R200_PP_TXCBLEND2_12, "R200_PP_TXCBLEND2_12" }, - { R200_PP_TXABLEND_12, "R200_PP_TXABLEND_12" }, - { R200_PP_TXABLEND2_12, "R200_PP_TXABLEND2_12" }, - { R200_PP_TXCBLEND_13, "R200_PP_TXCBLEND_13" }, - { R200_PP_TXCBLEND2_13, "R200_PP_TXCBLEND2_13" }, - { R200_PP_TXABLEND_13, "R200_PP_TXABLEND_13" }, - { R200_PP_TXABLEND2_13, "R200_PP_TXABLEND2_13" }, - { R200_PP_TXCBLEND_14, "R200_PP_TXCBLEND_14" }, - { R200_PP_TXCBLEND2_14, "R200_PP_TXCBLEND2_14" }, - { R200_PP_TXABLEND_14, "R200_PP_TXABLEND_14" }, - { R200_PP_TXABLEND2_14, "R200_PP_TXABLEND2_14" }, - { R200_PP_TXCBLEND_15, "R200_PP_TXCBLEND_15" }, - { R200_PP_TXCBLEND2_15, "R200_PP_TXCBLEND2_15" }, - { R200_PP_TXABLEND_15, "R200_PP_TXABLEND_15" }, - { R200_PP_TXABLEND2_15, "R200_PP_TXABLEND2_15" }, - { R200_VAP_PVS_CNTL_1, "R200_VAP_PVS_CNTL_1" }, - { R200_VAP_PVS_CNTL_2, "R200_VAP_PVS_CNTL_2" }, -}; - -static struct reg_names scalar_names[] = { - { R200_SS_LIGHT_DCD_ADDR, "R200_SS_LIGHT_DCD_ADDR" }, - { R200_SS_LIGHT_DCM_ADDR, "R200_SS_LIGHT_DCM_ADDR" }, - { R200_SS_LIGHT_SPOT_EXPONENT_ADDR, "R200_SS_LIGHT_SPOT_EXPONENT_ADDR" }, - { R200_SS_LIGHT_SPOT_CUTOFF_ADDR, "R200_SS_LIGHT_SPOT_CUTOFF_ADDR" }, - { R200_SS_LIGHT_SPECULAR_THRESH_ADDR, "R200_SS_LIGHT_SPECULAR_THRESH_ADDR" }, - { R200_SS_LIGHT_RANGE_CUTOFF_SQRD, "R200_SS_LIGHT_RANGE_CUTOFF_SQRD" }, - { R200_SS_LIGHT_RANGE_ATT_CONST, "R200_SS_LIGHT_RANGE_ATT_CONST" }, - { R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, "R200_SS_VERT_GUARD_CLIP_ADJ_ADDR" }, - { R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR, "R200_SS_VERT_GUARD_DISCARD_ADJ_ADDR" }, - { R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR, "R200_SS_HORZ_GUARD_CLIP_ADJ_ADDR" }, - { R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR, "R200_SS_HORZ_GUARD_DISCARD_ADJ_ADDR" }, - { R200_SS_MAT_0_SHININESS, "R200_SS_MAT_0_SHININESS" }, - { R200_SS_MAT_1_SHININESS, "R200_SS_MAT_1_SHININESS" }, - { 1000, "" }, -}; - -/* Puff these out to make them look like normal (dword) registers. - */ -static struct reg_names vector_names[] = { - { 0, "start" }, - { R200_VS_LIGHT_AMBIENT_ADDR, "R200_VS_LIGHT_AMBIENT_ADDR" }, - { R200_VS_LIGHT_DIFFUSE_ADDR, "R200_VS_LIGHT_DIFFUSE_ADDR" }, - { R200_VS_LIGHT_SPECULAR_ADDR, "R200_VS_LIGHT_SPECULAR_ADDR" }, - { R200_VS_LIGHT_DIRPOS_ADDR, "R200_VS_LIGHT_DIRPOS_ADDR" }, - { R200_VS_LIGHT_HWVSPOT_ADDR, "R200_VS_LIGHT_HWVSPOT_ADDR" }, - { R200_VS_LIGHT_ATTENUATION_ADDR, "R200_VS_LIGHT_ATTENUATION_ADDR" }, - { R200_VS_SPOT_DUAL_CONE, "R200_VS_SPOT_DUAL_CONE" }, - { R200_VS_GLOBAL_AMBIENT_ADDR, "R200_VS_GLOBAL_AMBIENT_ADDR" }, - { R200_VS_FOG_PARAM_ADDR, "R200_VS_FOG_PARAM_ADDR" }, - { R200_VS_EYE_VECTOR_ADDR, "R200_VS_EYE_VECTOR_ADDR" }, - { R200_VS_UCP_ADDR, "R200_VS_UCP_ADDR" }, - { R200_VS_PNT_SPRITE_VPORT_SCALE, "R200_VS_PNT_SPRITE_VPORT_SCALE" }, - { R200_VS_MATRIX_0_MV, "R200_VS_MATRIX_0_MV" }, - { R200_VS_MATRIX_1_INV_MV, "R200_VS_MATRIX_1_INV_MV" }, - { R200_VS_MATRIX_2_MVP, "R200_VS_MATRIX_2_MVP" }, - { R200_VS_MATRIX_3_TEX0, "R200_VS_MATRIX_3_TEX0" }, - { R200_VS_MATRIX_4_TEX1, "R200_VS_MATRIX_4_TEX1" }, - { R200_VS_MATRIX_5_TEX2, "R200_VS_MATRIX_5_TEX2" }, - { R200_VS_MATRIX_6_TEX3, "R200_VS_MATRIX_6_TEX3" }, - { R200_VS_MATRIX_7_TEX4, "R200_VS_MATRIX_7_TEX4" }, - { R200_VS_MATRIX_8_TEX5, "R200_VS_MATRIX_8_TEX5" }, - { R200_VS_MAT_0_EMISS, "R200_VS_MAT_0_EMISS" }, - { R200_VS_MAT_0_AMB, "R200_VS_MAT_0_AMB" }, - { R200_VS_MAT_0_DIF, "R200_VS_MAT_0_DIF" }, - { R200_VS_MAT_0_SPEC, "R200_VS_MAT_0_SPEC" }, - { R200_VS_MAT_1_EMISS, "R200_VS_MAT_1_EMISS" }, - { R200_VS_MAT_1_AMB, "R200_VS_MAT_1_AMB" }, - { R200_VS_MAT_1_DIF, "R200_VS_MAT_1_DIF" }, - { R200_VS_MAT_1_SPEC, "R200_VS_MAT_1_SPEC" }, - { R200_VS_EYE2CLIP_MTX, "R200_VS_EYE2CLIP_MTX" }, - { R200_VS_PNT_SPRITE_ATT_CONST, "R200_VS_PNT_SPRITE_ATT_CONST" }, - { R200_VS_PNT_SPRITE_EYE_IN_MODEL, "R200_VS_PNT_SPRITE_EYE_IN_MODEL" }, - { R200_VS_PNT_SPRITE_CLAMP, "R200_VS_PNT_SPRITE_CLAMP" }, - { R200_VS_MAX, "R200_VS_MAX" }, - { 1000, "" }, -}; - -#define ISVEC 1 -#define ISFLOAT 2 -#define TOUCHED 4 - -struct reg { - int idx; - struct reg_names *closest; - int flags; - union fi current; - union fi *values; - int nvalues; - int nalloc; - float vmin, vmax; -}; - - -static struct reg regs[ARRAY_SIZE(reg_names)+1]; -static struct reg scalars[512+1]; -static struct reg vectors[512*4+1]; - -static int total, total_changed, bufs; - -static void init_regs( void ) -{ - struct reg_names *tmp; - int i; - - for (i = 0 ; i < ARRAY_SIZE(reg_names) ; i++) { - regs[i].idx = reg_names[i].idx; - regs[i].closest = ®_names[i]; - regs[i].flags = 0; - } - - for (i = 0, tmp = scalar_names ; i < ARRAY_SIZE(scalars) ; i++) { - if (tmp[1].idx == i) tmp++; - scalars[i].idx = i; - scalars[i].closest = tmp; - scalars[i].flags = ISFLOAT; - } - - for (i = 0, tmp = vector_names ; i < ARRAY_SIZE(vectors) ; i++) { - if (tmp[1].idx*4 == i) tmp++; - vectors[i].idx = i; - vectors[i].closest = tmp; - vectors[i].flags = ISFLOAT|ISVEC; - } - - regs[ARRAY_SIZE(regs)-1].idx = -1; - scalars[ARRAY_SIZE(scalars)-1].idx = -1; - vectors[ARRAY_SIZE(vectors)-1].idx = -1; -} - -static int find_or_add_value( struct reg *reg, int val ) -{ - int j; - - for ( j = 0 ; j < reg->nvalues ; j++) - if ( val == reg->values[j].i ) - return 1; - - if (j == reg->nalloc) { - reg->nalloc += 5; - reg->nalloc *= 2; - reg->values = realloc( reg->values, reg->nalloc * sizeof(union fi) ); - } - - reg->values[reg->nvalues++].i = val; - return 0; -} - -static struct reg *lookup_reg( struct reg *tab, int reg ) -{ - int i; - - for (i = 0 ; tab[i].idx != -1 ; i++) { - if (tab[i].idx == reg) - return &tab[i]; - } - - fprintf(stderr, "*** unknown reg 0x%x\n", reg); - return NULL; -} - - -static const char *get_reg_name( struct reg *reg ) -{ - static char tmp[80]; - - if (reg->idx == reg->closest->idx) - return reg->closest->name; - - - if (reg->flags & ISVEC) { - if (reg->idx/4 != reg->closest->idx) - sprintf(tmp, "%s+%d[%d]", - reg->closest->name, - (reg->idx/4) - reg->closest->idx, - reg->idx%4); - else - sprintf(tmp, "%s[%d]", reg->closest->name, reg->idx%4); - } - else { - if (reg->idx != reg->closest->idx) - sprintf(tmp, "%s+%d", reg->closest->name, reg->idx - reg->closest->idx); - else - sprintf(tmp, "%s", reg->closest->name); - } - - return tmp; -} - -static int print_int_reg_assignment( struct reg *reg, int data ) -{ - int changed = (reg->current.i != data); - int ever_seen = find_or_add_value( reg, data ); - - if (VERBOSE || (NORMAL && (changed || !ever_seen))) - fprintf(stderr, " %s <-- 0x%x", get_reg_name(reg), data); - - if (NORMAL) { - if (!ever_seen) - fprintf(stderr, " *** BRAND NEW VALUE"); - else if (changed) - fprintf(stderr, " *** CHANGED"); - } - - reg->current.i = data; - - if (VERBOSE || (NORMAL && (changed || !ever_seen))) - fprintf(stderr, "\n"); - - return changed; -} - - -static int print_float_reg_assignment( struct reg *reg, float data ) -{ - int changed = (reg->current.f != data); - int newmin = (data < reg->vmin); - int newmax = (data > reg->vmax); - - if (VERBOSE || (NORMAL && (newmin || newmax || changed))) - fprintf(stderr, " %s <-- %.3f", get_reg_name(reg), data); - - if (NORMAL) { - if (newmin) { - fprintf(stderr, " *** NEW MIN (prev %.3f)", reg->vmin); - reg->vmin = data; - } - else if (newmax) { - fprintf(stderr, " *** NEW MAX (prev %.3f)", reg->vmax); - reg->vmax = data; - } - else if (changed) { - fprintf(stderr, " *** CHANGED"); - } - } - - reg->current.f = data; - - if (VERBOSE || (NORMAL && (newmin || newmax || changed))) - fprintf(stderr, "\n"); - - return changed; -} - -static int print_reg_assignment( struct reg *reg, int data ) -{ - float_ui32_type datau; - datau.ui32 = data; - reg->flags |= TOUCHED; - if (reg->flags & ISFLOAT) - return print_float_reg_assignment( reg, datau.f ); - else - return print_int_reg_assignment( reg, data ); -} - -static void print_reg( struct reg *reg ) -{ - if (reg->flags & TOUCHED) { - if (reg->flags & ISFLOAT) { - fprintf(stderr, " %s == %f\n", get_reg_name(reg), reg->current.f); - } else { - fprintf(stderr, " %s == 0x%x\n", get_reg_name(reg), reg->current.i); - } - } -} - - -static void dump_state( void ) -{ - int i; - - for (i = 0 ; i < ARRAY_SIZE(regs) ; i++) - print_reg( ®s[i] ); - - for (i = 0 ; i < ARRAY_SIZE(scalars) ; i++) - print_reg( &scalars[i] ); - - for (i = 0 ; i < ARRAY_SIZE(vectors) ; i++) - print_reg( &vectors[i] ); -} - - - -static int radeon_emit_packets( - drm_radeon_cmd_header_t header, - drm_radeon_cmd_buffer_t *cmdbuf ) -{ - int id = (int)header.packet.packet_id; - int sz = packet[id].len; - int *data = (int *)cmdbuf->buf; - int i; - - if (sz * sizeof(int) > cmdbuf->bufsz) { - fprintf(stderr, "Packet overflows cmdbuf\n"); - return -EINVAL; - } - - if (!packet[id].name) { - fprintf(stderr, "*** Unknown packet 0 nr %d\n", id ); - return -EINVAL; - } - - - if (VERBOSE) - fprintf(stderr, "Packet 0 reg %s nr %d\n", packet[id].name, sz ); - - for ( i = 0 ; i < sz ; i++) { - struct reg *reg = lookup_reg( regs, packet[id].start + i*4 ); - if (print_reg_assignment( reg, data[i] )) - total_changed++; - total++; - } - - cmdbuf->buf += sz * sizeof(int); - cmdbuf->bufsz -= sz * sizeof(int); - return 0; -} - - -static int radeon_emit_scalars( - drm_radeon_cmd_header_t header, - drm_radeon_cmd_buffer_t *cmdbuf ) -{ - int sz = header.scalars.count; - int *data = (int *)cmdbuf->buf; - int start = header.scalars.offset; - int stride = header.scalars.stride; - int i; - - if (VERBOSE) - fprintf(stderr, "emit scalars, start %d stride %d nr %d (end %d)\n", - start, stride, sz, start + stride * sz); - - - for (i = 0 ; i < sz ; i++, start += stride) { - struct reg *reg = lookup_reg( scalars, start ); - if (print_reg_assignment( reg, data[i] )) - total_changed++; - total++; - } - - cmdbuf->buf += sz * sizeof(int); - cmdbuf->bufsz -= sz * sizeof(int); - return 0; -} - - -static int radeon_emit_scalars2( - drm_radeon_cmd_header_t header, - drm_radeon_cmd_buffer_t *cmdbuf ) -{ - int sz = header.scalars.count; - int *data = (int *)cmdbuf->buf; - int start = header.scalars.offset + 0x100; - int stride = header.scalars.stride; - int i; - - if (VERBOSE) - fprintf(stderr, "emit scalars2, start %d stride %d nr %d (end %d)\n", - start, stride, sz, start + stride * sz); - - if (start + stride * sz > 258) { - fprintf(stderr, "emit scalars OVERFLOW %d/%d/%d\n", start, stride, sz); - return -1; - } - - for (i = 0 ; i < sz ; i++, start += stride) { - struct reg *reg = lookup_reg( scalars, start ); - if (print_reg_assignment( reg, data[i] )) - total_changed++; - total++; - } - - cmdbuf->buf += sz * sizeof(int); - cmdbuf->bufsz -= sz * sizeof(int); - return 0; -} - -/* Check: inf/nan/extreme-size? - * Check: table start, end, nr, etc. - */ -static int radeon_emit_vectors( - drm_radeon_cmd_header_t header, - drm_radeon_cmd_buffer_t *cmdbuf ) -{ - int sz = header.vectors.count; - int *data = (int *)cmdbuf->buf; - int start = header.vectors.offset; - int stride = header.vectors.stride; - int i,j; - - if (VERBOSE) - fprintf(stderr, "emit vectors, start %d stride %d nr %d (end %d) (0x%x)\n", - start, stride, sz, start + stride * sz, header.i); - -/* if (start + stride * (sz/4) > 128) { */ -/* fprintf(stderr, "emit vectors OVERFLOW %d/%d/%d\n", start, stride, sz); */ -/* return -1; */ -/* } */ - - for (i = 0 ; i < sz ; start += stride) { - int changed = 0; - for (j = 0 ; j < 4 ; i++,j++) { - struct reg *reg = lookup_reg( vectors, start*4+j ); - if (print_reg_assignment( reg, data[i] )) - changed = 1; - } - if (changed) - total_changed += 4; - total += 4; - } - - - cmdbuf->buf += sz * sizeof(int); - cmdbuf->bufsz -= sz * sizeof(int); - return 0; -} - -static int radeon_emit_veclinear( - drm_radeon_cmd_header_t header, - drm_radeon_cmd_buffer_t *cmdbuf ) -{ - int sz = header.veclinear.count * 4; - int *data = (int *)cmdbuf->buf; - float *fdata =(float *)cmdbuf->buf; - int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8); - int i; - - if (1||VERBOSE) - fprintf(stderr, "emit vectors linear, start %d nr %d (end %d) (0x%x)\n", - start, sz >> 2, start + (sz >> 2), header.i); - - - if (start < 0x60) { - for (i = 0 ; i < sz ; i += 4) { - fprintf(stderr, "R200_VS_PARAM %d 0 %f\n", (i >> 2) + start, fdata[i]); - fprintf(stderr, "R200_VS_PARAM %d 1 %f\n", (i >> 2) + start, fdata[i+1]); - fprintf(stderr, "R200_VS_PARAM %d 2 %f\n", (i >> 2) + start, fdata[i+2]); - fprintf(stderr, "R200_VS_PARAM %d 3 %f\n", (i >> 2) + start, fdata[i+3]); - } - } - else if ((start >= 0x100) && (start < 0x160)) { - for (i = 0 ; i < sz ; i += 4) { - fprintf(stderr, "R200_VS_PARAM %d 0 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i]); - fprintf(stderr, "R200_VS_PARAM %d 1 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i+1]); - fprintf(stderr, "R200_VS_PARAM %d 2 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i+2]); - fprintf(stderr, "R200_VS_PARAM %d 3 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i+3]); - } - } - else if ((start >= 0x80) && (start < 0xc0)) { - for (i = 0 ; i < sz ; i += 4) { - fprintf(stderr, "R200_VS_PROG %d OPDST %08x\n", (i >> 2) + start - 0x80, data[i]); - fprintf(stderr, "R200_VS_PROG %d SRC1 %08x\n", (i >> 2) + start - 0x80, data[i+1]); - fprintf(stderr, "R200_VS_PROG %d SRC2 %08x\n", (i >> 2) + start - 0x80, data[i+2]); - fprintf(stderr, "R200_VS_PROG %d SRC3 %08x\n", (i >> 2) + start - 0x80, data[i+3]); - } - } - else if ((start >= 0x180) && (start < 0x1c0)) { - for (i = 0 ; i < sz ; i += 4) { - fprintf(stderr, "R200_VS_PROG %d OPDST %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i]); - fprintf(stderr, "R200_VS_PROG %d SRC1 %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i+1]); - fprintf(stderr, "R200_VS_PROG %d SRC2 %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i+2]); - fprintf(stderr, "R200_VS_PROG %d SRC3 %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i+3]); - } - } - else { - fprintf(stderr, "write to unknown vector area\n"); - } - - cmdbuf->buf += sz * sizeof(int); - cmdbuf->bufsz -= sz * sizeof(int); - return 0; -} - -#if 0 -static int print_vertex_format( int vfmt ) -{ - if (NORMAL) { - fprintf(stderr, " %s(%x): %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", - "vertex format", - vfmt, - "xy,", - (vfmt & R200_VTX_Z0) ? "z," : "", - (vfmt & R200_VTX_W0) ? "w0," : "", - (vfmt & R200_VTX_FPCOLOR) ? "fpcolor," : "", - (vfmt & R200_VTX_FPALPHA) ? "fpalpha," : "", - (vfmt & R200_VTX_PKCOLOR) ? "pkcolor," : "", - (vfmt & R200_VTX_FPSPEC) ? "fpspec," : "", - (vfmt & R200_VTX_FPFOG) ? "fpfog," : "", - (vfmt & R200_VTX_PKSPEC) ? "pkspec," : "", - (vfmt & R200_VTX_ST0) ? "st0," : "", - (vfmt & R200_VTX_ST1) ? "st1," : "", - (vfmt & R200_VTX_Q1) ? "q1," : "", - (vfmt & R200_VTX_ST2) ? "st2," : "", - (vfmt & R200_VTX_Q2) ? "q2," : "", - (vfmt & R200_VTX_ST3) ? "st3," : "", - (vfmt & R200_VTX_Q3) ? "q3," : "", - (vfmt & R200_VTX_Q0) ? "q0," : "", - (vfmt & R200_VTX_N0) ? "n0," : "", - (vfmt & R200_VTX_XY1) ? "xy1," : "", - (vfmt & R200_VTX_Z1) ? "z1," : "", - (vfmt & R200_VTX_W1) ? "w1," : "", - (vfmt & R200_VTX_N1) ? "n1," : ""); - - - if (!find_or_add_value( &others[V_VTXFMT], vfmt )) - fprintf(stderr, " *** NEW VALUE"); - - fprintf(stderr, "\n"); - } - - return 0; -} -#endif - -static char *primname[0x10] = { - "NONE", - "POINTS", - "LINES", - "LINE_STRIP", - "TRIANGLES", - "TRIANGLE_FAN", - "TRIANGLE_STRIP", - "RECT_LIST", - NULL, - "3VRT_POINTS", - "3VRT_LINES", - "POINT_SPRITES", - "LINE_LOOP", - "QUADS", - "QUAD_STRIP", - "POLYGON", -}; - -static int print_prim_and_flags( int prim ) -{ - int numverts; - - if (NORMAL) - fprintf(stderr, " %s(%x): %s%s%s%s%s%s\n", - "prim flags", - prim, - ((prim & 0x30) == R200_VF_PRIM_WALK_IND) ? "IND," : "", - ((prim & 0x30) == R200_VF_PRIM_WALK_LIST) ? "LIST," : "", - ((prim & 0x30) == R200_VF_PRIM_WALK_RING) ? "RING," : "", - (prim & R200_VF_COLOR_ORDER_RGBA) ? "RGBA," : "BGRA, ", - (prim & R200_VF_INDEX_SZ_4) ? "INDX-32," : "", - (prim & R200_VF_TCL_OUTPUT_VTX_ENABLE) ? "TCL_OUT_VTX," : ""); - - numverts = prim>>16; - - if (NORMAL) - fprintf(stderr, " prim: %s numverts %d\n", primname[prim&0xf], numverts); - - switch (prim & 0xf) { - case R200_VF_PRIM_NONE: - case R200_VF_PRIM_POINTS: - if (numverts < 1) { - fprintf(stderr, "Bad nr verts for line %d\n", numverts); - return -1; - } - break; - case R200_VF_PRIM_LINES: - case R200_VF_PRIM_POINT_SPRITES: - if ((numverts & 1) || numverts == 0) { - fprintf(stderr, "Bad nr verts for line %d\n", numverts); - return -1; - } - break; - case R200_VF_PRIM_LINE_STRIP: - case R200_VF_PRIM_LINE_LOOP: - if (numverts < 2) { - fprintf(stderr, "Bad nr verts for line_strip %d\n", numverts); - return -1; - } - break; - case R200_VF_PRIM_TRIANGLES: - case R200_VF_PRIM_3VRT_POINTS: - case R200_VF_PRIM_3VRT_LINES: - case R200_VF_PRIM_RECT_LIST: - if (numverts % 3 || numverts == 0) { - fprintf(stderr, "Bad nr verts for tri %d\n", numverts); - return -1; - } - break; - case R200_VF_PRIM_TRIANGLE_FAN: - case R200_VF_PRIM_TRIANGLE_STRIP: - case R200_VF_PRIM_POLYGON: - if (numverts < 3) { - fprintf(stderr, "Bad nr verts for strip/fan %d\n", numverts); - return -1; - } - break; - case R200_VF_PRIM_QUADS: - if (numverts % 4 || numverts == 0) { - fprintf(stderr, "Bad nr verts for quad %d\n", numverts); - return -1; - } - break; - case R200_VF_PRIM_QUAD_STRIP: - if (numverts % 2 || numverts < 4) { - fprintf(stderr, "Bad nr verts for quadstrip %d\n", numverts); - return -1; - } - break; - default: - fprintf(stderr, "Bad primitive\n"); - return -1; - } - return 0; -} - -/* build in knowledge about each packet type - */ -static int radeon_emit_packet3( drm_radeon_cmd_buffer_t *cmdbuf ) -{ - int cmdsz; - int *cmd = (int *)cmdbuf->buf; - int *tmp; - int i, stride, size, start; - - cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16); - - if ((cmd[0] & RADEON_CP_PACKET_MASK) != RADEON_CP_PACKET3 || - cmdsz * 4 > cmdbuf->bufsz || - cmdsz > RADEON_CP_PACKET_MAX_DWORDS) { - fprintf(stderr, "Bad packet\n"); - return -EINVAL; - } - - switch( cmd[0] & ~RADEON_CP_PACKET_COUNT_MASK ) { - case R200_CP_CMD_NOP: - if (NORMAL) - fprintf(stderr, "PACKET3_NOP, %d dwords\n", cmdsz); - break; - case R200_CP_CMD_NEXT_CHAR: - if (NORMAL) - fprintf(stderr, "PACKET3_NEXT_CHAR, %d dwords\n", cmdsz); - break; - case R200_CP_CMD_PLY_NEXTSCAN: - if (NORMAL) - fprintf(stderr, "PACKET3_PLY_NEXTSCAN, %d dwords\n", cmdsz); - break; - case R200_CP_CMD_SET_SCISSORS: - if (NORMAL) - fprintf(stderr, "PACKET3_SET_SCISSORS, %d dwords\n", cmdsz); - break; - case R200_CP_CMD_LOAD_MICROCODE: - if (NORMAL) - fprintf(stderr, "PACKET3_LOAD_MICROCODE, %d dwords\n", cmdsz); - break; - case R200_CP_CMD_WAIT_FOR_IDLE: - if (NORMAL) - fprintf(stderr, "PACKET3_WAIT_FOR_IDLE, %d dwords\n", cmdsz); - break; - - case R200_CP_CMD_3D_DRAW_VBUF: - if (NORMAL) - fprintf(stderr, "PACKET3_3D_DRAW_VBUF, %d dwords\n", cmdsz); -/* print_vertex_format(cmd[1]); */ - if (print_prim_and_flags(cmd[2])) - return -EINVAL; - break; - - case R200_CP_CMD_3D_DRAW_IMMD: - if (NORMAL) - fprintf(stderr, "PACKET3_3D_DRAW_IMMD, %d dwords\n", cmdsz); - break; - case R200_CP_CMD_3D_DRAW_INDX: { - int neltdwords; - if (NORMAL) - fprintf(stderr, "PACKET3_3D_DRAW_INDX, %d dwords\n", cmdsz); -/* print_vertex_format(cmd[1]); */ - if (print_prim_and_flags(cmd[2])) - return -EINVAL; - neltdwords = cmd[2]>>16; - neltdwords += neltdwords & 1; - neltdwords /= 2; - if (neltdwords + 3 != cmdsz) - fprintf(stderr, "Mismatch in DRAW_INDX, %d vs cmdsz %d\n", - neltdwords, cmdsz); - break; - } - case R200_CP_CMD_LOAD_PALETTE: - if (NORMAL) - fprintf(stderr, "PACKET3_LOAD_PALETTE, %d dwords\n", cmdsz); - break; - case R200_CP_CMD_3D_LOAD_VBPNTR: - if (NORMAL) { - fprintf(stderr, "PACKET3_3D_LOAD_VBPNTR, %d dwords\n", cmdsz); - fprintf(stderr, " nr arrays: %d\n", cmd[1]); - } - - if (((cmd[1]/2)*3) + ((cmd[1]%2)*2) != cmdsz - 2) { - fprintf(stderr, " ****** MISMATCH %d/%d *******\n", - ((cmd[1]/2)*3) + ((cmd[1]%2)*2) + 2, cmdsz); - return -EINVAL; - } - - if (NORMAL) { - tmp = cmd+2; - for (i = 0 ; i < cmd[1] ; i++) { - if (i & 1) { - stride = (tmp[0]>>24) & 0xff; - size = (tmp[0]>>16) & 0xff; - start = tmp[2]; - tmp += 3; - } - else { - stride = (tmp[0]>>8) & 0xff; - size = (tmp[0]) & 0xff; - start = tmp[1]; - } - fprintf(stderr, " array %d: start 0x%x vsize %d vstride %d\n", - i, start, size, stride ); - } - } - break; - case R200_CP_CMD_PAINT: - if (NORMAL) - fprintf(stderr, "PACKET3_CNTL_PAINT, %d dwords\n", cmdsz); - break; - case R200_CP_CMD_BITBLT: - if (NORMAL) - fprintf(stderr, "PACKET3_CNTL_BITBLT, %d dwords\n", cmdsz); - break; - case R200_CP_CMD_SMALLTEXT: - if (NORMAL) - fprintf(stderr, "PACKET3_CNTL_SMALLTEXT, %d dwords\n", cmdsz); - break; - case R200_CP_CMD_HOSTDATA_BLT: - if (NORMAL) - fprintf(stderr, "PACKET3_CNTL_HOSTDATA_BLT, %d dwords\n", - cmdsz); - break; - case R200_CP_CMD_POLYLINE: - if (NORMAL) - fprintf(stderr, "PACKET3_CNTL_POLYLINE, %d dwords\n", cmdsz); - break; - case R200_CP_CMD_POLYSCANLINES: - if (NORMAL) - fprintf(stderr, "PACKET3_CNTL_POLYSCANLINES, %d dwords\n", - cmdsz); - break; - case R200_CP_CMD_PAINT_MULTI: - if (NORMAL) - fprintf(stderr, "PACKET3_CNTL_PAINT_MULTI, %d dwords\n", - cmdsz); - break; - case R200_CP_CMD_BITBLT_MULTI: - if (NORMAL) - fprintf(stderr, "PACKET3_CNTL_BITBLT_MULTI, %d dwords\n", - cmdsz); - break; - case R200_CP_CMD_TRANS_BITBLT: - if (NORMAL) - fprintf(stderr, "PACKET3_CNTL_TRANS_BITBLT, %d dwords\n", - cmdsz); - break; - case R200_CP_CMD_3D_DRAW_VBUF_2: - if (NORMAL) - fprintf(stderr, "R200_CP_CMD_3D_DRAW_VBUF_2, %d dwords\n", - cmdsz); - if (print_prim_and_flags(cmd[1])) - return -EINVAL; - break; - case R200_CP_CMD_3D_DRAW_IMMD_2: - if (NORMAL) - fprintf(stderr, "R200_CP_CMD_3D_DRAW_IMMD_2, %d dwords\n", - cmdsz); - if (print_prim_and_flags(cmd[1])) - return -EINVAL; - break; - case R200_CP_CMD_3D_DRAW_INDX_2: - if (NORMAL) - fprintf(stderr, "R200_CP_CMD_3D_DRAW_INDX_2, %d dwords\n", - cmdsz); - if (print_prim_and_flags(cmd[1])) - return -EINVAL; - break; - default: - fprintf(stderr, "UNKNOWN PACKET, %d dwords\n", cmdsz); - break; - } - - cmdbuf->buf += cmdsz * 4; - cmdbuf->bufsz -= cmdsz * 4; - return 0; -} - - -/* Check cliprects for bounds, then pass on to above: - */ -static int radeon_emit_packet3_cliprect( drm_radeon_cmd_buffer_t *cmdbuf ) -{ - drm_clip_rect_t *boxes = (drm_clip_rect_t *)cmdbuf->boxes; - int i = 0; - - if (VERBOSE && total_changed) { - dump_state(); - total_changed = 0; - } - - if (NORMAL) { - do { - if ( i < cmdbuf->nbox ) { - fprintf(stderr, "Emit box %d/%d %d,%d %d,%d\n", - i, cmdbuf->nbox, - boxes[i].x1, boxes[i].y1, boxes[i].x2, boxes[i].y2); - } - } while ( ++i < cmdbuf->nbox ); - } - - if (cmdbuf->nbox == 1) - cmdbuf->nbox = 0; - - return radeon_emit_packet3( cmdbuf ); -} - - -int r200SanityCmdBuffer( r200ContextPtr rmesa, - int nbox, - drm_clip_rect_t *boxes ) -{ - int idx; - drm_radeon_cmd_buffer_t cmdbuf; - drm_radeon_cmd_header_t header; - static int inited = 0; - - if (!inited) { - init_regs(); - inited = 1; - } - - - cmdbuf.buf = rmesa->store.cmd_buf; - cmdbuf.bufsz = rmesa->store.cmd_used; - cmdbuf.boxes = (drm_clip_rect_t *)boxes; - cmdbuf.nbox = nbox; - - while ( cmdbuf.bufsz >= sizeof(header) ) { - - header.i = *(int *)cmdbuf.buf; - cmdbuf.buf += sizeof(header); - cmdbuf.bufsz -= sizeof(header); - - switch (header.header.cmd_type) { - case RADEON_CMD_PACKET: - if (radeon_emit_packets( header, &cmdbuf )) { - fprintf(stderr,"radeon_emit_packets failed\n"); - return -EINVAL; - } - break; - - case RADEON_CMD_SCALARS: - if (radeon_emit_scalars( header, &cmdbuf )) { - fprintf(stderr,"radeon_emit_scalars failed\n"); - return -EINVAL; - } - break; - - case RADEON_CMD_SCALARS2: - if (radeon_emit_scalars2( header, &cmdbuf )) { - fprintf(stderr,"radeon_emit_scalars failed\n"); - return -EINVAL; - } - break; - - case RADEON_CMD_VECTORS: - if (radeon_emit_vectors( header, &cmdbuf )) { - fprintf(stderr,"radeon_emit_vectors failed\n"); - return -EINVAL; - } - break; - - case RADEON_CMD_DMA_DISCARD: - idx = header.dma.buf_idx; - if (NORMAL) - fprintf(stderr, "RADEON_CMD_DMA_DISCARD buf %d\n", idx); - bufs++; - break; - - case RADEON_CMD_PACKET3: - if (radeon_emit_packet3( &cmdbuf )) { - fprintf(stderr,"radeon_emit_packet3 failed\n"); - return -EINVAL; - } - break; - - case RADEON_CMD_PACKET3_CLIP: - if (radeon_emit_packet3_cliprect( &cmdbuf )) { - fprintf(stderr,"radeon_emit_packet3_clip failed\n"); - return -EINVAL; - } - break; - - case RADEON_CMD_WAIT: - break; - - case RADEON_CMD_VECLINEAR: - if (radeon_emit_veclinear( header, &cmdbuf )) { - fprintf(stderr,"radeon_emit_veclinear failed\n"); - return -EINVAL; - } - break; - - default: - fprintf(stderr,"bad cmd_type %d at %p\n", - header.header.cmd_type, - cmdbuf.buf - sizeof(header)); - return -EINVAL; - } - } - - if (0) - { - static int n = 0; - n++; - if (n == 10) { - fprintf(stderr, "Bufs %d Total emitted %d real changes %d (%.2f%%)\n", - bufs, - total, total_changed, - ((float)total_changed/(float)total*100.0)); - fprintf(stderr, "Total emitted per buf: %.2f\n", - (float)total/(float)bufs); - fprintf(stderr, "Real changes per buf: %.2f\n", - (float)total_changed/(float)bufs); - - bufs = n = total = total_changed = 0; - } - } - - fprintf(stderr, "leaving %s\n\n\n", __func__); - - return 0; -} diff --git a/src/mesa/drivers/dri/r200/r200_sanity.h b/src/mesa/drivers/dri/r200/r200_sanity.h deleted file mode 100644 index f4c110dba6e..00000000000 --- a/src/mesa/drivers/dri/r200/r200_sanity.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef R200_SANITY_H -#define R200_SANITY_H - -extern int r200SanityCmdBuffer( r200ContextPtr rmesa, - int nbox, - drm_clip_rect_t *boxes ); - -#endif diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c deleted file mode 100644 index d843fa199a2..00000000000 --- a/src/mesa/drivers/dri/r200/r200_state.c +++ /dev/null @@ -1,2401 +0,0 @@ -/************************************************************************** - -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell <keithw@vmware.com> - */ - -#include "main/glheader.h" - -#include "main/enums.h" -#include "main/light.h" -#include "main/framebuffer.h" -#include "main/fbobject.h" -#include "main/state.h" -#include "main/stencil.h" -#include "main/viewport.h" - -#include "swrast/swrast.h" -#include "vbo/vbo.h" -#include "tnl/tnl.h" -#include "tnl/t_pipeline.h" -#include "swrast_setup/swrast_setup.h" -#include "drivers/common/meta.h" -#include "util/bitscan.h" - -#include "radeon_common.h" -#include "radeon_mipmap_tree.h" -#include "r200_context.h" -#include "r200_ioctl.h" -#include "r200_state.h" -#include "r200_tcl.h" -#include "r200_tex.h" -#include "r200_swtcl.h" -#include "r200_vertprog.h" - -#include "util/simple_list.h" - -/* ============================================================= - * Alpha blending - */ - -static void r200AlphaFunc( struct gl_context *ctx, GLenum func, GLfloat ref ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - int pp_misc = rmesa->hw.ctx.cmd[CTX_PP_MISC]; - GLubyte refByte; - - CLAMPED_FLOAT_TO_UBYTE(refByte, ref); - - R200_STATECHANGE( rmesa, ctx ); - - pp_misc &= ~(R200_ALPHA_TEST_OP_MASK | R200_REF_ALPHA_MASK); - pp_misc |= (refByte & R200_REF_ALPHA_MASK); - - switch ( func ) { - case GL_NEVER: - pp_misc |= R200_ALPHA_TEST_FAIL; - break; - case GL_LESS: - pp_misc |= R200_ALPHA_TEST_LESS; - break; - case GL_EQUAL: - pp_misc |= R200_ALPHA_TEST_EQUAL; - break; - case GL_LEQUAL: - pp_misc |= R200_ALPHA_TEST_LEQUAL; - break; - case GL_GREATER: - pp_misc |= R200_ALPHA_TEST_GREATER; - break; - case GL_NOTEQUAL: - pp_misc |= R200_ALPHA_TEST_NEQUAL; - break; - case GL_GEQUAL: - pp_misc |= R200_ALPHA_TEST_GEQUAL; - break; - case GL_ALWAYS: - pp_misc |= R200_ALPHA_TEST_PASS; - break; - } - - rmesa->hw.ctx.cmd[CTX_PP_MISC] = pp_misc; -} - -static void r200BlendColor( struct gl_context *ctx, const GLfloat cf[4] ) -{ - GLubyte color[4]; - r200ContextPtr rmesa = R200_CONTEXT(ctx); - R200_STATECHANGE( rmesa, ctx ); - CLAMPED_FLOAT_TO_UBYTE(color[0], cf[0]); - CLAMPED_FLOAT_TO_UBYTE(color[1], cf[1]); - CLAMPED_FLOAT_TO_UBYTE(color[2], cf[2]); - CLAMPED_FLOAT_TO_UBYTE(color[3], cf[3]); - rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = radeonPackColor( 4, color[0], color[1], color[2], color[3] ); -} - -/** - * Calculate the hardware blend factor setting. This same function is used - * for source and destination of both alpha and RGB. - * - * \returns - * The hardware register value for the specified blend factor. This value - * will need to be shifted into the correct position for either source or - * destination factor. - * - * \todo - * Since the two cases where source and destination are handled differently - * are essentially error cases, they should never happen. Determine if these - * cases can be removed. - */ -static int blend_factor( GLenum factor, GLboolean is_src ) -{ - int func; - - switch ( factor ) { - case GL_ZERO: - func = R200_BLEND_GL_ZERO; - break; - case GL_ONE: - func = R200_BLEND_GL_ONE; - break; - case GL_DST_COLOR: - func = R200_BLEND_GL_DST_COLOR; - break; - case GL_ONE_MINUS_DST_COLOR: - func = R200_BLEND_GL_ONE_MINUS_DST_COLOR; - break; - case GL_SRC_COLOR: - func = R200_BLEND_GL_SRC_COLOR; - break; - case GL_ONE_MINUS_SRC_COLOR: - func = R200_BLEND_GL_ONE_MINUS_SRC_COLOR; - break; - case GL_SRC_ALPHA: - func = R200_BLEND_GL_SRC_ALPHA; - break; - case GL_ONE_MINUS_SRC_ALPHA: - func = R200_BLEND_GL_ONE_MINUS_SRC_ALPHA; - break; - case GL_DST_ALPHA: - func = R200_BLEND_GL_DST_ALPHA; - break; - case GL_ONE_MINUS_DST_ALPHA: - func = R200_BLEND_GL_ONE_MINUS_DST_ALPHA; - break; - case GL_SRC_ALPHA_SATURATE: - func = (is_src) ? R200_BLEND_GL_SRC_ALPHA_SATURATE : R200_BLEND_GL_ZERO; - break; - case GL_CONSTANT_COLOR: - func = R200_BLEND_GL_CONST_COLOR; - break; - case GL_ONE_MINUS_CONSTANT_COLOR: - func = R200_BLEND_GL_ONE_MINUS_CONST_COLOR; - break; - case GL_CONSTANT_ALPHA: - func = R200_BLEND_GL_CONST_ALPHA; - break; - case GL_ONE_MINUS_CONSTANT_ALPHA: - func = R200_BLEND_GL_ONE_MINUS_CONST_ALPHA; - break; - default: - func = (is_src) ? R200_BLEND_GL_ONE : R200_BLEND_GL_ZERO; - } - return func; -} - -/** - * Sets both the blend equation and the blend function. - * This is done in a single - * function because some blend equations (i.e., \c GL_MIN and \c GL_MAX) - * change the interpretation of the blend function. - * Also, make sure that blend function and blend equation are set to their default - * value if color blending is not enabled, since at least blend equations GL_MIN - * and GL_FUNC_REVERSE_SUBTRACT will cause wrong results otherwise for - * unknown reasons. - */ -static void r200_set_blend_state( struct gl_context * ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint cntl = rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] & - ~(R200_ROP_ENABLE | R200_ALPHA_BLEND_ENABLE | R200_SEPARATE_ALPHA_ENABLE); - - int func = (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | - (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT); - int eqn = R200_COMB_FCN_ADD_CLAMP; - int funcA = (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | - (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT); - int eqnA = R200_COMB_FCN_ADD_CLAMP; - - R200_STATECHANGE( rmesa, ctx ); - - if (ctx->Color.ColorLogicOpEnabled) { - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ROP_ENABLE; - rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = eqn | func; - rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = eqn | func; - return; - } else if (ctx->Color.BlendEnabled) { - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl | R200_ALPHA_BLEND_ENABLE | R200_SEPARATE_ALPHA_ENABLE; - } - else { - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = cntl; - rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = eqn | func; - rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = eqn | func; - return; - } - - func = (blend_factor( ctx->Color.Blend[0].SrcRGB, GL_TRUE ) << R200_SRC_BLEND_SHIFT) | - (blend_factor( ctx->Color.Blend[0].DstRGB, GL_FALSE ) << R200_DST_BLEND_SHIFT); - - switch(ctx->Color.Blend[0].EquationRGB) { - case GL_FUNC_ADD: - eqn = R200_COMB_FCN_ADD_CLAMP; - break; - - case GL_FUNC_SUBTRACT: - eqn = R200_COMB_FCN_SUB_CLAMP; - break; - - case GL_FUNC_REVERSE_SUBTRACT: - eqn = R200_COMB_FCN_RSUB_CLAMP; - break; - - case GL_MIN: - eqn = R200_COMB_FCN_MIN; - func = (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | - (R200_BLEND_GL_ONE << R200_DST_BLEND_SHIFT); - break; - - case GL_MAX: - eqn = R200_COMB_FCN_MAX; - func = (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | - (R200_BLEND_GL_ONE << R200_DST_BLEND_SHIFT); - break; - - default: - fprintf( stderr, "[%s:%u] Invalid RGB blend equation (0x%04x).\n", - __func__, __LINE__, ctx->Color.Blend[0].EquationRGB ); - return; - } - - funcA = (blend_factor( ctx->Color.Blend[0].SrcA, GL_TRUE ) << R200_SRC_BLEND_SHIFT) | - (blend_factor( ctx->Color.Blend[0].DstA, GL_FALSE ) << R200_DST_BLEND_SHIFT); - - switch(ctx->Color.Blend[0].EquationA) { - case GL_FUNC_ADD: - eqnA = R200_COMB_FCN_ADD_CLAMP; - break; - - case GL_FUNC_SUBTRACT: - eqnA = R200_COMB_FCN_SUB_CLAMP; - break; - - case GL_FUNC_REVERSE_SUBTRACT: - eqnA = R200_COMB_FCN_RSUB_CLAMP; - break; - - case GL_MIN: - eqnA = R200_COMB_FCN_MIN; - funcA = (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | - (R200_BLEND_GL_ONE << R200_DST_BLEND_SHIFT); - break; - - case GL_MAX: - eqnA = R200_COMB_FCN_MAX; - funcA = (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | - (R200_BLEND_GL_ONE << R200_DST_BLEND_SHIFT); - break; - - default: - fprintf( stderr, "[%s:%u] Invalid A blend equation (0x%04x).\n", - __func__, __LINE__, ctx->Color.Blend[0].EquationA ); - return; - } - - rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = eqnA | funcA; - rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = eqn | func; - -} - -static void r200BlendEquationSeparate( struct gl_context *ctx, - GLenum modeRGB, GLenum modeA ) -{ - r200_set_blend_state( ctx ); -} - -static void r200BlendFuncSeparate( struct gl_context *ctx, - GLenum sfactorRGB, GLenum dfactorRGB, - GLenum sfactorA, GLenum dfactorA ) -{ - r200_set_blend_state( ctx ); -} - - -/* ============================================================= - * Depth testing - */ - -static void r200DepthFunc( struct gl_context *ctx, GLenum func ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - R200_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~R200_Z_TEST_MASK; - - switch ( ctx->Depth.Func ) { - case GL_NEVER: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_NEVER; - break; - case GL_LESS: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_LESS; - break; - case GL_EQUAL: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_EQUAL; - break; - case GL_LEQUAL: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_LEQUAL; - break; - case GL_GREATER: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_GREATER; - break; - case GL_NOTEQUAL: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_NEQUAL; - break; - case GL_GEQUAL: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_GEQUAL; - break; - case GL_ALWAYS: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_TEST_ALWAYS; - break; - } -} - -static void r200DepthMask( struct gl_context *ctx, GLboolean flag ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - R200_STATECHANGE( rmesa, ctx ); - - if ( ctx->Depth.Mask ) { - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_WRITE_ENABLE; - } else { - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~R200_Z_WRITE_ENABLE; - } -} - - -/* ============================================================= - * Fog - */ - - -static void r200Fogfv( struct gl_context *ctx, GLenum pname, const GLfloat *param ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - union { int i; float f; } c, d; - GLubyte col[4]; - GLuint i; - - c.i = rmesa->hw.fog.cmd[FOG_C]; - d.i = rmesa->hw.fog.cmd[FOG_D]; - - switch (pname) { - case GL_FOG_MODE: - if (!ctx->Fog.Enabled) - return; - R200_STATECHANGE(rmesa, tcl); - rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~R200_TCL_FOG_MASK; - switch (ctx->Fog.Mode) { - case GL_LINEAR: - rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_LINEAR; - if (ctx->Fog.Start == ctx->Fog.End) { - c.f = 1.0F; - d.f = 1.0F; - } - else { - c.f = ctx->Fog.End/(ctx->Fog.End-ctx->Fog.Start); - d.f = -1.0/(ctx->Fog.End-ctx->Fog.Start); - } - break; - case GL_EXP: - rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_EXP; - c.f = 0.0; - d.f = -ctx->Fog.Density; - break; - case GL_EXP2: - rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_EXP2; - c.f = 0.0; - d.f = -(ctx->Fog.Density * ctx->Fog.Density); - break; - default: - return; - } - break; - case GL_FOG_DENSITY: - switch (ctx->Fog.Mode) { - case GL_EXP: - c.f = 0.0; - d.f = -ctx->Fog.Density; - break; - case GL_EXP2: - c.f = 0.0; - d.f = -(ctx->Fog.Density * ctx->Fog.Density); - break; - default: - break; - } - break; - case GL_FOG_START: - case GL_FOG_END: - if (ctx->Fog.Mode == GL_LINEAR) { - if (ctx->Fog.Start == ctx->Fog.End) { - c.f = 1.0F; - d.f = 1.0F; - } else { - c.f = ctx->Fog.End/(ctx->Fog.End-ctx->Fog.Start); - d.f = -1.0/(ctx->Fog.End-ctx->Fog.Start); - } - } - break; - case GL_FOG_COLOR: - R200_STATECHANGE( rmesa, ctx ); - _mesa_unclamped_float_rgba_to_ubyte(col, ctx->Fog.Color ); - i = radeonPackColor( 4, col[0], col[1], col[2], 0 ); - rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] &= ~R200_FOG_COLOR_MASK; - rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] |= i; - break; - case GL_FOG_COORD_SRC: { - GLuint out_0 = rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0]; - GLuint fog = rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR]; - - fog &= ~R200_FOG_USE_MASK; - if ( ctx->Fog.FogCoordinateSource == GL_FOG_COORD || ctx->VertexProgram.Enabled) { - fog |= R200_FOG_USE_VTX_FOG; - out_0 |= R200_VTX_DISCRETE_FOG; - } - else { - fog |= R200_FOG_USE_SPEC_ALPHA; - out_0 &= ~R200_VTX_DISCRETE_FOG; - } - - if ( fog != rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] ) { - R200_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = fog; - } - - if (out_0 != rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0]) { - R200_STATECHANGE( rmesa, vtx ); - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] = out_0; - } - - break; - } - default: - return; - } - - if (c.i != rmesa->hw.fog.cmd[FOG_C] || d.i != rmesa->hw.fog.cmd[FOG_D]) { - R200_STATECHANGE( rmesa, fog ); - rmesa->hw.fog.cmd[FOG_C] = c.i; - rmesa->hw.fog.cmd[FOG_D] = d.i; - } -} - -/* ============================================================= - * Culling - */ - -static void r200CullFace( struct gl_context *ctx, GLenum unused ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint s = rmesa->hw.set.cmd[SET_SE_CNTL]; - GLuint t = rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL]; - - s |= R200_FFACE_SOLID | R200_BFACE_SOLID; - t &= ~(R200_CULL_FRONT | R200_CULL_BACK); - - if ( ctx->Polygon.CullFlag ) { - switch ( ctx->Polygon.CullFaceMode ) { - case GL_FRONT: - s &= ~R200_FFACE_SOLID; - t |= R200_CULL_FRONT; - break; - case GL_BACK: - s &= ~R200_BFACE_SOLID; - t |= R200_CULL_BACK; - break; - case GL_FRONT_AND_BACK: - s &= ~(R200_FFACE_SOLID | R200_BFACE_SOLID); - t |= (R200_CULL_FRONT | R200_CULL_BACK); - break; - } - } - - if ( rmesa->hw.set.cmd[SET_SE_CNTL] != s ) { - R200_STATECHANGE(rmesa, set ); - rmesa->hw.set.cmd[SET_SE_CNTL] = s; - } - - if ( rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] != t ) { - R200_STATECHANGE(rmesa, tcl ); - rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = t; - } -} - -static void r200FrontFace( struct gl_context *ctx, GLenum mode ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - int cull_face = (mode == GL_CW) ? R200_FFACE_CULL_CW : R200_FFACE_CULL_CCW; - - R200_STATECHANGE( rmesa, set ); - rmesa->hw.set.cmd[SET_SE_CNTL] &= ~R200_FFACE_CULL_DIR_MASK; - - R200_STATECHANGE( rmesa, tcl ); - rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~R200_CULL_FRONT_IS_CCW; - - /* Winding is inverted when rendering to FBO */ - if (ctx->DrawBuffer && _mesa_is_user_fbo(ctx->DrawBuffer)) - cull_face = (mode == GL_CCW) ? R200_FFACE_CULL_CW : R200_FFACE_CULL_CCW; - rmesa->hw.set.cmd[SET_SE_CNTL] |= cull_face; - - if ( mode == GL_CCW ) - rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_CULL_FRONT_IS_CCW; -} - -/* ============================================================= - * Point state - */ -static void r200PointSize( struct gl_context *ctx, GLfloat size ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLfloat *fcmd = (GLfloat *)rmesa->hw.ptp.cmd; - - radeon_print(RADEON_STATE, RADEON_TRACE, - "%s(%p) size: %f, fixed point result: %d.%d (%d/16)\n", - __func__, ctx, size, - ((GLuint)(ctx->Point.Size * 16.0))/16, - (((GLuint)(ctx->Point.Size * 16.0))&15)*100/16, - ((GLuint)(ctx->Point.Size * 16.0))&15); - - R200_STATECHANGE( rmesa, cst ); - R200_STATECHANGE( rmesa, ptp ); - rmesa->hw.cst.cmd[CST_RE_POINTSIZE] &= ~0xffff; - rmesa->hw.cst.cmd[CST_RE_POINTSIZE] |= ((GLuint)(ctx->Point.Size * 16.0)); -/* this is the size param of the point size calculation (point size reg value - is not used when calculation is active). */ - fcmd[PTP_VPORT_SCALE_PTSIZE] = ctx->Point.Size; -} - -static void r200PointParameter( struct gl_context *ctx, GLenum pname, const GLfloat *params) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLfloat *fcmd = (GLfloat *)rmesa->hw.ptp.cmd; - - switch (pname) { - case GL_POINT_SIZE_MIN: - /* Can clamp both in tcl and setup - just set both (as does fglrx) */ - R200_STATECHANGE( rmesa, lin ); - R200_STATECHANGE( rmesa, ptp ); - rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] &= 0xffff; - rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] |= (GLuint)(ctx->Point.MinSize * 16.0) << 16; - fcmd[PTP_CLAMP_MIN] = ctx->Point.MinSize; - break; - case GL_POINT_SIZE_MAX: - R200_STATECHANGE( rmesa, cst ); - R200_STATECHANGE( rmesa, ptp ); - rmesa->hw.cst.cmd[CST_RE_POINTSIZE] &= 0xffff; - rmesa->hw.cst.cmd[CST_RE_POINTSIZE] |= (GLuint)(ctx->Point.MaxSize * 16.0) << 16; - fcmd[PTP_CLAMP_MAX] = ctx->Point.MaxSize; - break; - case GL_POINT_DISTANCE_ATTENUATION: - R200_STATECHANGE( rmesa, vtx ); - R200_STATECHANGE( rmesa, spr ); - R200_STATECHANGE( rmesa, ptp ); - GLfloat *fcmd = (GLfloat *)rmesa->hw.ptp.cmd; - rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] &= - ~(R200_PS_MULT_MASK | R200_PS_LIN_ATT_ZERO | R200_PS_SE_SEL_STATE); - /* can't rely on ctx->Point._Attenuated here and test for NEW_POINT in - r200ValidateState looks like overkill */ - if (ctx->Point.Params[0] != 1.0 || - ctx->Point.Params[1] != 0.0 || - ctx->Point.Params[2] != 0.0 || - (ctx->VertexProgram.Enabled && ctx->VertexProgram.PointSizeEnabled)) { - /* all we care for vp would be the ps_se_sel_state setting */ - fcmd[PTP_ATT_CONST_QUAD] = ctx->Point.Params[2]; - fcmd[PTP_ATT_CONST_LIN] = ctx->Point.Params[1]; - fcmd[PTP_ATT_CONST_CON] = ctx->Point.Params[0]; - rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] |= R200_PS_MULT_ATTENCONST; - if (ctx->Point.Params[1] == 0.0) - rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] |= R200_PS_LIN_ATT_ZERO; -/* FIXME: setting this here doesn't look quite ok - we only want to do - that if we're actually drawing points probably */ - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] |= R200_OUTPUT_PT_SIZE; - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= R200_VTX_POINT_SIZE; - } - else { - rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] |= - R200_PS_SE_SEL_STATE | R200_PS_MULT_CONST; - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] &= ~R200_OUTPUT_PT_SIZE; - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] &= ~R200_VTX_POINT_SIZE; - } - break; - case GL_POINT_FADE_THRESHOLD_SIZE: - /* don't support multisampling, so doesn't matter. */ - break; - /* can't do these but don't need them. - case GL_POINT_SPRITE_COORD_ORIGIN: */ - default: - fprintf(stderr, "bad pname parameter in r200PointParameter\n"); - return; - } -} - -/* ============================================================= - * Line state - */ -static void r200LineWidth( struct gl_context *ctx, GLfloat widthf ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - R200_STATECHANGE( rmesa, lin ); - R200_STATECHANGE( rmesa, set ); - - /* Line width is stored in U6.4 format. - * Same min/max limits for AA, non-AA lines. - */ - rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] &= ~0xffff; - rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] |= (GLuint) - (CLAMP(widthf, ctx->Const.MinLineWidth, ctx->Const.MaxLineWidth) * 16.0); - - if ( widthf > 1.0 ) { - rmesa->hw.set.cmd[SET_SE_CNTL] |= R200_WIDELINE_ENABLE; - } else { - rmesa->hw.set.cmd[SET_SE_CNTL] &= ~R200_WIDELINE_ENABLE; - } -} - -static void r200LineStipple( struct gl_context *ctx, GLint factor, GLushort pattern ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - R200_STATECHANGE( rmesa, lin ); - rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = - ((((GLuint)factor & 0xff) << 16) | ((GLuint)pattern)); -} - - -/* ============================================================= - * Masks - */ -static void r200ColorMask( struct gl_context *ctx, - GLboolean r, GLboolean g, - GLboolean b, GLboolean a ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint mask; - struct radeon_renderbuffer *rrb; - GLuint flag = rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] & ~R200_PLANE_MASK_ENABLE; - - rrb = radeon_get_colorbuffer(&rmesa->radeon); - if (!rrb) - return; - mask = radeonPackColor( rrb->cpp, - GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 0)*0xFF, - GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 1)*0xFF, - GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 2)*0xFF, - GET_COLORMASK_BIT(ctx->Color.ColorMask, 0, 3)*0xFF ); - - - if (!(r && g && b && a)) - flag |= R200_PLANE_MASK_ENABLE; - - if ( rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] != flag ) { - R200_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = flag; - } - - if ( rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] != mask ) { - R200_STATECHANGE( rmesa, msk ); - rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = mask; - } -} - - -/* ============================================================= - * Polygon state - */ - -static void r200PolygonOffset( struct gl_context *ctx, - GLfloat factor, GLfloat units, GLfloat clamp ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - const GLfloat depthScale = 1.0F / ctx->DrawBuffer->_DepthMaxF; - float_ui32_type constant = { units * depthScale }; - float_ui32_type factoru = { factor }; - -/* factor *= 2; */ -/* constant *= 2; */ - -/* fprintf(stderr, "%s f:%f u:%f\n", __func__, factor, constant); */ - - R200_STATECHANGE( rmesa, zbs ); - rmesa->hw.zbs.cmd[ZBS_SE_ZBIAS_FACTOR] = factoru.ui32; - rmesa->hw.zbs.cmd[ZBS_SE_ZBIAS_CONSTANT] = constant.ui32; -} - -static void r200PolygonMode( struct gl_context *ctx, GLenum face, GLenum mode ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL || - ctx->Polygon.BackMode != GL_FILL); - - /* Can't generally do unfilled via tcl, but some good special - * cases work. - */ - TCL_FALLBACK( ctx, R200_TCL_FALLBACK_UNFILLED, unfilled); - if (rmesa->radeon.TclFallback) { - r200ChooseRenderState( ctx ); - r200ChooseVertexState( ctx ); - } -} - - -/* ============================================================= - * Rendering attributes - * - * We really don't want to recalculate all this every time we bind a - * texture. These things shouldn't change all that often, so it makes - * sense to break them out of the core texture state update routines. - */ - -/* Examine lighting and texture state to determine if separate specular - * should be enabled. - */ -static void r200UpdateSpecular( struct gl_context *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - uint32_t p = rmesa->hw.ctx.cmd[CTX_PP_CNTL]; - - R200_STATECHANGE( rmesa, tcl ); - R200_STATECHANGE( rmesa, vtx ); - - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] &= ~(3<<R200_VTX_COLOR_0_SHIFT); - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] &= ~(3<<R200_VTX_COLOR_1_SHIFT); - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] &= ~R200_OUTPUT_COLOR_0; - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] &= ~R200_OUTPUT_COLOR_1; - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &= ~R200_LIGHTING_ENABLE; - - p &= ~R200_SPECULAR_ENABLE; - - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_DIFFUSE_SPECULAR_COMBINE; - - - if (ctx->Light.Enabled && - ctx->Light.Model.ColorControl == GL_SEPARATE_SPECULAR_COLOR) { - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= - ((R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT) | - (R200_VTX_FP_RGBA << R200_VTX_COLOR_1_SHIFT)); - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] |= R200_OUTPUT_COLOR_0; - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] |= R200_OUTPUT_COLOR_1; - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_LIGHTING_ENABLE; - p |= R200_SPECULAR_ENABLE; - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &= - ~R200_DIFFUSE_SPECULAR_COMBINE; - } - else if (ctx->Light.Enabled) { - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= - ((R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)); - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] |= R200_OUTPUT_COLOR_0; - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_LIGHTING_ENABLE; - } else if (ctx->Fog.ColorSumEnabled ) { - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= - ((R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT) | - (R200_VTX_FP_RGBA << R200_VTX_COLOR_1_SHIFT)); - p |= R200_SPECULAR_ENABLE; - } else { - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= - ((R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT)); - } - - if (ctx->Fog.Enabled) { - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] |= - ((R200_VTX_FP_RGBA << R200_VTX_COLOR_1_SHIFT)); - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] |= R200_OUTPUT_COLOR_1; - } - - if ( rmesa->hw.ctx.cmd[CTX_PP_CNTL] != p ) { - R200_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_PP_CNTL] = p; - } - - /* Update vertex/render formats - */ - if (rmesa->radeon.TclFallback) { - r200ChooseRenderState( ctx ); - r200ChooseVertexState( ctx ); - } -} - - -/* ============================================================= - * Materials - */ - - -/* Update on colormaterial, material emmissive/ambient, - * lightmodel.globalambient - */ -static void update_global_ambient( struct gl_context *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - float *fcmd = (float *)R200_DB_STATE( glt ); - - /* Need to do more if both emmissive & ambient are PREMULT: - * I believe this is not nessary when using source_material. This condition thus - * will never happen currently, and the function has no dependencies on materials now - */ - if ((rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] & - ((3 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) | - (3 << R200_FRONT_AMBIENT_SOURCE_SHIFT))) == 0) - { - COPY_3V( &fcmd[GLT_RED], - ctx->Light.Material.Attrib[MAT_ATTRIB_FRONT_EMISSION]); - ACC_SCALE_3V( &fcmd[GLT_RED], - ctx->Light.Model.Ambient, - ctx->Light.Material.Attrib[MAT_ATTRIB_FRONT_AMBIENT]); - } - else - { - COPY_3V( &fcmd[GLT_RED], ctx->Light.Model.Ambient ); - } - - R200_DB_STATECHANGE(rmesa, &rmesa->hw.glt); -} - -/* Update on change to - * - light[p].colors - * - light[p].enabled - */ -static void update_light_colors( struct gl_context *ctx, GLuint p ) -{ - struct gl_light *l = &ctx->Light.Light[p]; - struct gl_light_uniforms *lu = &ctx->Light.LightSource[p]; - -/* fprintf(stderr, "%s\n", __func__); */ - - if (l->Enabled) { - r200ContextPtr rmesa = R200_CONTEXT(ctx); - float *fcmd = (float *)R200_DB_STATE( lit[p] ); - - COPY_4V( &fcmd[LIT_AMBIENT_RED], lu->Ambient ); - COPY_4V( &fcmd[LIT_DIFFUSE_RED], lu->Diffuse ); - COPY_4V( &fcmd[LIT_SPECULAR_RED], lu->Specular ); - - R200_DB_STATECHANGE( rmesa, &rmesa->hw.lit[p] ); - } -} - -static void r200ColorMaterial( struct gl_context *ctx, GLenum face, GLenum mode ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint light_model_ctl1 = rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1]; - light_model_ctl1 &= ~((0xf << R200_FRONT_EMISSIVE_SOURCE_SHIFT) | - (0xf << R200_FRONT_AMBIENT_SOURCE_SHIFT) | - (0xf << R200_FRONT_DIFFUSE_SOURCE_SHIFT) | - (0xf << R200_FRONT_SPECULAR_SOURCE_SHIFT) | - (0xf << R200_BACK_EMISSIVE_SOURCE_SHIFT) | - (0xf << R200_BACK_AMBIENT_SOURCE_SHIFT) | - (0xf << R200_BACK_DIFFUSE_SOURCE_SHIFT) | - (0xf << R200_BACK_SPECULAR_SOURCE_SHIFT)); - - if (ctx->Light.ColorMaterialEnabled) { - GLuint mask = ctx->Light._ColorMaterialBitmask; - - if (mask & MAT_BIT_FRONT_EMISSION) { - light_model_ctl1 |= (R200_LM1_SOURCE_VERTEX_COLOR_0 << - R200_FRONT_EMISSIVE_SOURCE_SHIFT); - } - else - light_model_ctl1 |= (R200_LM1_SOURCE_MATERIAL_0 << - R200_FRONT_EMISSIVE_SOURCE_SHIFT); - - if (mask & MAT_BIT_FRONT_AMBIENT) { - light_model_ctl1 |= (R200_LM1_SOURCE_VERTEX_COLOR_0 << - R200_FRONT_AMBIENT_SOURCE_SHIFT); - } - else - light_model_ctl1 |= (R200_LM1_SOURCE_MATERIAL_0 << - R200_FRONT_AMBIENT_SOURCE_SHIFT); - - if (mask & MAT_BIT_FRONT_DIFFUSE) { - light_model_ctl1 |= (R200_LM1_SOURCE_VERTEX_COLOR_0 << - R200_FRONT_DIFFUSE_SOURCE_SHIFT); - } - else - light_model_ctl1 |= (R200_LM1_SOURCE_MATERIAL_0 << - R200_FRONT_DIFFUSE_SOURCE_SHIFT); - - if (mask & MAT_BIT_FRONT_SPECULAR) { - light_model_ctl1 |= (R200_LM1_SOURCE_VERTEX_COLOR_0 << - R200_FRONT_SPECULAR_SOURCE_SHIFT); - } - else { - light_model_ctl1 |= (R200_LM1_SOURCE_MATERIAL_0 << - R200_FRONT_SPECULAR_SOURCE_SHIFT); - } - - if (mask & MAT_BIT_BACK_EMISSION) { - light_model_ctl1 |= (R200_LM1_SOURCE_VERTEX_COLOR_0 << - R200_BACK_EMISSIVE_SOURCE_SHIFT); - } - - else light_model_ctl1 |= (R200_LM1_SOURCE_MATERIAL_1 << - R200_BACK_EMISSIVE_SOURCE_SHIFT); - - if (mask & MAT_BIT_BACK_AMBIENT) { - light_model_ctl1 |= (R200_LM1_SOURCE_VERTEX_COLOR_0 << - R200_BACK_AMBIENT_SOURCE_SHIFT); - } - else light_model_ctl1 |= (R200_LM1_SOURCE_MATERIAL_1 << - R200_BACK_AMBIENT_SOURCE_SHIFT); - - if (mask & MAT_BIT_BACK_DIFFUSE) { - light_model_ctl1 |= (R200_LM1_SOURCE_VERTEX_COLOR_0 << - R200_BACK_DIFFUSE_SOURCE_SHIFT); - } - else light_model_ctl1 |= (R200_LM1_SOURCE_MATERIAL_1 << - R200_BACK_DIFFUSE_SOURCE_SHIFT); - - if (mask & MAT_BIT_BACK_SPECULAR) { - light_model_ctl1 |= (R200_LM1_SOURCE_VERTEX_COLOR_0 << - R200_BACK_SPECULAR_SOURCE_SHIFT); - } - else { - light_model_ctl1 |= (R200_LM1_SOURCE_MATERIAL_1 << - R200_BACK_SPECULAR_SOURCE_SHIFT); - } - } - else { - /* Default to SOURCE_MATERIAL: - */ - light_model_ctl1 |= - (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) | - (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) | - (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) | - (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) | - (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) | - (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) | - (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) | - (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT); - } - - if (light_model_ctl1 != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1]) { - R200_STATECHANGE( rmesa, tcl ); - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] = light_model_ctl1; - } - - -} - -void r200UpdateMaterial( struct gl_context *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLfloat (*mat)[4] = ctx->Light.Material.Attrib; - GLfloat *fcmd = (GLfloat *)R200_DB_STATE( mtl[0] ); - GLfloat *fcmd2 = (GLfloat *)R200_DB_STATE( mtl[1] ); - GLuint mask = ~0; - - /* Might be possible and faster to update everything unconditionally? */ - if (ctx->Light.ColorMaterialEnabled) - mask &= ~ctx->Light._ColorMaterialBitmask; - - if (R200_DEBUG & RADEON_STATE) - fprintf(stderr, "%s\n", __func__); - - if (mask & MAT_BIT_FRONT_EMISSION) { - fcmd[MTL_EMMISSIVE_RED] = mat[MAT_ATTRIB_FRONT_EMISSION][0]; - fcmd[MTL_EMMISSIVE_GREEN] = mat[MAT_ATTRIB_FRONT_EMISSION][1]; - fcmd[MTL_EMMISSIVE_BLUE] = mat[MAT_ATTRIB_FRONT_EMISSION][2]; - fcmd[MTL_EMMISSIVE_ALPHA] = mat[MAT_ATTRIB_FRONT_EMISSION][3]; - } - if (mask & MAT_BIT_FRONT_AMBIENT) { - fcmd[MTL_AMBIENT_RED] = mat[MAT_ATTRIB_FRONT_AMBIENT][0]; - fcmd[MTL_AMBIENT_GREEN] = mat[MAT_ATTRIB_FRONT_AMBIENT][1]; - fcmd[MTL_AMBIENT_BLUE] = mat[MAT_ATTRIB_FRONT_AMBIENT][2]; - fcmd[MTL_AMBIENT_ALPHA] = mat[MAT_ATTRIB_FRONT_AMBIENT][3]; - } - if (mask & MAT_BIT_FRONT_DIFFUSE) { - fcmd[MTL_DIFFUSE_RED] = mat[MAT_ATTRIB_FRONT_DIFFUSE][0]; - fcmd[MTL_DIFFUSE_GREEN] = mat[MAT_ATTRIB_FRONT_DIFFUSE][1]; - fcmd[MTL_DIFFUSE_BLUE] = mat[MAT_ATTRIB_FRONT_DIFFUSE][2]; - fcmd[MTL_DIFFUSE_ALPHA] = mat[MAT_ATTRIB_FRONT_DIFFUSE][3]; - } - if (mask & MAT_BIT_FRONT_SPECULAR) { - fcmd[MTL_SPECULAR_RED] = mat[MAT_ATTRIB_FRONT_SPECULAR][0]; - fcmd[MTL_SPECULAR_GREEN] = mat[MAT_ATTRIB_FRONT_SPECULAR][1]; - fcmd[MTL_SPECULAR_BLUE] = mat[MAT_ATTRIB_FRONT_SPECULAR][2]; - fcmd[MTL_SPECULAR_ALPHA] = mat[MAT_ATTRIB_FRONT_SPECULAR][3]; - } - if (mask & MAT_BIT_FRONT_SHININESS) { - fcmd[MTL_SHININESS] = mat[MAT_ATTRIB_FRONT_SHININESS][0]; - } - - if (mask & MAT_BIT_BACK_EMISSION) { - fcmd2[MTL_EMMISSIVE_RED] = mat[MAT_ATTRIB_BACK_EMISSION][0]; - fcmd2[MTL_EMMISSIVE_GREEN] = mat[MAT_ATTRIB_BACK_EMISSION][1]; - fcmd2[MTL_EMMISSIVE_BLUE] = mat[MAT_ATTRIB_BACK_EMISSION][2]; - fcmd2[MTL_EMMISSIVE_ALPHA] = mat[MAT_ATTRIB_BACK_EMISSION][3]; - } - if (mask & MAT_BIT_BACK_AMBIENT) { - fcmd2[MTL_AMBIENT_RED] = mat[MAT_ATTRIB_BACK_AMBIENT][0]; - fcmd2[MTL_AMBIENT_GREEN] = mat[MAT_ATTRIB_BACK_AMBIENT][1]; - fcmd2[MTL_AMBIENT_BLUE] = mat[MAT_ATTRIB_BACK_AMBIENT][2]; - fcmd2[MTL_AMBIENT_ALPHA] = mat[MAT_ATTRIB_BACK_AMBIENT][3]; - } - if (mask & MAT_BIT_BACK_DIFFUSE) { - fcmd2[MTL_DIFFUSE_RED] = mat[MAT_ATTRIB_BACK_DIFFUSE][0]; - fcmd2[MTL_DIFFUSE_GREEN] = mat[MAT_ATTRIB_BACK_DIFFUSE][1]; - fcmd2[MTL_DIFFUSE_BLUE] = mat[MAT_ATTRIB_BACK_DIFFUSE][2]; - fcmd2[MTL_DIFFUSE_ALPHA] = mat[MAT_ATTRIB_BACK_DIFFUSE][3]; - } - if (mask & MAT_BIT_BACK_SPECULAR) { - fcmd2[MTL_SPECULAR_RED] = mat[MAT_ATTRIB_BACK_SPECULAR][0]; - fcmd2[MTL_SPECULAR_GREEN] = mat[MAT_ATTRIB_BACK_SPECULAR][1]; - fcmd2[MTL_SPECULAR_BLUE] = mat[MAT_ATTRIB_BACK_SPECULAR][2]; - fcmd2[MTL_SPECULAR_ALPHA] = mat[MAT_ATTRIB_BACK_SPECULAR][3]; - } - if (mask & MAT_BIT_BACK_SHININESS) { - fcmd2[MTL_SHININESS] = mat[MAT_ATTRIB_BACK_SHININESS][0]; - } - - R200_DB_STATECHANGE( rmesa, &rmesa->hw.mtl[0] ); - R200_DB_STATECHANGE( rmesa, &rmesa->hw.mtl[1] ); - - /* currently material changes cannot trigger a global ambient change, I believe this is correct - update_global_ambient( ctx ); */ -} - -/* _NEW_LIGHT - * _NEW_MODELVIEW - * _MESA_NEW_NEED_EYE_COORDS - * - * Uses derived state from mesa: - * _VP_inf_norm - * _h_inf_norm - * _Position - * _NormSpotDirection - * _ModelViewInvScale - * _NeedEyeCoords - * _EyeZDir - * - * which are calculated in light.c and are correct for the current - * lighting space (model or eye), hence dependencies on _NEW_MODELVIEW - * and _MESA_NEW_NEED_EYE_COORDS. - */ -static void update_light( struct gl_context *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - /* Have to check these, or have an automatic shortcircuit mechanism - * to remove noop statechanges. (Or just do a better job on the - * front end). - */ - { - GLuint tmp = rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0]; - - if (ctx->_NeedEyeCoords) - tmp &= ~R200_LIGHT_IN_MODELSPACE; - else - tmp |= R200_LIGHT_IN_MODELSPACE; - - if (tmp != rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0]) - { - R200_STATECHANGE( rmesa, tcl ); - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] = tmp; - } - } - - { - GLfloat *fcmd = (GLfloat *)R200_DB_STATE( eye ); - fcmd[EYE_X] = ctx->_EyeZDir[0]; - fcmd[EYE_Y] = ctx->_EyeZDir[1]; - fcmd[EYE_Z] = - ctx->_EyeZDir[2]; - fcmd[EYE_RESCALE_FACTOR] = ctx->_ModelViewInvScale; - R200_DB_STATECHANGE( rmesa, &rmesa->hw.eye ); - } - - - - if (ctx->Light.Enabled) { - GLbitfield mask = ctx->Light._EnabledLights; - while (mask) { - const int p = u_bit_scan(&mask); - struct gl_light *l = &ctx->Light.Light[p]; - struct gl_light_uniforms *lu = &ctx->Light.LightSource[p]; - GLfloat *fcmd = (GLfloat *)R200_DB_STATE( lit[p] ); - - if (lu->EyePosition[3] == 0.0) { - COPY_3FV( &fcmd[LIT_POSITION_X], l->_VP_inf_norm ); - COPY_3FV( &fcmd[LIT_DIRECTION_X], l->_h_inf_norm ); - fcmd[LIT_POSITION_W] = 0; - fcmd[LIT_DIRECTION_W] = 0; - } else { - COPY_4V( &fcmd[LIT_POSITION_X], l->_Position ); - fcmd[LIT_DIRECTION_X] = -l->_NormSpotDirection[0]; - fcmd[LIT_DIRECTION_Y] = -l->_NormSpotDirection[1]; - fcmd[LIT_DIRECTION_Z] = -l->_NormSpotDirection[2]; - fcmd[LIT_DIRECTION_W] = 0; - } - - R200_DB_STATECHANGE( rmesa, &rmesa->hw.lit[p] ); - } - } -} - -static void r200Lightfv( struct gl_context *ctx, GLenum light, - GLenum pname, const GLfloat *params ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLint p = light - GL_LIGHT0; - struct gl_light_uniforms *lu = &ctx->Light.LightSource[p]; - GLfloat *fcmd = (GLfloat *)rmesa->hw.lit[p].cmd; - - - switch (pname) { - case GL_AMBIENT: - case GL_DIFFUSE: - case GL_SPECULAR: - update_light_colors( ctx, p ); - break; - - case GL_SPOT_DIRECTION: - /* picked up in update_light */ - break; - - case GL_POSITION: { - /* positions picked up in update_light, but can do flag here */ - GLuint flag = (p&1)? R200_LIGHT_1_IS_LOCAL : R200_LIGHT_0_IS_LOCAL; - GLuint idx = TCL_PER_LIGHT_CTL_0 + p/2; - - R200_STATECHANGE(rmesa, tcl); - if (lu->EyePosition[3] != 0.0F) - rmesa->hw.tcl.cmd[idx] |= flag; - else - rmesa->hw.tcl.cmd[idx] &= ~flag; - break; - } - - case GL_SPOT_EXPONENT: - R200_STATECHANGE(rmesa, lit[p]); - fcmd[LIT_SPOT_EXPONENT] = params[0]; - break; - - case GL_SPOT_CUTOFF: { - GLuint flag = (p&1) ? R200_LIGHT_1_IS_SPOT : R200_LIGHT_0_IS_SPOT; - GLuint idx = TCL_PER_LIGHT_CTL_0 + p/2; - - R200_STATECHANGE(rmesa, lit[p]); - fcmd[LIT_SPOT_CUTOFF] = lu->_CosCutoff; - - R200_STATECHANGE(rmesa, tcl); - if (lu->SpotCutoff != 180.0F) - rmesa->hw.tcl.cmd[idx] |= flag; - else - rmesa->hw.tcl.cmd[idx] &= ~flag; - - break; - } - - case GL_CONSTANT_ATTENUATION: - R200_STATECHANGE(rmesa, lit[p]); - fcmd[LIT_ATTEN_CONST] = params[0]; - if ( params[0] == 0.0 ) - fcmd[LIT_ATTEN_CONST_INV] = FLT_MAX; - else - fcmd[LIT_ATTEN_CONST_INV] = 1.0 / params[0]; - break; - case GL_LINEAR_ATTENUATION: - R200_STATECHANGE(rmesa, lit[p]); - fcmd[LIT_ATTEN_LINEAR] = params[0]; - break; - case GL_QUADRATIC_ATTENUATION: - R200_STATECHANGE(rmesa, lit[p]); - fcmd[LIT_ATTEN_QUADRATIC] = params[0]; - break; - default: - return; - } - - /* Set RANGE_ATTEN only when needed */ - switch (pname) { - case GL_POSITION: - case GL_CONSTANT_ATTENUATION: - case GL_LINEAR_ATTENUATION: - case GL_QUADRATIC_ATTENUATION: { - GLuint *icmd = (GLuint *)R200_DB_STATE( tcl ); - GLuint idx = TCL_PER_LIGHT_CTL_0 + p/2; - GLuint atten_flag = ( p&1 ) ? R200_LIGHT_1_ENABLE_RANGE_ATTEN - : R200_LIGHT_0_ENABLE_RANGE_ATTEN; - GLuint atten_const_flag = ( p&1 ) ? R200_LIGHT_1_CONSTANT_RANGE_ATTEN - : R200_LIGHT_0_CONSTANT_RANGE_ATTEN; - - if ( lu->EyePosition[3] == 0.0F || - ( ( fcmd[LIT_ATTEN_CONST] == 0.0 || fcmd[LIT_ATTEN_CONST] == 1.0 ) && - fcmd[LIT_ATTEN_QUADRATIC] == 0.0 && fcmd[LIT_ATTEN_LINEAR] == 0.0 ) ) { - /* Disable attenuation */ - icmd[idx] &= ~atten_flag; - } else { - if ( fcmd[LIT_ATTEN_QUADRATIC] == 0.0 && fcmd[LIT_ATTEN_LINEAR] == 0.0 ) { - /* Enable only constant portion of attenuation calculation */ - icmd[idx] |= ( atten_flag | atten_const_flag ); - } else { - /* Enable full attenuation calculation */ - icmd[idx] &= ~atten_const_flag; - icmd[idx] |= atten_flag; - } - } - - R200_DB_STATECHANGE( rmesa, &rmesa->hw.tcl ); - break; - } - default: - break; - } -} - -static void r200UpdateLocalViewer ( struct gl_context *ctx ) -{ -/* It looks like for the texgen modes GL_SPHERE_MAP, GL_NORMAL_MAP and - GL_REFLECTION_MAP we need R200_LOCAL_VIEWER set (fglrx does exactly that - for these and only these modes). This means specular highlights may turn out - wrong in some cases when lighting is enabled but GL_LIGHT_MODEL_LOCAL_VIEWER - is not set, though it seems to happen rarely and the effect seems quite - subtle. May need TCL fallback to fix it completely, though I'm not sure - how you'd identify the cases where the specular highlights indeed will - be wrong. Don't know if fglrx does something special in that case. -*/ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - R200_STATECHANGE( rmesa, tcl ); - if (ctx->Light.Model.LocalViewer || - ctx->Texture._GenFlags & TEXGEN_NEED_NORMALS) - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_LOCAL_VIEWER; - else - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &= ~R200_LOCAL_VIEWER; -} - -static void r200LightModelfv( struct gl_context *ctx, GLenum pname, - const GLfloat *param ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - switch (pname) { - case GL_LIGHT_MODEL_AMBIENT: - update_global_ambient( ctx ); - break; - - case GL_LIGHT_MODEL_LOCAL_VIEWER: - r200UpdateLocalViewer( ctx ); - break; - - case GL_LIGHT_MODEL_TWO_SIDE: - R200_STATECHANGE( rmesa, tcl ); - if (ctx->Light.Model.TwoSide) - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_LIGHT_TWOSIDE; - else - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &= ~(R200_LIGHT_TWOSIDE); - if (rmesa->radeon.TclFallback) { - r200ChooseRenderState( ctx ); - r200ChooseVertexState( ctx ); - } - break; - - case GL_LIGHT_MODEL_COLOR_CONTROL: - r200UpdateSpecular(ctx); - break; - - default: - break; - } -} - -static void r200ShadeModel( struct gl_context *ctx, GLenum mode ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint s = rmesa->hw.set.cmd[SET_SE_CNTL]; - - s &= ~(R200_DIFFUSE_SHADE_MASK | - R200_ALPHA_SHADE_MASK | - R200_SPECULAR_SHADE_MASK | - R200_FOG_SHADE_MASK | - R200_DISC_FOG_SHADE_MASK); - - switch ( mode ) { - case GL_FLAT: - s |= (R200_DIFFUSE_SHADE_FLAT | - R200_ALPHA_SHADE_FLAT | - R200_SPECULAR_SHADE_FLAT | - R200_FOG_SHADE_FLAT | - R200_DISC_FOG_SHADE_FLAT); - break; - case GL_SMOOTH: - s |= (R200_DIFFUSE_SHADE_GOURAUD | - R200_ALPHA_SHADE_GOURAUD | - R200_SPECULAR_SHADE_GOURAUD | - R200_FOG_SHADE_GOURAUD | - R200_DISC_FOG_SHADE_GOURAUD); - break; - default: - return; - } - - if ( rmesa->hw.set.cmd[SET_SE_CNTL] != s ) { - R200_STATECHANGE( rmesa, set ); - rmesa->hw.set.cmd[SET_SE_CNTL] = s; - } -} - - -/* ============================================================= - * User clip planes - */ - -static void r200ClipPlane( struct gl_context *ctx, GLenum plane, const GLfloat *eq ) -{ - GLint p = (GLint) plane - (GLint) GL_CLIP_PLANE0; - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p]; - - R200_STATECHANGE( rmesa, ucp[p] ); - rmesa->hw.ucp[p].cmd[UCP_X] = ip[0]; - rmesa->hw.ucp[p].cmd[UCP_Y] = ip[1]; - rmesa->hw.ucp[p].cmd[UCP_Z] = ip[2]; - rmesa->hw.ucp[p].cmd[UCP_W] = ip[3]; -} - -static void r200UpdateClipPlanes( struct gl_context *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLbitfield mask = ctx->Transform.ClipPlanesEnabled; - - while (mask) { - const int p = u_bit_scan(&mask); - GLint *ip = (GLint *)ctx->Transform._ClipUserPlane[p]; - - R200_STATECHANGE( rmesa, ucp[p] ); - rmesa->hw.ucp[p].cmd[UCP_X] = ip[0]; - rmesa->hw.ucp[p].cmd[UCP_Y] = ip[1]; - rmesa->hw.ucp[p].cmd[UCP_Z] = ip[2]; - rmesa->hw.ucp[p].cmd[UCP_W] = ip[3]; - } -} - - -/* ============================================================= - * Stencil - */ - -static void -r200StencilFuncSeparate( struct gl_context *ctx, GLenum face, GLenum func, - GLint ref, GLuint mask ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint refmask = ((_mesa_get_stencil_ref(ctx, 0) << R200_STENCIL_REF_SHIFT) | - ((ctx->Stencil.ValueMask[0] & 0xff) << R200_STENCIL_MASK_SHIFT)); - - R200_STATECHANGE( rmesa, ctx ); - R200_STATECHANGE( rmesa, msk ); - - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~R200_STENCIL_TEST_MASK; - rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] &= ~(R200_STENCIL_REF_MASK| - R200_STENCIL_VALUE_MASK); - - switch ( ctx->Stencil.Function[0] ) { - case GL_NEVER: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_TEST_NEVER; - break; - case GL_LESS: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_TEST_LESS; - break; - case GL_EQUAL: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_TEST_EQUAL; - break; - case GL_LEQUAL: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_TEST_LEQUAL; - break; - case GL_GREATER: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_TEST_GREATER; - break; - case GL_NOTEQUAL: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_TEST_NEQUAL; - break; - case GL_GEQUAL: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_TEST_GEQUAL; - break; - case GL_ALWAYS: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_TEST_ALWAYS; - break; - } - - rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] |= refmask; -} - -static void -r200StencilMaskSeparate( struct gl_context *ctx, GLenum face, GLuint mask ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - R200_STATECHANGE( rmesa, msk ); - rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] &= ~R200_STENCIL_WRITE_MASK; - rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] |= - ((ctx->Stencil.WriteMask[0] & 0xff) << R200_STENCIL_WRITEMASK_SHIFT); -} - -static void -r200StencilOpSeparate( struct gl_context *ctx, GLenum face, GLenum fail, - GLenum zfail, GLenum zpass ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - R200_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] &= ~(R200_STENCIL_FAIL_MASK | - R200_STENCIL_ZFAIL_MASK | - R200_STENCIL_ZPASS_MASK); - - switch ( ctx->Stencil.FailFunc[0] ) { - case GL_KEEP: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_FAIL_KEEP; - break; - case GL_ZERO: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_FAIL_ZERO; - break; - case GL_REPLACE: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_FAIL_REPLACE; - break; - case GL_INCR: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_FAIL_INC; - break; - case GL_DECR: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_FAIL_DEC; - break; - case GL_INCR_WRAP_EXT: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_FAIL_INC_WRAP; - break; - case GL_DECR_WRAP_EXT: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_FAIL_DEC_WRAP; - break; - case GL_INVERT: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_FAIL_INVERT; - break; - } - - switch ( ctx->Stencil.ZFailFunc[0] ) { - case GL_KEEP: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZFAIL_KEEP; - break; - case GL_ZERO: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZFAIL_ZERO; - break; - case GL_REPLACE: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZFAIL_REPLACE; - break; - case GL_INCR: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZFAIL_INC; - break; - case GL_DECR: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZFAIL_DEC; - break; - case GL_INCR_WRAP_EXT: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZFAIL_INC_WRAP; - break; - case GL_DECR_WRAP_EXT: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZFAIL_DEC_WRAP; - break; - case GL_INVERT: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZFAIL_INVERT; - break; - } - - switch ( ctx->Stencil.ZPassFunc[0] ) { - case GL_KEEP: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZPASS_KEEP; - break; - case GL_ZERO: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZPASS_ZERO; - break; - case GL_REPLACE: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZPASS_REPLACE; - break; - case GL_INCR: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZPASS_INC; - break; - case GL_DECR: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZPASS_DEC; - break; - case GL_INCR_WRAP_EXT: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZPASS_INC_WRAP; - break; - case GL_DECR_WRAP_EXT: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZPASS_DEC_WRAP; - break; - case GL_INVERT: - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_STENCIL_ZPASS_INVERT; - break; - } -} - - -/* ============================================================= - * Window position and viewport transformation - */ - -/** - * Called when window size or position changes or viewport or depth range - * state is changed. We update the hardware viewport state here. - */ -void r200UpdateWindow( struct gl_context *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - __DRIdrawable *dPriv = radeon_get_drawable(&rmesa->radeon); - GLfloat xoffset = 0; - GLfloat yoffset = dPriv ? (GLfloat) dPriv->h : 0; - const GLboolean render_to_fbo = (ctx->DrawBuffer ? _mesa_is_user_fbo(ctx->DrawBuffer) : 0); - float scale[3], translate[3]; - GLfloat y_scale, y_bias; - - if (render_to_fbo) { - y_scale = 1.0; - y_bias = 0; - } else { - y_scale = -1.0; - y_bias = yoffset; - } - - _mesa_get_viewport_xform(ctx, 0, scale, translate); - float_ui32_type sx = { scale[0] }; - float_ui32_type sy = { scale[1] * y_scale }; - float_ui32_type sz = { scale[2] }; - float_ui32_type tx = { translate[0] + xoffset }; - float_ui32_type ty = { (translate[1] * y_scale) + y_bias }; - float_ui32_type tz = { translate[2] }; - - R200_STATECHANGE( rmesa, vpt ); - - rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = sx.ui32; - rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = tx.ui32; - rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = sy.ui32; - rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = ty.ui32; - rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = sz.ui32; - rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = tz.ui32; -} - -void r200_vtbl_update_scissor( struct gl_context *ctx ) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - unsigned x1, y1, x2, y2; - struct radeon_renderbuffer *rrb; - - R200_SET_STATE(r200, set, SET_RE_CNTL, R200_SCISSOR_ENABLE | r200->hw.set.cmd[SET_RE_CNTL]); - - if (r200->radeon.state.scissor.enabled) { - x1 = r200->radeon.state.scissor.rect.x1; - y1 = r200->radeon.state.scissor.rect.y1; - x2 = r200->radeon.state.scissor.rect.x2; - y2 = r200->radeon.state.scissor.rect.y2; - } else { - rrb = radeon_get_colorbuffer(&r200->radeon); - x1 = 0; - y1 = 0; - x2 = rrb->base.Base.Width - 1; - y2 = rrb->base.Base.Height - 1; - } - - R200_SET_STATE(r200, sci, SCI_XY_1, x1 | (y1 << 16)); - R200_SET_STATE(r200, sci, SCI_XY_2, x2 | (y2 << 16)); -} - - -static void r200Viewport(struct gl_context *ctx) -{ - /* Don't pipeline viewport changes, conflict with window offset - * setting below. Could apply deltas to rescue pipelined viewport - * values, or keep the originals hanging around. - */ - r200UpdateWindow( ctx ); - - radeon_viewport(ctx); -} - -static void r200DepthRange(struct gl_context *ctx) -{ - r200UpdateWindow( ctx ); -} - -/* ============================================================= - * Miscellaneous - */ - -static void r200RenderMode( struct gl_context *ctx, GLenum mode ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - FALLBACK( rmesa, R200_FALLBACK_RENDER_MODE, (mode != GL_RENDER) ); -} - -static void r200LogicOpCode(struct gl_context *ctx, enum gl_logicop_mode opcode) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - assert((unsigned) opcode <= 15); - - R200_STATECHANGE( rmesa, msk ); - rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = opcode; -} - -/* ============================================================= - * State enable/disable - */ - -static void r200Enable( struct gl_context *ctx, GLenum cap, GLboolean state ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint p, flag; - - if ( R200_DEBUG & RADEON_STATE ) - fprintf( stderr, "%s( %s = %s )\n", __func__, - _mesa_enum_to_string( cap ), - state ? "GL_TRUE" : "GL_FALSE" ); - - switch ( cap ) { - /* Fast track this one... - */ - case GL_TEXTURE_1D: - case GL_TEXTURE_2D: - case GL_TEXTURE_3D: - break; - - case GL_ALPHA_TEST: - R200_STATECHANGE( rmesa, ctx ); - if (state) { - rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_ALPHA_TEST_ENABLE; - } else { - rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~R200_ALPHA_TEST_ENABLE; - } - break; - - case GL_BLEND: - case GL_COLOR_LOGIC_OP: - r200_set_blend_state( ctx ); - break; - - case GL_CLIP_PLANE0: - case GL_CLIP_PLANE1: - case GL_CLIP_PLANE2: - case GL_CLIP_PLANE3: - case GL_CLIP_PLANE4: - case GL_CLIP_PLANE5: - p = cap-GL_CLIP_PLANE0; - R200_STATECHANGE( rmesa, tcl ); - if (state) { - rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= (R200_UCP_ENABLE_0<<p); - r200ClipPlane( ctx, cap, NULL ); - } - else { - rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~(R200_UCP_ENABLE_0<<p); - } - break; - - case GL_COLOR_MATERIAL: - r200ColorMaterial( ctx, 0, 0 ); - r200UpdateMaterial( ctx ); - break; - - case GL_CULL_FACE: - r200CullFace( ctx, 0 ); - break; - - case GL_DEPTH_TEST: - R200_STATECHANGE(rmesa, ctx ); - if ( state ) { - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_Z_ENABLE; - } else { - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~R200_Z_ENABLE; - } - break; - - case GL_DITHER: - R200_STATECHANGE(rmesa, ctx ); - if ( state ) { - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE; - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~rmesa->radeon.state.color.roundEnable; - } else { - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~R200_DITHER_ENABLE; - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable; - } - break; - - case GL_FOG: - R200_STATECHANGE(rmesa, ctx ); - if ( state ) { - rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_FOG_ENABLE; - r200Fogfv( ctx, GL_FOG_MODE, NULL ); - } else { - rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~R200_FOG_ENABLE; - R200_STATECHANGE(rmesa, tcl); - rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~R200_TCL_FOG_MASK; - } - r200UpdateSpecular( ctx ); /* for PK_SPEC */ - if (rmesa->radeon.TclFallback) - r200ChooseVertexState( ctx ); - _mesa_allow_light_in_model( ctx, !state ); - break; - - case GL_LIGHT0: - case GL_LIGHT1: - case GL_LIGHT2: - case GL_LIGHT3: - case GL_LIGHT4: - case GL_LIGHT5: - case GL_LIGHT6: - case GL_LIGHT7: - R200_STATECHANGE(rmesa, tcl); - p = cap - GL_LIGHT0; - if (p&1) - flag = (R200_LIGHT_1_ENABLE | - R200_LIGHT_1_ENABLE_AMBIENT | - R200_LIGHT_1_ENABLE_SPECULAR); - else - flag = (R200_LIGHT_0_ENABLE | - R200_LIGHT_0_ENABLE_AMBIENT | - R200_LIGHT_0_ENABLE_SPECULAR); - - if (state) - rmesa->hw.tcl.cmd[p/2 + TCL_PER_LIGHT_CTL_0] |= flag; - else - rmesa->hw.tcl.cmd[p/2 + TCL_PER_LIGHT_CTL_0] &= ~flag; - - /* - */ - update_light_colors( ctx, p ); - break; - - case GL_LIGHTING: - r200UpdateSpecular(ctx); - /* for reflection map fixup - might set recheck_texgen for all units too */ - rmesa->radeon.NewGLState |= _NEW_TEXTURE; - break; - - case GL_LINE_SMOOTH: - R200_STATECHANGE( rmesa, ctx ); - if ( state ) { - rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_ANTI_ALIAS_LINE; - } else { - rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~R200_ANTI_ALIAS_LINE; - } - break; - - case GL_LINE_STIPPLE: - R200_STATECHANGE( rmesa, set ); - if ( state ) { - rmesa->hw.set.cmd[SET_RE_CNTL] |= R200_PATTERN_ENABLE; - } else { - rmesa->hw.set.cmd[SET_RE_CNTL] &= ~R200_PATTERN_ENABLE; - } - break; - - case GL_NORMALIZE: - R200_STATECHANGE( rmesa, tcl ); - if ( state ) { - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_NORMALIZE_NORMALS; - } else { - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &= ~R200_NORMALIZE_NORMALS; - } - break; - - /* Pointsize registers on r200 only work for point sprites, and point smooth - * doesn't work for point sprites (and isn't needed for 1.0 sized aa points). - * In any case, setting pointmin == pointsizemax == 1.0 for aa points - * is enough to satisfy conform. - */ - case GL_POINT_SMOOTH: - break; - - /* These don't really do anything, as we don't use the 3vtx - * primitives yet. - */ -#if 0 - case GL_POLYGON_OFFSET_POINT: - R200_STATECHANGE( rmesa, set ); - if ( state ) { - rmesa->hw.set.cmd[SET_SE_CNTL] |= R200_ZBIAS_ENABLE_POINT; - } else { - rmesa->hw.set.cmd[SET_SE_CNTL] &= ~R200_ZBIAS_ENABLE_POINT; - } - break; - - case GL_POLYGON_OFFSET_LINE: - R200_STATECHANGE( rmesa, set ); - if ( state ) { - rmesa->hw.set.cmd[SET_SE_CNTL] |= R200_ZBIAS_ENABLE_LINE; - } else { - rmesa->hw.set.cmd[SET_SE_CNTL] &= ~R200_ZBIAS_ENABLE_LINE; - } - break; -#endif - - case GL_POINT_SPRITE_ARB: - R200_STATECHANGE( rmesa, spr ); - if ( state ) { - rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] |= R200_PS_GEN_TEX_MASK & - (ctx->Point.CoordReplace << R200_PS_GEN_TEX_0_SHIFT); - } else { - rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] &= ~R200_PS_GEN_TEX_MASK; - } - break; - - case GL_POLYGON_OFFSET_FILL: - R200_STATECHANGE( rmesa, set ); - if ( state ) { - rmesa->hw.set.cmd[SET_SE_CNTL] |= R200_ZBIAS_ENABLE_TRI; - } else { - rmesa->hw.set.cmd[SET_SE_CNTL] &= ~R200_ZBIAS_ENABLE_TRI; - } - break; - - case GL_POLYGON_SMOOTH: - R200_STATECHANGE( rmesa, ctx ); - if ( state ) { - rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_ANTI_ALIAS_POLY; - } else { - rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~R200_ANTI_ALIAS_POLY; - } - break; - - case GL_POLYGON_STIPPLE: - R200_STATECHANGE(rmesa, set ); - if ( state ) { - rmesa->hw.set.cmd[SET_RE_CNTL] |= R200_STIPPLE_ENABLE; - } else { - rmesa->hw.set.cmd[SET_RE_CNTL] &= ~R200_STIPPLE_ENABLE; - } - break; - - case GL_RESCALE_NORMAL_EXT: { - GLboolean tmp = ctx->_NeedEyeCoords ? state : !state; - R200_STATECHANGE( rmesa, tcl ); - if ( tmp ) { - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_RESCALE_NORMALS; - } else { - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &= ~R200_RESCALE_NORMALS; - } - break; - } - - case GL_SCISSOR_TEST: - radeon_firevertices(&rmesa->radeon); - rmesa->radeon.state.scissor.enabled = state; - radeonUpdateScissor( ctx ); - break; - - case GL_STENCIL_TEST: - { - GLboolean hw_stencil = GL_FALSE; - if (ctx->DrawBuffer) { - struct radeon_renderbuffer *rrbStencil - = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL); - hw_stencil = (rrbStencil && rrbStencil->bo); - } - - if (hw_stencil) { - R200_STATECHANGE( rmesa, ctx ); - if ( state ) { - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_STENCIL_ENABLE; - } else { - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~R200_STENCIL_ENABLE; - } - } else { - FALLBACK( rmesa, R200_FALLBACK_STENCIL, state ); - } - } - break; - - case GL_TEXTURE_GEN_Q: - case GL_TEXTURE_GEN_R: - case GL_TEXTURE_GEN_S: - case GL_TEXTURE_GEN_T: - /* Picked up in r200UpdateTextureState. - */ - rmesa->recheck_texgen[ctx->Texture.CurrentUnit] = GL_TRUE; - break; - - case GL_COLOR_SUM_EXT: - r200UpdateSpecular ( ctx ); - break; - - case GL_VERTEX_PROGRAM_ARB: - if (!state) { - GLuint i; - rmesa->curr_vp_hw = NULL; - R200_STATECHANGE( rmesa, vap ); - rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] &= ~R200_VAP_PROG_VTX_SHADER_ENABLE; - /* mark all tcl atoms (tcl vector state got overwritten) dirty - not sure about tcl scalar state - we need at least grd - with vert progs too. - ucp looks like it doesn't get overwritten (may even work - with vp for pos-invariant progs if we're lucky) */ - R200_STATECHANGE( rmesa, mtl[0] ); - R200_STATECHANGE( rmesa, mtl[1] ); - R200_STATECHANGE( rmesa, fog ); - R200_STATECHANGE( rmesa, glt ); - R200_STATECHANGE( rmesa, eye ); - for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++) { - R200_STATECHANGE( rmesa, mat[i] ); - } - for (i = 0 ; i < 8; i++) { - R200_STATECHANGE( rmesa, lit[i] ); - } - R200_STATECHANGE( rmesa, tcl ); - for (i = 0; i <= ctx->Const.MaxClipPlanes; i++) { - if (ctx->Transform.ClipPlanesEnabled & (1 << i)) { - rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= (R200_UCP_ENABLE_0 << i); - } -/* else { - rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~(R200_UCP_ENABLE_0 << i); - }*/ - } - /* ugly. Need to call everything which might change compsel. */ - r200UpdateSpecular( ctx ); -#if 0 - /* shouldn't be necessary, as it's picked up anyway in r200ValidateState (_NEW_PROGRAM), - but without it doom3 locks up at always the same places. Why? */ - /* FIXME: This can (and should) be replaced by a call to the TCL_STATE_FLUSH reg before - accessing VAP_SE_VAP_CNTL. Requires drm changes (done). Remove after some time... */ - r200UpdateTextureState( ctx ); - /* if we call r200UpdateTextureState we need the code below because we are calling it with - non-current derived enabled values which may revert the state atoms for frag progs even when - they already got disabled... ugh - Should really figure out why we need to call r200UpdateTextureState in the first place */ - GLuint unit; - for (unit = 0; unit < R200_MAX_TEXTURE_UNITS; unit++) { - R200_STATECHANGE( rmesa, pix[unit] ); - R200_STATECHANGE( rmesa, tex[unit] ); - rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] &= - ~(R200_TXFORMAT_ST_ROUTE_MASK | R200_TXFORMAT_LOOKUP_DISABLE); - rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] |= unit << R200_TXFORMAT_ST_ROUTE_SHIFT; - /* need to guard this with drmSupportsFragmentShader? Should never get here if - we don't announce ATI_fs, right? */ - rmesa->hw.tex[unit].cmd[TEX_PP_TXMULTI_CTL] = 0; - } - R200_STATECHANGE( rmesa, cst ); - R200_STATECHANGE( rmesa, tf ); - rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0; -#endif - } - else { - /* picked up later */ - } - /* call functions which change hw state based on ARB_vp enabled or not. */ - r200PointParameter( ctx, GL_POINT_DISTANCE_ATTENUATION, NULL ); - r200Fogfv( ctx, GL_FOG_COORD_SRC, NULL ); - break; - - case GL_VERTEX_PROGRAM_POINT_SIZE_ARB: - r200PointParameter( ctx, GL_POINT_DISTANCE_ATTENUATION, NULL ); - break; - - case GL_FRAGMENT_SHADER_ATI: - if ( !state ) { - /* restore normal tex env colors and make sure tex env combine will get updated - mark env atoms dirty (as their data was overwritten by afs even - if they didn't change) and restore tex coord routing */ - GLuint unit; - for (unit = 0; unit < R200_MAX_TEXTURE_UNITS; unit++) { - R200_STATECHANGE( rmesa, pix[unit] ); - R200_STATECHANGE( rmesa, tex[unit] ); - rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] &= - ~(R200_TXFORMAT_ST_ROUTE_MASK | R200_TXFORMAT_LOOKUP_DISABLE); - rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] |= unit << R200_TXFORMAT_ST_ROUTE_SHIFT; - rmesa->hw.tex[unit].cmd[TEX_PP_TXMULTI_CTL] = 0; - } - R200_STATECHANGE( rmesa, cst ); - R200_STATECHANGE( rmesa, tf ); - rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0; - } - else { - /* need to mark this dirty as pix/tf atoms have overwritten the data - even if the data in the atoms didn't change */ - R200_STATECHANGE( rmesa, atf ); - R200_STATECHANGE( rmesa, afs[1] ); - /* everything else picked up in r200UpdateTextureState hopefully */ - } - break; - default: - return; - } -} - - -void r200LightingSpaceChange( struct gl_context *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLboolean tmp; - - if (R200_DEBUG & RADEON_STATE) - fprintf(stderr, "%s %d BEFORE %x\n", __func__, ctx->_NeedEyeCoords, - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0]); - - if (ctx->_NeedEyeCoords) - tmp = ctx->Transform.RescaleNormals; - else - tmp = !ctx->Transform.RescaleNormals; - - R200_STATECHANGE( rmesa, tcl ); - if ( tmp ) { - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] |= R200_RESCALE_NORMALS; - } else { - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] &= ~R200_RESCALE_NORMALS; - } - - if (R200_DEBUG & RADEON_STATE) - fprintf(stderr, "%s %d AFTER %x\n", __func__, ctx->_NeedEyeCoords, - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0]); -} - -/* ============================================================= - * Deferred state management - matrices, textures, other? - */ - - - - -static void upload_matrix( r200ContextPtr rmesa, GLfloat *src, int idx ) -{ - float *dest = ((float *)R200_DB_STATE( mat[idx] ))+MAT_ELT_0; - int i; - - - for (i = 0 ; i < 4 ; i++) { - *dest++ = src[i]; - *dest++ = src[i+4]; - *dest++ = src[i+8]; - *dest++ = src[i+12]; - } - - R200_DB_STATECHANGE( rmesa, &rmesa->hw.mat[idx] ); -} - -static void upload_matrix_t( r200ContextPtr rmesa, const GLfloat *src, int idx ) -{ - float *dest = ((float *)R200_DB_STATE( mat[idx] ))+MAT_ELT_0; - memcpy(dest, src, 16*sizeof(float)); - R200_DB_STATECHANGE( rmesa, &rmesa->hw.mat[idx] ); -} - - -static void update_texturematrix( struct gl_context *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT( ctx ); - GLuint tpc = rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0]; - GLuint compsel = rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL]; - int unit; - - if (R200_DEBUG & RADEON_STATE) - fprintf(stderr, "%s before COMPSEL: %x\n", __func__, - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL]); - - rmesa->TexMatEnabled = 0; - rmesa->TexMatCompSel = 0; - - for (unit = 0 ; unit < ctx->Const.MaxTextureUnits; unit++) { - if (!ctx->Texture.Unit[unit]._Current) - continue; - - if (ctx->TextureMatrixStack[unit].Top->type != MATRIX_IDENTITY) { - rmesa->TexMatEnabled |= (R200_TEXGEN_TEXMAT_0_ENABLE| - R200_TEXMAT_0_ENABLE) << unit; - - rmesa->TexMatCompSel |= R200_OUTPUT_TEX_0 << unit; - - if (rmesa->TexGenEnabled & (R200_TEXMAT_0_ENABLE << unit)) { - /* Need to preconcatenate any active texgen - * obj/eyeplane matrices: - */ - _math_matrix_mul_matrix( &rmesa->tmpmat, - ctx->TextureMatrixStack[unit].Top, - &rmesa->TexGenMatrix[unit] ); - upload_matrix( rmesa, rmesa->tmpmat.m, R200_MTX_TEX0+unit ); - } - else { - upload_matrix( rmesa, ctx->TextureMatrixStack[unit].Top->m, - R200_MTX_TEX0+unit ); - } - } - else if (rmesa->TexGenEnabled & (R200_TEXMAT_0_ENABLE << unit)) { - upload_matrix( rmesa, rmesa->TexGenMatrix[unit].m, - R200_MTX_TEX0+unit ); - } - } - - tpc = (rmesa->TexMatEnabled | rmesa->TexGenEnabled); - if (tpc != rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0]) { - R200_STATECHANGE(rmesa, tcg); - rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = tpc; - } - - compsel &= ~R200_OUTPUT_TEX_MASK; - compsel |= rmesa->TexMatCompSel | rmesa->TexGenCompSel; - if (compsel != rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL]) { - R200_STATECHANGE(rmesa, vtx); - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = compsel; - } -} - -GLboolean r200ValidateBuffers(struct gl_context *ctx) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - struct radeon_renderbuffer *rrb; - struct radeon_dma_bo *dma_bo; - int i, ret; - - if (RADEON_DEBUG & RADEON_IOCTL) - fprintf(stderr, "%s\n", __func__); - radeon_cs_space_reset_bos(rmesa->radeon.cmdbuf.cs); - - rrb = radeon_get_colorbuffer(&rmesa->radeon); - /* color buffer */ - if (rrb && rrb->bo) { - radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, rrb->bo, - 0, RADEON_GEM_DOMAIN_VRAM); - } - - /* depth buffer */ - rrb = radeon_get_depthbuffer(&rmesa->radeon); - /* color buffer */ - if (rrb && rrb->bo) { - radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, rrb->bo, - 0, RADEON_GEM_DOMAIN_VRAM); - } - - for (i = 0; i < ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits; ++i) { - radeonTexObj *t; - - if (!ctx->Texture.Unit[i]._Current) - continue; - - t = radeon_tex_obj(ctx->Texture.Unit[i]._Current); - if (t->image_override && t->bo) - radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, t->bo, - RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); - else if (t->mt->bo) - radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs, t->mt->bo, - RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0); - } - - dma_bo = first_elem(&rmesa->radeon.dma.reserved); - { - ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs, dma_bo->bo, RADEON_GEM_DOMAIN_GTT, 0); - if (ret) - return GL_FALSE; - } - return GL_TRUE; -} - -GLboolean r200ValidateState( struct gl_context *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint new_state = rmesa->radeon.NewGLState; - - if (new_state & _NEW_BUFFERS) { - _mesa_update_framebuffer(ctx, ctx->ReadBuffer, ctx->DrawBuffer); - /* this updates the DrawBuffer's Width/Height if it's a FBO */ - _mesa_update_draw_buffer_bounds(ctx, ctx->DrawBuffer); - - R200_STATECHANGE(rmesa, ctx); - } - - if (new_state & (_NEW_TEXTURE | _NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS)) { - r200UpdateTextureState( ctx ); - new_state |= rmesa->radeon.NewGLState; /* may add TEXTURE_MATRIX */ - r200UpdateLocalViewer( ctx ); - } - - /* we need to do a space check here */ - if (!r200ValidateBuffers(ctx)) - return GL_FALSE; - -/* FIXME: don't really need most of these when vertex progs are enabled */ - - /* Need an event driven matrix update? - */ - if (new_state & (_NEW_MODELVIEW|_NEW_PROJECTION)) - upload_matrix( rmesa, ctx->_ModelProjectMatrix.m, R200_MTX_MVP ); - - /* Need these for lighting (shouldn't upload otherwise) - */ - if (new_state & (_NEW_MODELVIEW)) { - upload_matrix( rmesa, ctx->ModelviewMatrixStack.Top->m, R200_MTX_MV ); - upload_matrix_t( rmesa, ctx->ModelviewMatrixStack.Top->inv, R200_MTX_IMV ); - } - - /* Does this need to be triggered on eg. modelview for - * texgen-derived objplane/eyeplane matrices? - */ - if (new_state & (_NEW_TEXTURE|_NEW_TEXTURE_MATRIX)) { - update_texturematrix( ctx ); - } - - if (new_state & (_NEW_LIGHT|_NEW_MODELVIEW|_MESA_NEW_NEED_EYE_COORDS)) { - update_light( ctx ); - } - - /* emit all active clip planes if projection matrix changes. - */ - if (new_state & (_NEW_PROJECTION)) { - if (ctx->Transform.ClipPlanesEnabled) - r200UpdateClipPlanes( ctx ); - } - - if (new_state & (_NEW_PROGRAM| - _NEW_PROGRAM_CONSTANTS | - /* need to test for pretty much anything due to possible parameter bindings */ - _NEW_MODELVIEW|_NEW_PROJECTION|_NEW_TRANSFORM| - _NEW_LIGHT|_NEW_TEXTURE|_NEW_TEXTURE_MATRIX| - _NEW_FOG|_NEW_POINT|_NEW_TRACK_MATRIX)) { - if (_mesa_arb_vertex_program_enabled(ctx)) { - r200SetupVertexProg( ctx ); - } - else TCL_FALLBACK(ctx, R200_TCL_FALLBACK_VERTEX_PROGRAM, 0); - } - - rmesa->radeon.NewGLState = 0; - return GL_TRUE; -} - - -static void r200InvalidateState(struct gl_context *ctx) -{ - GLuint new_state = ctx->NewState; - - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - if (new_state & (_NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT)) - _mesa_update_draw_buffer_bounds(ctx, ctx->DrawBuffer); - - _swrast_InvalidateState( ctx, new_state ); - _swsetup_InvalidateState( ctx, new_state ); - _tnl_InvalidateState( ctx, new_state ); - R200_CONTEXT(ctx)->radeon.NewGLState |= new_state; - - if (new_state & _NEW_PROGRAM) - rmesa->curr_vp_hw = NULL; -} - -/* A hack. The r200 can actually cope just fine with materials - * between begin/ends, so fix this. - * Should map to inputs just like the generic vertex arrays for vertex progs. - * In theory there could still be too many and we'd still need a fallback. - */ -static GLboolean check_material( struct gl_context *ctx ) -{ - TNLcontext *tnl = TNL_CONTEXT(ctx); - GLint i; - - for (i = _TNL_ATTRIB_MAT_FRONT_AMBIENT; - i < _TNL_ATTRIB_MAT_BACK_INDEXES; - i++) - if (tnl->vb.AttribPtr[i] && - tnl->vb.AttribPtr[i]->stride) - return GL_TRUE; - - return GL_FALSE; -} - -static void r200WrapRunPipeline( struct gl_context *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLboolean has_material; - - if (0) - fprintf(stderr, "%s, newstate: %x\n", __func__, rmesa->radeon.NewGLState); - - /* Validate state: - */ - if (rmesa->radeon.NewGLState) - if (!r200ValidateState( ctx )) - FALLBACK(rmesa, RADEON_FALLBACK_TEXTURE, GL_TRUE); - - has_material = !_mesa_arb_vertex_program_enabled(ctx) && - ctx->Light.Enabled && check_material( ctx ); - - if (has_material) { - TCL_FALLBACK( ctx, R200_TCL_FALLBACK_MATERIAL, GL_TRUE ); - } - - /* Run the pipeline. - */ - _tnl_run_pipeline( ctx ); - - if (has_material) { - TCL_FALLBACK( ctx, R200_TCL_FALLBACK_MATERIAL, GL_FALSE ); - } -} - - -static void r200PolygonStipple( struct gl_context *ctx, const GLubyte *mask ) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - GLint i; - - radeon_firevertices(&r200->radeon); - - radeon_print(RADEON_STATE, RADEON_TRACE, - "%s(%p) first 32 bits are %x.\n", - __func__, - ctx, - *(uint32_t*)mask); - - R200_STATECHANGE(r200, stp); - - /* Must flip pattern upside down. - */ - for ( i = 31 ; i >= 0; i--) { - r200->hw.stp.cmd[3 + i] = ((GLuint *) mask)[i]; - } -} -/* Initialize the driver's state functions. - */ -void r200InitStateFuncs( radeonContextPtr radeon, struct dd_function_table *functions ) -{ - functions->UpdateState = r200InvalidateState; - functions->LightingSpaceChange = r200LightingSpaceChange; - - functions->DrawBuffer = radeonDrawBuffer; - functions->ReadBuffer = radeonReadBuffer; - - functions->CopyPixels = _mesa_meta_CopyPixels; - functions->DrawPixels = _mesa_meta_DrawPixels; - functions->ReadPixels = radeonReadPixels; - - functions->AlphaFunc = r200AlphaFunc; - functions->BlendColor = r200BlendColor; - functions->BlendEquationSeparate = r200BlendEquationSeparate; - functions->BlendFuncSeparate = r200BlendFuncSeparate; - functions->ClipPlane = r200ClipPlane; - functions->ColorMask = r200ColorMask; - functions->CullFace = r200CullFace; - functions->DepthFunc = r200DepthFunc; - functions->DepthMask = r200DepthMask; - functions->DepthRange = r200DepthRange; - functions->Enable = r200Enable; - functions->Fogfv = r200Fogfv; - functions->FrontFace = r200FrontFace; - functions->LightModelfv = r200LightModelfv; - functions->Lightfv = r200Lightfv; - functions->LineStipple = r200LineStipple; - functions->LineWidth = r200LineWidth; - functions->LogicOpcode = r200LogicOpCode; - functions->PolygonMode = r200PolygonMode; - functions->PolygonOffset = r200PolygonOffset; - functions->PolygonStipple = r200PolygonStipple; - functions->PointParameterfv = r200PointParameter; - functions->PointSize = r200PointSize; - functions->RenderMode = r200RenderMode; - functions->Scissor = radeonScissor; - functions->ShadeModel = r200ShadeModel; - functions->StencilFuncSeparate = r200StencilFuncSeparate; - functions->StencilMaskSeparate = r200StencilMaskSeparate; - functions->StencilOpSeparate = r200StencilOpSeparate; - functions->Viewport = r200Viewport; -} - - -void r200InitTnlFuncs( struct gl_context *ctx ) -{ - TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange = r200UpdateMaterial; - TNL_CONTEXT(ctx)->Driver.RunPipeline = r200WrapRunPipeline; -} diff --git a/src/mesa/drivers/dri/r200/r200_state.h b/src/mesa/drivers/dri/r200/r200_state.h deleted file mode 100644 index 3b719b52a73..00000000000 --- a/src/mesa/drivers/dri/r200/r200_state.h +++ /dev/null @@ -1,63 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell <keithw@vmware.com> - */ - -#ifndef __R200_STATE_H__ -#define __R200_STATE_H__ - -#include "r200_context.h" - -extern void r200InitState( r200ContextPtr rmesa ); -extern void r200InitStateFuncs( radeonContextPtr radeon, struct dd_function_table *functions ); -extern void r200InitTnlFuncs( struct gl_context *ctx ); - -extern void r200UpdateMaterial( struct gl_context *ctx ); - -extern void r200UpdateWindow( struct gl_context *ctx ); -extern void r200UpdateDrawBuffer(struct gl_context *ctx); - -extern GLboolean r200ValidateBuffers(struct gl_context *ctx); -extern GLboolean r200ValidateState( struct gl_context *ctx ); - -extern void r200_vtbl_update_scissor( struct gl_context *ctx ); - -extern void r200Fallback( struct gl_context *ctx, GLuint bit, GLboolean mode ); -#define FALLBACK( rmesa, bit, mode ) do { \ - if ( 0 ) fprintf( stderr, "FALLBACK in %s: #%d=%d\n", \ - __func__, bit, mode ); \ - r200Fallback( &rmesa->radeon.glCtx, bit, mode ); \ -} while (0) - -extern void r200LightingSpaceChange( struct gl_context *ctx ); - -#endif diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c deleted file mode 100644 index 0f19ea7e69e..00000000000 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ /dev/null @@ -1,1302 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - -/* - * Authors: - * Keith Whitwell <keithw@vmware.com> - */ - -#include "main/errors.h" -#include "main/glheader.h" - -#include "main/enums.h" -#include "main/api_arrayelt.h" -#include "main/state.h" - -#include "swrast/swrast.h" -#include "vbo/vbo.h" -#include "tnl/t_pipeline.h" -#include "swrast_setup/swrast_setup.h" - -#include "radeon_common.h" -#include "radeon_mipmap_tree.h" -#include "r200_context.h" -#include "r200_ioctl.h" -#include "r200_state.h" -#include "radeon_queryobj.h" - -#include "util/driconf.h" - -/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in - * 1.3 cmdbuffers allow all previous state to be updated as well as - * the tcl scalar and vector areas. - */ -static struct { - int start; - int len; - const char *name; -} packet[RADEON_MAX_STATE_PACKETS] = { - {RADEON_PP_MISC, 7, "RADEON_PP_MISC"}, - {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"}, - {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"}, - {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"}, - {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"}, - {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"}, - {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"}, - {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"}, - {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"}, - {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"}, - {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"}, - {RADEON_RE_MISC, 1, "RADEON_RE_MISC"}, - {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"}, - {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"}, - {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"}, - {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"}, - {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"}, - {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"}, - {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"}, - {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"}, - {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17, - "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"}, - {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"}, - {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"}, - {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"}, - {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"}, - {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"}, - {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"}, - {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"}, - {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"}, - {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"}, - {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"}, - {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"}, - {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"}, - {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"}, - {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"}, - {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"}, - {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"}, - {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"}, - {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"}, - {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"}, - {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"}, - {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"}, - {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"}, - {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"}, - {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"}, - {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"}, - {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"}, - {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"}, - {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"}, - {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, - "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"}, - {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"}, - {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"}, - {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"}, - {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"}, - {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"}, - {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"}, - {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"}, - {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"}, - {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"}, - {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"}, - {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, - "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"}, - {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */ - {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */ - {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"}, - {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"}, - {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"}, - {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"}, - {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"}, - {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"}, - {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"}, - {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"}, - {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"}, - {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"}, - {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"}, - {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"}, - {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"}, - {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"}, - {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"}, - {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, - {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, - {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, - {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, - {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, - {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, - {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, - {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */ - {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"}, - {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, - {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, - {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, - {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, - {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, - {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, - {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, - {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"}, -}; - -/* ============================================================= - * State initialization - */ -static int cmdpkt( r200ContextPtr rmesa, int id ) -{ - return CP_PACKET0(packet[id].start, packet[id].len - 1); -} - -static int cmdvec( int offset, int stride, int count ) -{ - drm_radeon_cmd_header_t h; - h.i = 0; - h.vectors.cmd_type = RADEON_CMD_VECTORS; - h.vectors.offset = offset; - h.vectors.stride = stride; - h.vectors.count = count; - return h.i; -} - -/* warning: the count here is divided by 4 compared to other cmds - (so it doesn't exceed the char size)! */ -static int cmdveclinear( int offset, int count ) -{ - drm_radeon_cmd_header_t h; - h.i = 0; - h.veclinear.cmd_type = RADEON_CMD_VECLINEAR; - h.veclinear.addr_lo = offset & 0xff; - h.veclinear.addr_hi = (offset & 0xff00) >> 8; - h.veclinear.count = count; - return h.i; -} - -static int cmdscl( int offset, int stride, int count ) -{ - drm_radeon_cmd_header_t h; - h.i = 0; - h.scalars.cmd_type = RADEON_CMD_SCALARS; - h.scalars.offset = offset; - h.scalars.stride = stride; - h.scalars.count = count; - return h.i; -} - -static int cmdscl2( int offset, int stride, int count ) -{ - drm_radeon_cmd_header_t h; - h.i = 0; - h.scalars.cmd_type = RADEON_CMD_SCALARS2; - h.scalars.offset = offset - 0x100; - h.scalars.stride = stride; - h.scalars.count = count; - return h.i; -} - -/** - * Check functions are used to check if state is active. - * If it is active check function returns maximum emit size. - */ -#define CHECK( NM, FLAG, ADD ) \ -static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom) \ -{ \ - r200ContextPtr rmesa = R200_CONTEXT(ctx); \ - (void) rmesa; \ - return (FLAG) ? atom->cmd_size + (ADD) : 0; \ -} - -#define TCL_CHECK( NM, FLAG, ADD ) \ -static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom) \ -{ \ - r200ContextPtr rmesa = R200_CONTEXT(ctx); \ - return (!rmesa->radeon.TclFallback && !_mesa_arb_vertex_program_enabled(ctx) && (FLAG)) ? atom->cmd_size + (ADD) : 0; \ -} - -#define TCL_OR_VP_CHECK( NM, FLAG, ADD ) \ -static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom ) \ -{ \ - r200ContextPtr rmesa = R200_CONTEXT(ctx); \ - return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \ -} - -#define VP_CHECK( NM, FLAG, ADD ) \ -static int check_##NM( struct gl_context *ctx, struct radeon_state_atom *atom ) \ -{ \ - r200ContextPtr rmesa = R200_CONTEXT(ctx); \ - (void) atom; \ - return (!rmesa->radeon.TclFallback && _mesa_arb_vertex_program_enabled(ctx) && (FLAG)) ? atom->cmd_size + (ADD) : 0; \ -} - -CHECK( always, GL_TRUE, 0 ) -CHECK( always_add4, GL_TRUE, 4 ) -CHECK( never, GL_FALSE, 0 ) -CHECK( tex_any, ctx->Texture._MaxEnabledTexImageUnit != -1, 0 ) -CHECK( tf, (ctx->Texture._MaxEnabledTexImageUnit != -1 && !_mesa_ati_fragment_shader_enabled(ctx)), 0 ); -CHECK( pix_zero, !_mesa_ati_fragment_shader_enabled(ctx), 0 ) -CHECK( texenv, (rmesa->state.envneeded & (1 << (atom->idx)) && !_mesa_ati_fragment_shader_enabled(ctx)), 0 ) -CHECK( afs_pass1, (_mesa_ati_fragment_shader_enabled(ctx) && (ctx->ATIFragmentShader.Current->NumPasses > 1)), 0 ) -CHECK( afs, _mesa_ati_fragment_shader_enabled(ctx), 0 ) -CHECK( tex_cube, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 3 + 3*5 - CUBE_STATE_SIZE ) -CHECK( tex_cube_cs, rmesa->state.texture.unit[atom->idx].unitneeded & TEXTURE_CUBE_BIT, 2 + 4*5 - CUBE_STATE_SIZE ) -TCL_CHECK( tcl_fog_add4, ctx->Fog.Enabled, 4 ) -TCL_CHECK( tcl, GL_TRUE, 0 ) -TCL_CHECK( tcl_add8, GL_TRUE, 8 ) -TCL_CHECK( tcl_add4, GL_TRUE, 4 ) -TCL_CHECK( tcl_tex_add4, rmesa->state.texture.unit[atom->idx].unitneeded, 4 ) -TCL_CHECK( tcl_lighting_add4, ctx->Light.Enabled, 4 ) -TCL_CHECK( tcl_lighting_add6, ctx->Light.Enabled, 6 ) -TCL_CHECK( tcl_light_add6, ctx->Light.Enabled && ctx->Light.Light[atom->idx].Enabled, 6 ) -TCL_OR_VP_CHECK( tcl_ucp_add4, (ctx->Transform.ClipPlanesEnabled & (1 << (atom->idx))), 4 ) -TCL_OR_VP_CHECK( tcl_or_vp, GL_TRUE, 0 ) -TCL_OR_VP_CHECK( tcl_or_vp_add2, GL_TRUE, 2 ) -VP_CHECK( tcl_vp, GL_TRUE, 0 ) -VP_CHECK( tcl_vp_add4, GL_TRUE, 4 ) -VP_CHECK( tcl_vp_size_add4, ctx->VertexProgram.Current->arb.NumNativeInstructions > 64, 4 ) -VP_CHECK( tcl_vpp_size_add4, ctx->VertexProgram.Current->arb.NumNativeParameters > 96, 4 ) - -#define OUT_VEC(hdr, data) do { \ - drm_radeon_cmd_header_t h; \ - h.i = hdr; \ - OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \ - OUT_BATCH(0); \ - OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \ - OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \ - OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \ - OUT_BATCH_TABLE((data), h.vectors.count); \ - } while(0) - -#define OUT_VECLINEAR(hdr, data) do { \ - drm_radeon_cmd_header_t h; \ - uint32_t _start, _sz; \ - h.i = hdr; \ - _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \ - _sz = h.veclinear.count * 4; \ - if (_sz) { \ - BEGIN_BATCH(dwords); \ - OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \ - OUT_BATCH(0); \ - OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \ - OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \ - OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1)); \ - OUT_BATCH_TABLE((data), _sz); \ - END_BATCH(); \ - } \ - } while(0) - -#define OUT_SCL(hdr, data) do { \ - drm_radeon_cmd_header_t h; \ - h.i = hdr; \ - OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \ - OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \ - OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \ - OUT_BATCH_TABLE((data), h.scalars.count); \ - } while(0) - -#define OUT_SCL2(hdr, data) do { \ - drm_radeon_cmd_header_t h; \ - h.i = hdr; \ - OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \ - OUT_BATCH((h.scalars.offset + 0x100) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \ - OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \ - OUT_BATCH_TABLE((data), h.scalars.count); \ - } while(0) -static int check_rrb(struct gl_context *ctx, struct radeon_state_atom *atom) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - struct radeon_renderbuffer *rrb; - rrb = radeon_get_colorbuffer(&r200->radeon); - if (!rrb || !rrb->bo) - return 0; - return atom->cmd_size; -} - -static int check_polygon_stipple(struct gl_context *ctx, - struct radeon_state_atom *atom) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - if (r200->hw.set.cmd[SET_RE_CNTL] & R200_STIPPLE_ENABLE) - return atom->cmd_size; - return 0; -} - -static void mtl_emit(struct gl_context *ctx, struct radeon_state_atom *atom) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - BATCH_LOCALS(&r200->radeon); - uint32_t dwords = atom->check(ctx, atom); - - BEGIN_BATCH(dwords); - OUT_VEC(atom->cmd[MTL_CMD_0], (atom->cmd+1)); - OUT_SCL2(atom->cmd[MTL_CMD_1], (atom->cmd + 18)); - END_BATCH(); -} - -static void lit_emit(struct gl_context *ctx, struct radeon_state_atom *atom) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - BATCH_LOCALS(&r200->radeon); - uint32_t dwords = atom->check(ctx, atom); - - BEGIN_BATCH(dwords); - OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1); - OUT_SCL(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1); - END_BATCH(); -} - -static void ptp_emit(struct gl_context *ctx, struct radeon_state_atom *atom) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - BATCH_LOCALS(&r200->radeon); - uint32_t dwords = atom->check(ctx, atom); - - BEGIN_BATCH(dwords); - OUT_VEC(atom->cmd[PTP_CMD_0], atom->cmd+1); - OUT_VEC(atom->cmd[PTP_CMD_1], atom->cmd+PTP_CMD_1+1); - END_BATCH(); -} - -static void veclinear_emit(struct gl_context *ctx, struct radeon_state_atom *atom) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - BATCH_LOCALS(&r200->radeon); - uint32_t dwords = atom->check(ctx, atom); - - OUT_VECLINEAR(atom->cmd[0], atom->cmd+1); -} - -static void scl_emit(struct gl_context *ctx, struct radeon_state_atom *atom) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - BATCH_LOCALS(&r200->radeon); - uint32_t dwords = atom->check(ctx, atom); - - BEGIN_BATCH(dwords); - OUT_SCL(atom->cmd[0], atom->cmd+1); - END_BATCH(); -} - - -static void vec_emit(struct gl_context *ctx, struct radeon_state_atom *atom) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - BATCH_LOCALS(&r200->radeon); - uint32_t dwords = atom->check(ctx, atom); - - BEGIN_BATCH(dwords); - OUT_VEC(atom->cmd[0], atom->cmd+1); - END_BATCH(); -} - -static int check_always_ctx( struct gl_context *ctx, struct radeon_state_atom *atom) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - struct radeon_renderbuffer *rrb, *drb; - uint32_t dwords; - - rrb = radeon_get_colorbuffer(&r200->radeon); - if (!rrb || !rrb->bo) { - return 0; - } - - drb = radeon_get_depthbuffer(&r200->radeon); - - dwords = 10; - if (drb) - dwords += 6; - if (rrb) - dwords += 8; - if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) - dwords += 4; - - - return dwords; -} - -static void ctx_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - BATCH_LOCALS(&r200->radeon); - struct radeon_renderbuffer *rrb, *drb; - uint32_t cbpitch = 0; - uint32_t zbpitch = 0; - uint32_t dwords = atom->check(ctx, atom); - uint32_t depth_fmt; - - rrb = radeon_get_colorbuffer(&r200->radeon); - if (!rrb || !rrb->bo) { - return; - } - - atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10); - if (rrb->cpp == 4) - atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888; - else switch (rrb->base.Base.Format) { - case MESA_FORMAT_B5G6R5_UNORM: - case MESA_FORMAT_R5G6B5_UNORM: - atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565; - break; - case MESA_FORMAT_B4G4R4A4_UNORM: - case MESA_FORMAT_A4R4G4B4_UNORM: - atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444; - break; - case MESA_FORMAT_B5G5R5A1_UNORM: - case MESA_FORMAT_A1R5G5B5_UNORM: - atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555; - break; - default: - _mesa_problem(ctx, "Unexpected format in ctx_emit_cs"); - } - - cbpitch = (rrb->pitch / rrb->cpp); - if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) - cbpitch |= R200_COLOR_TILE_ENABLE; - if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE) - cbpitch |= R200_COLOR_MICROTILE_ENABLE; - - - drb = radeon_get_depthbuffer(&r200->radeon); - if (drb) { - zbpitch = (drb->pitch / drb->cpp); - if (drb->cpp == 4) - depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; - else - depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; - atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK; - atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt; - } - - /* output the first 7 bytes of context */ - BEGIN_BATCH(dwords); - - /* In the CS case we need to split this up */ - OUT_BATCH(CP_PACKET0(packet[0].start, 3)); - OUT_BATCH_TABLE((atom->cmd + 1), 4); - - if (drb) { - OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0)); - OUT_BATCH_RELOC(drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0); - - OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0)); - OUT_BATCH(zbpitch); - } - - OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0)); - OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]); - OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1)); - OUT_BATCH(atom->cmd[CTX_PP_CNTL]); - OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]); - - - if (rrb) { - OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0)); - OUT_BATCH_RELOC(rrb->bo, rrb->draw_offset, 0, RADEON_GEM_DOMAIN_VRAM, 0); - - OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); - OUT_BATCH_RELOC(rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0); - } - - if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) { - OUT_BATCH_TABLE((atom->cmd + 14), 4); - } - - END_BATCH(); -} - -static int get_tex_mm_size(struct gl_context* ctx, struct radeon_state_atom *atom) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - uint32_t dwords = atom->cmd_size + 2; - int hastexture = 1; - int i = atom->idx; - radeonTexObj *t = r200->state.texture.unit[i].texobj; - if (!t) - hastexture = 0; - else { - if (!t->mt && !t->bo) - hastexture = 0; - } - - if (!hastexture) - dwords -= 4; - return dwords; -} - -static int check_tex_pair_mm(struct gl_context* ctx, struct radeon_state_atom *atom) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - /** XOR is bit flip operation so use it for finding pair */ - if (!(r200->state.texture.unit[atom->idx].unitneeded | r200->state.texture.unit[atom->idx ^ 1].unitneeded)) - return 0; - - return get_tex_mm_size(ctx, atom); -} - -static int check_tex_mm(struct gl_context* ctx, struct radeon_state_atom *atom) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - if (!(r200->state.texture.unit[atom->idx].unitneeded)) - return 0; - - return get_tex_mm_size(ctx, atom); -} - - -static void tex_emit_mm(struct gl_context *ctx, struct radeon_state_atom *atom) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - BATCH_LOCALS(&r200->radeon); - uint32_t dwords = atom->check(ctx, atom); - int i = atom->idx; - radeonTexObj *t = r200->state.texture.unit[i].texobj; - - if (!r200->state.texture.unit[i].unitneeded && !(dwords <= atom->cmd_size)) - dwords -= 4; - BEGIN_BATCH(dwords); - - OUT_BATCH(CP_PACKET0(R200_PP_TXFILTER_0 + (32 * i), 7)); - OUT_BATCH_TABLE((atom->cmd + 1), 8); - - if (dwords > atom->cmd_size) { - OUT_BATCH(CP_PACKET0(R200_PP_TXOFFSET_0 + (24 * i), 0)); - if (t->mt && !t->image_override) { - OUT_BATCH_RELOC(t->mt->bo, t->tile_bits, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - } else { - if (t->bo) - OUT_BATCH_RELOC(t->bo, t->tile_bits, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - } - } - END_BATCH(); -} - -static void cube_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) -{ - r200ContextPtr r200 = R200_CONTEXT(ctx); - BATCH_LOCALS(&r200->radeon); - uint32_t dwords = atom->check(ctx, atom); - int i = atom->idx, j; - radeonTexObj *t = r200->state.texture.unit[i].texobj; - radeon_mipmap_level *lvl; - if (!(t && !t->image_override)) - dwords = 2; - - BEGIN_BATCH(dwords); - OUT_BATCH_TABLE(atom->cmd, 2); - - if (t && !t->image_override) { - lvl = &t->mt->levels[0]; - for (j = 1; j <= 5; j++) { - OUT_BATCH(CP_PACKET0(R200_PP_CUBIC_OFFSET_F1_0 + (24*i) + (4 * (j-1)), 0)); - OUT_BATCH_RELOC(t->mt->bo, lvl->faces[j].offset, - RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); - } - } - END_BATCH(); -} - -/* Initialize the context's hardware state. - */ -void r200InitState( r200ContextPtr rmesa ) -{ - struct gl_context *ctx = &rmesa->radeon.glCtx; - GLuint i; - - rmesa->radeon.Fallback = 0; - - rmesa->radeon.hw.max_state_size = 0; - -#define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \ - do { \ - rmesa->hw.ATOM.cmd_size = SZ; \ - rmesa->hw.ATOM.cmd = (GLuint *) calloc(SZ, sizeof(int)); \ - rmesa->hw.ATOM.lastcmd = (GLuint *) calloc(SZ, sizeof(int)); \ - rmesa->hw.ATOM.name = NM; \ - rmesa->hw.ATOM.idx = IDX; \ - if (check_##CHK != check_never) { \ - rmesa->hw.ATOM.check = check_##CHK; \ - rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \ - } else { \ - rmesa->hw.ATOM.check = NULL; \ - } \ - rmesa->hw.ATOM.dirty = GL_FALSE; \ - } while (0) - - - /* Allocate state buffers: - */ - ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE_NEWDRM, "CTX/context", 0 ); - - rmesa->hw.ctx.emit = ctx_emit_cs; - rmesa->hw.ctx.check = check_always_ctx; - ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 ); - ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 ); - ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 ); - ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 ); - ALLOC_STATE( vtx, always, VTX_STATE_SIZE, "VTX/vertex", 0 ); - ALLOC_STATE( vap, always, VAP_STATE_SIZE, "VAP/vap", 0 ); - ALLOC_STATE( vte, always, VTE_STATE_SIZE, "VTE/vte", 0 ); - ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 ); - ALLOC_STATE( cst, always, CST_STATE_SIZE, "CST/constant", 0 ); - ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 ); - ALLOC_STATE( tf, tf, TF_STATE_SIZE, "TF/tfactor", 0 ); - { - int state_size = TEX_STATE_SIZE_NEWDRM; - if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) { - /* make sure texture units 0/1 are emitted pair-wise for r200 t0 hang workaround */ - ALLOC_STATE( tex[0], tex_pair_mm, state_size, "TEX/tex-0", 0 ); - ALLOC_STATE( tex[1], tex_pair_mm, state_size, "TEX/tex-1", 1 ); - ALLOC_STATE( tam, tex_any, TAM_STATE_SIZE, "TAM/tam", 0 ); - } - else { - ALLOC_STATE( tex[0], tex_mm, state_size, "TEX/tex-0", 0 ); - ALLOC_STATE( tex[1], tex_mm, state_size, "TEX/tex-1", 1 ); - ALLOC_STATE( tam, never, TAM_STATE_SIZE, "TAM/tam", 0 ); - } - ALLOC_STATE( tex[2], tex_mm, state_size, "TEX/tex-2", 2 ); - ALLOC_STATE( tex[3], tex_mm, state_size, "TEX/tex-3", 3 ); - ALLOC_STATE( tex[4], tex_mm, state_size, "TEX/tex-4", 4 ); - ALLOC_STATE( tex[5], tex_mm, state_size, "TEX/tex-5", 5 ); - ALLOC_STATE( atf, afs, ATF_STATE_SIZE, "ATF/tfactor", 0 ); - ALLOC_STATE( afs[0], afs_pass1, AFS_STATE_SIZE, "AFS/afsinst-0", 0 ); - ALLOC_STATE( afs[1], afs, AFS_STATE_SIZE, "AFS/afsinst-1", 1 ); - } - - ALLOC_STATE( stp, polygon_stipple, STP_STATE_SIZE, "STP/stp", 0 ); - - for (i = 0; i < 6; i++) - rmesa->hw.tex[i].emit = tex_emit_mm; - ALLOC_STATE( cube[0], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-0", 0 ); - ALLOC_STATE( cube[1], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-1", 1 ); - ALLOC_STATE( cube[2], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-2", 2 ); - ALLOC_STATE( cube[3], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-3", 3 ); - ALLOC_STATE( cube[4], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-4", 4 ); - ALLOC_STATE( cube[5], tex_cube, CUBE_STATE_SIZE, "CUBE/tex-5", 5 ); - for (i = 0; i < 6; i++) { - rmesa->hw.cube[i].emit = cube_emit_cs; - rmesa->hw.cube[i].check = check_tex_cube_cs; - } - - ALLOC_STATE( pvs, tcl_vp, PVS_STATE_SIZE, "PVS/pvscntl", 0 ); - ALLOC_STATE( vpi[0], tcl_vp_add4, VPI_STATE_SIZE, "VP/vertexprog-0", 0 ); - ALLOC_STATE( vpi[1], tcl_vp_size_add4, VPI_STATE_SIZE, "VP/vertexprog-1", 1 ); - ALLOC_STATE( vpp[0], tcl_vp_add4, VPP_STATE_SIZE, "VPP/vertexparam-0", 0 ); - ALLOC_STATE( vpp[1], tcl_vpp_size_add4, VPP_STATE_SIZE, "VPP/vertexparam-1", 1 ); - - /* FIXME: this atom has two commands, we need only one (ucp_vert_blend) for vp */ - ALLOC_STATE( tcl, tcl_or_vp, TCL_STATE_SIZE, "TCL/tcl", 0 ); - ALLOC_STATE( msl, tcl, MSL_STATE_SIZE, "MSL/matrix-select", 0 ); - ALLOC_STATE( tcg, tcl, TCG_STATE_SIZE, "TCG/texcoordgen", 0 ); - ALLOC_STATE( mtl[0], tcl_lighting_add6, MTL_STATE_SIZE, "MTL0/material0", 0 ); - ALLOC_STATE( mtl[1], tcl_lighting_add6, MTL_STATE_SIZE, "MTL1/material1", 1 ); - ALLOC_STATE( grd, tcl_or_vp_add2, GRD_STATE_SIZE, "GRD/guard-band", 0 ); - ALLOC_STATE( fog, tcl_fog_add4, FOG_STATE_SIZE, "FOG/fog", 0 ); - ALLOC_STATE( glt, tcl_lighting_add4, GLT_STATE_SIZE, "GLT/light-global", 0 ); - ALLOC_STATE( eye, tcl_lighting_add4, EYE_STATE_SIZE, "EYE/eye-vector", 0 ); - ALLOC_STATE( mat[R200_MTX_MV], tcl_add4, MAT_STATE_SIZE, "MAT/modelview", 0 ); - ALLOC_STATE( mat[R200_MTX_IMV], tcl_add4, MAT_STATE_SIZE, "MAT/it-modelview", 0 ); - ALLOC_STATE( mat[R200_MTX_MVP], tcl_add4, MAT_STATE_SIZE, "MAT/modelproject", 0 ); - ALLOC_STATE( mat[R200_MTX_TEX0], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat0", 0 ); - ALLOC_STATE( mat[R200_MTX_TEX1], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat1", 1 ); - ALLOC_STATE( mat[R200_MTX_TEX2], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat2", 2 ); - ALLOC_STATE( mat[R200_MTX_TEX3], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat3", 3 ); - ALLOC_STATE( mat[R200_MTX_TEX4], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat4", 4 ); - ALLOC_STATE( mat[R200_MTX_TEX5], tcl_tex_add4, MAT_STATE_SIZE, "MAT/texmat5", 5 ); - ALLOC_STATE( ucp[0], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-0", 0 ); - ALLOC_STATE( ucp[1], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-1", 1 ); - ALLOC_STATE( ucp[2], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-2", 2 ); - ALLOC_STATE( ucp[3], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-3", 3 ); - ALLOC_STATE( ucp[4], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-4", 4 ); - ALLOC_STATE( ucp[5], tcl_ucp_add4, UCP_STATE_SIZE, "UCP/userclip-5", 5 ); - ALLOC_STATE( lit[0], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-0", 0 ); - ALLOC_STATE( lit[1], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-1", 1 ); - ALLOC_STATE( lit[2], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-2", 2 ); - ALLOC_STATE( lit[3], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-3", 3 ); - ALLOC_STATE( lit[4], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-4", 4 ); - ALLOC_STATE( lit[5], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-5", 5 ); - ALLOC_STATE( lit[6], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-6", 6 ); - ALLOC_STATE( lit[7], tcl_light_add6, LIT_STATE_SIZE, "LIT/light-7", 7 ); - ALLOC_STATE( sci, rrb, SCI_STATE_SIZE, "SCI/scissor", 0 ); - ALLOC_STATE( pix[0], pix_zero, PIX_STATE_SIZE, "PIX/pixstage-0", 0 ); - ALLOC_STATE( pix[1], texenv, PIX_STATE_SIZE, "PIX/pixstage-1", 1 ); - ALLOC_STATE( pix[2], texenv, PIX_STATE_SIZE, "PIX/pixstage-2", 2 ); - ALLOC_STATE( pix[3], texenv, PIX_STATE_SIZE, "PIX/pixstage-3", 3 ); - ALLOC_STATE( pix[4], texenv, PIX_STATE_SIZE, "PIX/pixstage-4", 4 ); - ALLOC_STATE( pix[5], texenv, PIX_STATE_SIZE, "PIX/pixstage-5", 5 ); - ALLOC_STATE( prf, always, PRF_STATE_SIZE, "PRF/performance-tri", 0 ); - ALLOC_STATE( spr, always, SPR_STATE_SIZE, "SPR/pointsprite", 0 ); - ALLOC_STATE( ptp, tcl_add8, PTP_STATE_SIZE, "PTP/pointparams", 0 ); - - r200SetUpAtomList( rmesa ); - - /* Fill in the packet headers: - */ - rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC); - rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL); - rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH); - rmesa->hw.ctx.cmd[CTX_CMD_3] = cmdpkt(rmesa, R200_EMIT_RB3D_BLENDCOLOR); - rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN); - rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH); - rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK); - rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE); - rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL); - rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC); - rmesa->hw.cst.cmd[CST_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CNTL_X); - rmesa->hw.cst.cmd[CST_CMD_1] = cmdpkt(rmesa, R200_EMIT_RB3D_DEPTHXY_OFFSET); - rmesa->hw.cst.cmd[CST_CMD_2] = cmdpkt(rmesa, R200_EMIT_RE_AUX_SCISSOR_CNTL); - rmesa->hw.cst.cmd[CST_CMD_4] = cmdpkt(rmesa, R200_EMIT_SE_VAP_CNTL_STATUS); - rmesa->hw.cst.cmd[CST_CMD_5] = cmdpkt(rmesa, R200_EMIT_RE_POINTSIZE); - rmesa->hw.cst.cmd[CST_CMD_6] = cmdpkt(rmesa, R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0); - rmesa->hw.tam.cmd[TAM_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TAM_DEBUG3); - rmesa->hw.tf.cmd[TF_CMD_0] = cmdpkt(rmesa, R200_EMIT_TFACTOR_0); - rmesa->hw.atf.cmd[ATF_CMD_0] = cmdpkt(rmesa, R200_EMIT_ATF_TFACTOR); - rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_0); - rmesa->hw.tex[0].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_0); - rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_1); - rmesa->hw.tex[1].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_1); - rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_2); - rmesa->hw.tex[2].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_2); - rmesa->hw.tex[3].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_3); - rmesa->hw.tex[3].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_3); - rmesa->hw.tex[4].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_4); - rmesa->hw.tex[4].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_4); - rmesa->hw.tex[5].cmd[TEX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCTLALL_5); - rmesa->hw.tex[5].cmd[TEX_CMD_1_NEWDRM] = cmdpkt(rmesa, R200_EMIT_PP_TXOFFSET_5); - rmesa->hw.afs[0].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_0); - rmesa->hw.afs[1].cmd[AFS_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_AFS_1); - rmesa->hw.pvs.cmd[PVS_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_PVS_CNTL); - rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_0); - rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_0); - rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_1); - rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_1); - rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_2); - rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_2); - rmesa->hw.cube[3].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_3); - rmesa->hw.cube[3].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_3); - rmesa->hw.cube[4].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_4); - rmesa->hw.cube[4].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_4); - rmesa->hw.cube[5].cmd[CUBE_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_FACES_5); - rmesa->hw.cube[5].cmd[CUBE_CMD_1] = cmdpkt(rmesa, R200_EMIT_PP_CUBIC_OFFSETS_5); - rmesa->hw.pix[0].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_0); - rmesa->hw.pix[1].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_1); - rmesa->hw.pix[2].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_2); - rmesa->hw.pix[3].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_3); - rmesa->hw.pix[4].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_4); - rmesa->hw.pix[5].cmd[PIX_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TXCBLEND_5); - rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR); - rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_LIGHT_MODEL_CTL_0); - rmesa->hw.tcl.cmd[TCL_CMD_1] = cmdpkt(rmesa, R200_EMIT_TCL_UCP_VERT_BLEND_CTL); - rmesa->hw.tcg.cmd[TCG_CMD_0] = cmdpkt(rmesa, R200_EMIT_TEX_PROC_CTL_2); - rmesa->hw.msl.cmd[MSL_CMD_0] = cmdpkt(rmesa, R200_EMIT_MATRIX_SELECT_0); - rmesa->hw.vap.cmd[VAP_CMD_0] = cmdpkt(rmesa, R200_EMIT_VAP_CTL); - rmesa->hw.vtx.cmd[VTX_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTX_FMT_0); - rmesa->hw.vtx.cmd[VTX_CMD_1] = cmdpkt(rmesa, R200_EMIT_OUTPUT_VTX_COMP_SEL); - rmesa->hw.vtx.cmd[VTX_CMD_2] = cmdpkt(rmesa, R200_EMIT_SE_VTX_STATE_CNTL); - rmesa->hw.vte.cmd[VTE_CMD_0] = cmdpkt(rmesa, R200_EMIT_VTE_CNTL); - rmesa->hw.prf.cmd[PRF_CMD_0] = cmdpkt(rmesa, R200_EMIT_PP_TRI_PERF_CNTL); - rmesa->hw.spr.cmd[SPR_CMD_0] = cmdpkt(rmesa, R200_EMIT_TCL_POINT_SPRITE_CNTL); - - rmesa->hw.sci.cmd[SCI_CMD_1] = CP_PACKET0(R200_RE_TOP_LEFT, 0); - rmesa->hw.sci.cmd[SCI_CMD_2] = CP_PACKET0(R200_RE_WIDTH_HEIGHT, 0); - - rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0); - rmesa->hw.stp.cmd[STP_DATA_0] = 0; - rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31); - - rmesa->hw.mtl[0].emit = mtl_emit; - rmesa->hw.mtl[1].emit = mtl_emit; - - rmesa->hw.vpi[0].emit = veclinear_emit; - rmesa->hw.vpi[1].emit = veclinear_emit; - rmesa->hw.vpp[0].emit = veclinear_emit; - rmesa->hw.vpp[1].emit = veclinear_emit; - - rmesa->hw.grd.emit = scl_emit; - rmesa->hw.fog.emit = vec_emit; - rmesa->hw.glt.emit = vec_emit; - rmesa->hw.eye.emit = vec_emit; - - for (i = R200_MTX_MV; i <= R200_MTX_TEX5; i++) - rmesa->hw.mat[i].emit = vec_emit; - - for (i = 0; i < 8; i++) - rmesa->hw.lit[i].emit = lit_emit; - - for (i = 0; i < 6; i++) - rmesa->hw.ucp[i].emit = vec_emit; - - rmesa->hw.ptp.emit = ptp_emit; - - rmesa->hw.mtl[0].cmd[MTL_CMD_0] = - cmdvec( R200_VS_MAT_0_EMISS, 1, 16 ); - rmesa->hw.mtl[0].cmd[MTL_CMD_1] = - cmdscl2( R200_SS_MAT_0_SHININESS, 1, 1 ); - rmesa->hw.mtl[1].cmd[MTL_CMD_0] = - cmdvec( R200_VS_MAT_1_EMISS, 1, 16 ); - rmesa->hw.mtl[1].cmd[MTL_CMD_1] = - cmdscl2( R200_SS_MAT_1_SHININESS, 1, 1 ); - - rmesa->hw.vpi[0].cmd[VPI_CMD_0] = - cmdveclinear( R200_PVS_PROG0, 64 ); - rmesa->hw.vpi[1].cmd[VPI_CMD_0] = - cmdveclinear( R200_PVS_PROG1, 64 ); - rmesa->hw.vpp[0].cmd[VPP_CMD_0] = - cmdveclinear( R200_PVS_PARAM0, 96 ); - rmesa->hw.vpp[1].cmd[VPP_CMD_0] = - cmdveclinear( R200_PVS_PARAM1, 96 ); - - rmesa->hw.grd.cmd[GRD_CMD_0] = - cmdscl( R200_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 ); - rmesa->hw.fog.cmd[FOG_CMD_0] = - cmdvec( R200_VS_FOG_PARAM_ADDR, 1, 4 ); - rmesa->hw.glt.cmd[GLT_CMD_0] = - cmdvec( R200_VS_GLOBAL_AMBIENT_ADDR, 1, 4 ); - rmesa->hw.eye.cmd[EYE_CMD_0] = - cmdvec( R200_VS_EYE_VECTOR_ADDR, 1, 4 ); - - rmesa->hw.mat[R200_MTX_MV].cmd[MAT_CMD_0] = - cmdvec( R200_VS_MATRIX_0_MV, 1, 16); - rmesa->hw.mat[R200_MTX_IMV].cmd[MAT_CMD_0] = - cmdvec( R200_VS_MATRIX_1_INV_MV, 1, 16); - rmesa->hw.mat[R200_MTX_MVP].cmd[MAT_CMD_0] = - cmdvec( R200_VS_MATRIX_2_MVP, 1, 16); - rmesa->hw.mat[R200_MTX_TEX0].cmd[MAT_CMD_0] = - cmdvec( R200_VS_MATRIX_3_TEX0, 1, 16); - rmesa->hw.mat[R200_MTX_TEX1].cmd[MAT_CMD_0] = - cmdvec( R200_VS_MATRIX_4_TEX1, 1, 16); - rmesa->hw.mat[R200_MTX_TEX2].cmd[MAT_CMD_0] = - cmdvec( R200_VS_MATRIX_5_TEX2, 1, 16); - rmesa->hw.mat[R200_MTX_TEX3].cmd[MAT_CMD_0] = - cmdvec( R200_VS_MATRIX_6_TEX3, 1, 16); - rmesa->hw.mat[R200_MTX_TEX4].cmd[MAT_CMD_0] = - cmdvec( R200_VS_MATRIX_7_TEX4, 1, 16); - rmesa->hw.mat[R200_MTX_TEX5].cmd[MAT_CMD_0] = - cmdvec( R200_VS_MATRIX_8_TEX5, 1, 16); - - for (i = 0 ; i < 8; i++) { - rmesa->hw.lit[i].cmd[LIT_CMD_0] = - cmdvec( R200_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 ); - rmesa->hw.lit[i].cmd[LIT_CMD_1] = - cmdscl( R200_SS_LIGHT_DCD_ADDR + i, 8, 7 ); - } - - for (i = 0 ; i < 6; i++) { - rmesa->hw.ucp[i].cmd[UCP_CMD_0] = - cmdvec( R200_VS_UCP_ADDR + i, 1, 4 ); - } - - rmesa->hw.ptp.cmd[PTP_CMD_0] = - cmdvec( R200_VS_PNT_SPRITE_VPORT_SCALE, 1, 4 ); - rmesa->hw.ptp.cmd[PTP_CMD_1] = - cmdvec( R200_VS_PNT_SPRITE_ATT_CONST, 1, 12 ); - - /* Initial Harware state: - */ - rmesa->hw.ctx.cmd[CTX_PP_MISC] = (R200_ALPHA_TEST_PASS - /* | R200_RIGHT_HAND_CUBE_OGL*/); - - rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (R200_FOG_VERTEX | - R200_FOG_USE_SPEC_ALPHA); - - rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000; - - rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP | - (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | - (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT)); - - rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCOLOR] = 0x00000000; - rmesa->hw.ctx.cmd[CTX_RB3D_ABLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP | - (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | - (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT)); - rmesa->hw.ctx.cmd[CTX_RB3D_CBLENDCNTL] = (R200_COMB_FCN_ADD_CLAMP | - (R200_BLEND_GL_ONE << R200_SRC_BLEND_SHIFT) | - (R200_BLEND_GL_ZERO << R200_DST_BLEND_SHIFT)); - - rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] = - rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation; - - rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] = - ((rmesa->radeon.radeonScreen->depthPitch & - R200_DEPTHPITCH_MASK) | - R200_DEPTH_ENDIAN_NO_SWAP); - - if (rmesa->using_hyperz) - rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= R200_DEPTH_HYPERZ; - - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (R200_Z_TEST_LESS | - R200_STENCIL_TEST_ALWAYS | - R200_STENCIL_FAIL_KEEP | - R200_STENCIL_ZPASS_KEEP | - R200_STENCIL_ZFAIL_KEEP | - R200_Z_WRITE_ENABLE); - - if (rmesa->using_hyperz) { - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= R200_Z_COMPRESSION_ENABLE | - R200_Z_DECOMPRESSION_ENABLE; -/* if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) - rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/ - } - - rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (R200_ANTI_ALIAS_NONE - | R200_TEX_BLEND_0_ENABLE); - - switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) { - case DRI_CONF_DITHER_XERRORDIFFRESET: - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_INIT; - break; - case DRI_CONF_DITHER_ORDERED: - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_SCALE_DITHER_ENABLE; - break; - } - if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) == - DRI_CONF_ROUND_ROUND ) - rmesa->radeon.state.color.roundEnable = R200_ROUND_ENABLE; - else - rmesa->radeon.state.color.roundEnable = 0; - if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) == - DRI_CONF_COLOR_REDUCTION_DITHER ) - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= R200_DITHER_ENABLE; - else - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable; - - rmesa->hw.prf.cmd[PRF_PP_TRI_PERF] = R200_TRI_CUTOFF_MASK - R200_TRI_CUTOFF_MASK * - driQueryOptionf (&rmesa->radeon.optionCache,"texture_blend_quality"); - rmesa->hw.prf.cmd[PRF_PP_PERF_CNTL] = 0; - - rmesa->hw.set.cmd[SET_SE_CNTL] = (R200_FFACE_CULL_CCW | - R200_BFACE_SOLID | - R200_FFACE_SOLID | - R200_FLAT_SHADE_VTX_LAST | - R200_DIFFUSE_SHADE_GOURAUD | - R200_ALPHA_SHADE_GOURAUD | - R200_SPECULAR_SHADE_GOURAUD | - R200_FOG_SHADE_GOURAUD | - R200_DISC_FOG_SHADE_GOURAUD | - R200_VTX_PIX_CENTER_OGL | - R200_ROUND_MODE_TRUNC | - R200_ROUND_PREC_8TH_PIX); - - rmesa->hw.set.cmd[SET_RE_CNTL] = (R200_PERSPECTIVE_ENABLE | - R200_SCISSOR_ENABLE); - - rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff); - - rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] = - ((0 << R200_LINE_CURRENT_PTR_SHIFT) | - (1 << R200_LINE_CURRENT_COUNT_SHIFT)); - - rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4); - - rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] = - ((0x00 << R200_STENCIL_REF_SHIFT) | - (0xff << R200_STENCIL_MASK_SHIFT) | - (0xff << R200_STENCIL_WRITEMASK_SHIFT)); - - rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = R200_ROP_COPY; - rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff; - - rmesa->hw.tam.cmd[TAM_DEBUG3] = 0; - - rmesa->hw.msc.cmd[MSC_RE_MISC] = - ((0 << R200_STIPPLE_X_OFFSET_SHIFT) | - (0 << R200_STIPPLE_Y_OFFSET_SHIFT) | - R200_STIPPLE_BIG_BIT_ORDER); - - - rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0; - rmesa->hw.cst.cmd[CST_RB3D_DEPTHXY_OFFSET] = 0; - rmesa->hw.cst.cmd[CST_RE_AUX_SCISSOR_CNTL] = 0x0; - rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] = -#ifdef MESA_BIG_ENDIAN - R200_VC_32BIT_SWAP; -#else - R200_VC_NO_SWAP; -#endif - - if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) { - /* Bypass TCL */ - rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8); - } - - rmesa->hw.cst.cmd[CST_RE_POINTSIZE] = - (((GLuint)(ctx->Const.MaxPointSize * 16.0)) << R200_MAXPOINTSIZE_SHIFT) | 0x10; - rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] = - (0x0 << R200_VERTEX_POSITION_ADDR__SHIFT); - rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_1] = - (0x02 << R200_VTX_COLOR_0_ADDR__SHIFT) | - (0x03 << R200_VTX_COLOR_1_ADDR__SHIFT); - rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_2] = - (0x06 << R200_VTX_TEX_0_ADDR__SHIFT) | - (0x07 << R200_VTX_TEX_1_ADDR__SHIFT) | - (0x08 << R200_VTX_TEX_2_ADDR__SHIFT) | - (0x09 << R200_VTX_TEX_3_ADDR__SHIFT); - rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_3] = - (0x0A << R200_VTX_TEX_4_ADDR__SHIFT) | - (0x0B << R200_VTX_TEX_5_ADDR__SHIFT); - - - rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000; - rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000; - rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000; - rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000; - rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000; - rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000; - - for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) { - rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = R200_BORDER_MODE_OGL; - rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] = - ((i << R200_TXFORMAT_ST_ROUTE_SHIFT) | /* <-- note i */ - (2 << R200_TXFORMAT_WIDTH_SHIFT) | - (2 << R200_TXFORMAT_HEIGHT_SHIFT)); - rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0; - rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT_X] = - (/* R200_TEXCOORD_PROJ | */ - R200_LOD_BIAS_CORRECTION); /* Small default bias */ - rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET_NEWDRM] = - rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; - rmesa->hw.tex[i].cmd[TEX_PP_CUBIC_FACES] = 0; - rmesa->hw.tex[i].cmd[TEX_PP_TXMULTI_CTL] = 0; - - rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0; - rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F1] = - rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; - rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F2] = - rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; - rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F3] = - rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; - rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F4] = - rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; - rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_F5] = - rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]; - - rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND] = - (R200_TXC_ARG_A_ZERO | - R200_TXC_ARG_B_ZERO | - R200_TXC_ARG_C_DIFFUSE_COLOR | - R200_TXC_OP_MADD); - - rmesa->hw.pix[i].cmd[PIX_PP_TXCBLEND2] = - ((i << R200_TXC_TFACTOR_SEL_SHIFT) | - R200_TXC_SCALE_1X | - R200_TXC_CLAMP_0_1 | - R200_TXC_OUTPUT_REG_R0); - - rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND] = - (R200_TXA_ARG_A_ZERO | - R200_TXA_ARG_B_ZERO | - R200_TXA_ARG_C_DIFFUSE_ALPHA | - R200_TXA_OP_MADD); - - rmesa->hw.pix[i].cmd[PIX_PP_TXABLEND2] = - ((i << R200_TXA_TFACTOR_SEL_SHIFT) | - R200_TXA_SCALE_1X | - R200_TXA_CLAMP_0_1 | - R200_TXA_OUTPUT_REG_R0); - } - - rmesa->hw.tf.cmd[TF_TFACTOR_0] = 0; - rmesa->hw.tf.cmd[TF_TFACTOR_1] = 0; - rmesa->hw.tf.cmd[TF_TFACTOR_2] = 0; - rmesa->hw.tf.cmd[TF_TFACTOR_3] = 0; - rmesa->hw.tf.cmd[TF_TFACTOR_4] = 0; - rmesa->hw.tf.cmd[TF_TFACTOR_5] = 0; - - rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] = - (R200_VAP_TCL_ENABLE | - (0x9 << R200_VAP_VF_MAX_VTX_NUM__SHIFT)); - - rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] = - (R200_VPORT_X_SCALE_ENA | - R200_VPORT_Y_SCALE_ENA | - R200_VPORT_Z_SCALE_ENA | - R200_VPORT_X_OFFSET_ENA | - R200_VPORT_Y_OFFSET_ENA | - R200_VPORT_Z_OFFSET_ENA | -/* FIXME: Turn on for tex rect only */ - R200_VTX_ST_DENORMALIZED | - R200_VTX_W0_FMT); - - - rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = 0; - rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = 0; - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_0] = - ((R200_VTX_Z0 | R200_VTX_W0 | - (R200_VTX_FP_RGBA << R200_VTX_COLOR_0_SHIFT))); - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] = 0; - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = (R200_OUTPUT_XYZW); - rmesa->hw.vtx.cmd[VTX_STATE_CNTL] = R200_VSC_UPDATE_USER_COLOR_0_ENABLE; - - - /* Matrix selection */ - rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_0] = - (R200_MTX_MV << R200_MODELVIEW_0_SHIFT); - - rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_1] = - (R200_MTX_IMV << R200_IT_MODELVIEW_0_SHIFT); - - rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_2] = - (R200_MTX_MVP << R200_MODELPROJECT_0_SHIFT); - - rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_3] = - ((R200_MTX_TEX0 << R200_TEXMAT_0_SHIFT) | - (R200_MTX_TEX1 << R200_TEXMAT_1_SHIFT) | - (R200_MTX_TEX2 << R200_TEXMAT_2_SHIFT) | - (R200_MTX_TEX3 << R200_TEXMAT_3_SHIFT)); - - rmesa->hw.msl.cmd[MSL_MATRIX_SELECT_4] = - ((R200_MTX_TEX4 << R200_TEXMAT_4_SHIFT) | - (R200_MTX_TEX5 << R200_TEXMAT_5_SHIFT)); - - - /* General TCL state */ - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_0] = - (R200_SPECULAR_LIGHTS | - R200_DIFFUSE_SPECULAR_COMBINE | - R200_LOCAL_LIGHT_VEC_GL | - R200_LM0_SOURCE_MATERIAL_0 << R200_FRONT_SHININESS_SOURCE_SHIFT | - R200_LM0_SOURCE_MATERIAL_1 << R200_BACK_SHININESS_SOURCE_SHIFT); - - rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL_1] = - ((R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_EMISSIVE_SOURCE_SHIFT) | - (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_AMBIENT_SOURCE_SHIFT) | - (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_DIFFUSE_SOURCE_SHIFT) | - (R200_LM1_SOURCE_MATERIAL_0 << R200_FRONT_SPECULAR_SOURCE_SHIFT) | - (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_EMISSIVE_SOURCE_SHIFT) | - (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_AMBIENT_SOURCE_SHIFT) | - (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_DIFFUSE_SOURCE_SHIFT) | - (R200_LM1_SOURCE_MATERIAL_1 << R200_BACK_SPECULAR_SOURCE_SHIFT)); - - rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_0] = 0; /* filled in via callbacks */ - rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_1] = 0; - rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_2] = 0; - rmesa->hw.tcl.cmd[TCL_PER_LIGHT_CTL_3] = 0; - - rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = - (R200_UCP_IN_CLIP_SPACE | - R200_CULL_FRONT_IS_CCW); - - /* Texgen/Texmat state */ - rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = 0x00ffffff; - rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_3] = - ((0 << R200_TEXGEN_0_INPUT_TEX_SHIFT) | - (1 << R200_TEXGEN_1_INPUT_TEX_SHIFT) | - (2 << R200_TEXGEN_2_INPUT_TEX_SHIFT) | - (3 << R200_TEXGEN_3_INPUT_TEX_SHIFT) | - (4 << R200_TEXGEN_4_INPUT_TEX_SHIFT) | - (5 << R200_TEXGEN_5_INPUT_TEX_SHIFT)); - rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_0] = 0; - rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] = - ((0 << R200_TEXGEN_0_INPUT_SHIFT) | - (1 << R200_TEXGEN_1_INPUT_SHIFT) | - (2 << R200_TEXGEN_2_INPUT_SHIFT) | - (3 << R200_TEXGEN_3_INPUT_SHIFT) | - (4 << R200_TEXGEN_4_INPUT_SHIFT) | - (5 << R200_TEXGEN_5_INPUT_SHIFT)); - rmesa->hw.tcg.cmd[TCG_TEX_CYL_WRAP_CTL] = 0; - - - for (i = 0 ; i < 8; i++) { - struct gl_light_uniforms *lu = &ctx->Light.LightSource[i]; - GLenum p = GL_LIGHT0 + i; - *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX; - - ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, lu->Ambient ); - ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, lu->Diffuse ); - ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, lu->Specular ); - ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL ); - ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL ); - ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &lu->SpotExponent ); - ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &lu->SpotCutoff ); - ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION, - &lu->ConstantAttenuation ); - ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION, - &lu->LinearAttenuation ); - ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION, - &lu->QuadraticAttenuation ); - *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0; - } - - ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT, - ctx->Light.Model.Ambient ); - - TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx ); - - for (i = 0 ; i < 6; i++) { - ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL ); - } - - ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL ); - ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density ); - ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start ); - ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End ); - ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color ); - ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL ); - - rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE; - rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE; - rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE; - rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE; - - rmesa->hw.eye.cmd[EYE_X] = 0; - rmesa->hw.eye.cmd[EYE_Y] = 0; - rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE; - rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE; - - rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] = - R200_PS_SE_SEL_STATE | R200_PS_MULT_CONST; - - /* ptp_eye is presumably used to calculate the attenuation wrt a different - location? In any case, since point attenuation triggers _needeyecoords, - it is constant. Probably ignored as long as R200_PS_USE_MODEL_EYE_VEC - isn't set */ - rmesa->hw.ptp.cmd[PTP_EYE_X] = 0; - rmesa->hw.ptp.cmd[PTP_EYE_Y] = 0; - rmesa->hw.ptp.cmd[PTP_EYE_Z] = IEEE_ONE | 0x80000000; /* -1.0 */ - rmesa->hw.ptp.cmd[PTP_EYE_3] = 0; - /* no idea what the ptp_vport_scale values are good for, except the - PTSIZE one - hopefully doesn't matter */ - rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_0] = IEEE_ONE; - rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_1] = IEEE_ONE; - rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_PTSIZE] = IEEE_ONE; - rmesa->hw.ptp.cmd[PTP_VPORT_SCALE_3] = IEEE_ONE; - rmesa->hw.ptp.cmd[PTP_ATT_CONST_QUAD] = 0; - rmesa->hw.ptp.cmd[PTP_ATT_CONST_LIN] = 0; - rmesa->hw.ptp.cmd[PTP_ATT_CONST_CON] = IEEE_ONE; - rmesa->hw.ptp.cmd[PTP_ATT_CONST_3] = 0; - rmesa->hw.ptp.cmd[PTP_CLAMP_MIN] = IEEE_ONE; - rmesa->hw.ptp.cmd[PTP_CLAMP_MAX] = 0x44ffe000; /* 2047 */ - rmesa->hw.ptp.cmd[PTP_CLAMP_2] = 0; - rmesa->hw.ptp.cmd[PTP_CLAMP_3] = 0; - - r200LightingSpaceChange( ctx ); - - radeon_init_query_stateobj(&rmesa->radeon, R200_QUERYOBJ_CMDSIZE); - rmesa->radeon.query.queryobj.cmd[R200_QUERYOBJ_CMD_0] = CP_PACKET0(RADEON_RB3D_ZPASS_DATA, 0); - rmesa->radeon.query.queryobj.cmd[R200_QUERYOBJ_DATA_0] = 0; - - rmesa->radeon.hw.all_dirty = GL_TRUE; - - rcommonInitCmdBuf(&rmesa->radeon); -} diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.c b/src/mesa/drivers/dri/r200/r200_swtcl.c deleted file mode 100644 index 07e7d6e7ac8..00000000000 --- a/src/mesa/drivers/dri/r200/r200_swtcl.c +++ /dev/null @@ -1,955 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell <keithw@vmware.com> - */ - -#include "main/glheader.h" -#include "main/mtypes.h" -#include "main/enums.h" -#include "main/image.h" - -#include "main/macros.h" -#include "main/state.h" - -#include "swrast/s_context.h" -#include "swrast/s_fog.h" -#include "swrast_setup/swrast_setup.h" -#include "tnl/tnl.h" -#include "tnl/t_context.h" -#include "tnl/t_pipeline.h" - -#include "r200_context.h" -#include "r200_ioctl.h" -#include "r200_state.h" -#include "r200_swtcl.h" -#include "r200_tcl.h" - - -/*********************************************************************** - * Initialization - ***********************************************************************/ - -#define EMIT_ATTR( ATTR, STYLE, F0 ) \ -do { \ - rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \ - rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \ - rmesa->radeon.swtcl.vertex_attr_count++; \ - fmt_0 |= F0; \ -} while (0) - -#define EMIT_PAD( N ) \ -do { \ - rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \ - rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \ - rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N); \ - rmesa->radeon.swtcl.vertex_attr_count++; \ -} while (0) - -static void r200SetVertexFormat( struct gl_context *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT( ctx ); - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *VB = &tnl->vb; - GLbitfield64 index_bitset = tnl->render_inputs_bitset; - int fmt_0 = 0; - int fmt_1 = 0; - int offset = 0; - - /* Important: - */ - if ( VB->NdcPtr != NULL ) { - VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr; - } - else { - VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr; - } - - assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL ); - rmesa->radeon.swtcl.vertex_attr_count = 0; - - /* EMIT_ATTR's must be in order as they tell t_vertex.c how to - * build up a hardware vertex. - */ - if ( !rmesa->swtcl.needproj || - (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) ) { - /* need w coord for projected textures */ - EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F, R200_VTX_XY | R200_VTX_Z0 | R200_VTX_W0 ); - offset = 4; - } - else { - EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F, R200_VTX_XY | R200_VTX_Z0 ); - offset = 3; - } - - if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_POINTSIZE)) { - EMIT_ATTR( _TNL_ATTRIB_POINTSIZE, EMIT_1F, R200_VTX_POINT_SIZE ); - offset += 1; - } - - rmesa->swtcl.coloroffset = offset; -#if MESA_LITTLE_ENDIAN - EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA, (R200_VTX_PK_RGBA << R200_VTX_COLOR_0_SHIFT) ); -#else - EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR, (R200_VTX_PK_RGBA << R200_VTX_COLOR_0_SHIFT) ); -#endif - offset += 1; - - rmesa->swtcl.specoffset = 0; - if (index_bitset & - (BITFIELD64_BIT(_TNL_ATTRIB_COLOR1) | BITFIELD64_BIT(_TNL_ATTRIB_FOG))) { - -#if MESA_LITTLE_ENDIAN - if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) { - rmesa->swtcl.specoffset = offset; - EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB, (R200_VTX_PK_RGBA << R200_VTX_COLOR_1_SHIFT) ); - } - else { - EMIT_PAD( 3 ); - } - - if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) { - EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F, (R200_VTX_PK_RGBA << R200_VTX_COLOR_1_SHIFT) ); - } - else { - EMIT_PAD( 1 ); - } -#else - if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) { - EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F, (R200_VTX_PK_RGBA << R200_VTX_COLOR_1_SHIFT) ); - } - else { - EMIT_PAD( 1 ); - } - - if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) { - rmesa->swtcl.specoffset = offset; - EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, (R200_VTX_PK_RGBA << R200_VTX_COLOR_1_SHIFT) ); - } - else { - EMIT_PAD( 3 ); - } -#endif - } - - if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { - int i; - - for (i = 0; i < ctx->Const.MaxTextureUnits; i++) { - if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_TEX(i))) { - GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size; - - fmt_1 |= sz << (3 * i); - EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_1F + sz - 1, 0 ); - } - } - } - - if ( (rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] & R200_FOG_USE_MASK) - != R200_FOG_USE_SPEC_ALPHA ) { - R200_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] &= ~R200_FOG_USE_MASK; - rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] |= R200_FOG_USE_SPEC_ALPHA; - } - - if (rmesa->radeon.tnl_index_bitset != index_bitset || - (rmesa->hw.vtx.cmd[VTX_VTXFMT_0] != fmt_0) || - (rmesa->hw.vtx.cmd[VTX_VTXFMT_1] != fmt_1) ) { - R200_NEWPRIM(rmesa); - R200_STATECHANGE( rmesa, vtx ); - rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = fmt_0; - rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = fmt_1; - - rmesa->radeon.swtcl.vertex_size = - _tnl_install_attrs( ctx, - rmesa->radeon.swtcl.vertex_attrs, - rmesa->radeon.swtcl.vertex_attr_count, - NULL, 0 ); - rmesa->radeon.swtcl.vertex_size /= 4; - rmesa->radeon.tnl_index_bitset = index_bitset; - } -} - -static void r200_predict_emit_size( r200ContextPtr rmesa ) -{ - if (RADEON_DEBUG & RADEON_VERTS) - fprintf(stderr, "%s\n", __func__); - const int vertex_array_size = 7; - const int prim_size = 3; - if (!rmesa->radeon.swtcl.emit_prediction) { - const int state_size = radeonCountStateEmitSize(&rmesa->radeon); - if (rcommonEnsureCmdBufSpace(&rmesa->radeon, - state_size + - vertex_array_size + prim_size, - __func__)) - rmesa->radeon.swtcl.emit_prediction = radeonCountStateEmitSize(&rmesa->radeon); - else - rmesa->radeon.swtcl.emit_prediction = state_size; - rmesa->radeon.swtcl.emit_prediction += vertex_array_size + prim_size - + rmesa->radeon.cmdbuf.cs->cdw; - } -} - - -static void r200RenderStart( struct gl_context *ctx ) -{ - r200SetVertexFormat( ctx ); - if (RADEON_DEBUG & RADEON_VERTS) - fprintf(stderr, "%s\n", __func__); -} - - -/** - * Set vertex state for SW TCL. The primary purpose of this function is to - * determine in advance whether or not the hardware can / should do the - * projection divide or Mesa should do it. - */ -void r200ChooseVertexState( struct gl_context *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT( ctx ); - TNLcontext *tnl = TNL_CONTEXT(ctx); - GLuint vte; - GLuint vap; - GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL || - ctx->Polygon.BackMode != GL_FILL); - GLboolean twosided = ctx->Light.Enabled && ctx->Light.Model.TwoSide; - - /* We must ensure that we don't do _tnl_need_projected_coords while in a - * rasterization fallback. As this function will be called again when we - * leave a rasterization fallback, we can just skip it for now. - */ - if (rmesa->radeon.Fallback != 0) - return; - - vte = rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL]; - vap = rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL]; - - /* HW perspective divide is a win, but tiny vertex formats are a - * bigger one. - */ - if ((0 == (tnl->render_inputs_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))) - || twosided - || unfilled) { - rmesa->swtcl.needproj = GL_TRUE; - vte |= R200_VTX_XY_FMT | R200_VTX_Z_FMT; - vte &= ~R200_VTX_W0_FMT; - if (tnl->render_inputs_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { - vap &= ~R200_VAP_FORCE_W_TO_ONE; - } - else { - vap |= R200_VAP_FORCE_W_TO_ONE; - } - } - else { - rmesa->swtcl.needproj = GL_FALSE; - vte &= ~(R200_VTX_XY_FMT | R200_VTX_Z_FMT); - vte |= R200_VTX_W0_FMT; - vap &= ~R200_VAP_FORCE_W_TO_ONE; - } - - _tnl_need_projected_coords( ctx, rmesa->swtcl.needproj ); - - if (vte != rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL]) { - R200_STATECHANGE( rmesa, vte ); - rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] = vte; - } - - if (vap != rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL]) { - R200_STATECHANGE( rmesa, vap ); - rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] = vap; - } -} - -void r200_swtcl_flush(struct gl_context *ctx, uint32_t current_offset) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - if (RADEON_DEBUG & RADEON_VERTS) - fprintf(stderr, "%s\n", __func__); - - - radeonEmitState(&rmesa->radeon); - r200EmitVertexAOS( rmesa, - rmesa->radeon.swtcl.vertex_size, - rmesa->radeon.swtcl.bo, - current_offset); - - - r200EmitVbufPrim( rmesa, - rmesa->radeon.swtcl.hw_primitive, - rmesa->radeon.swtcl.numverts); - if ( rmesa->radeon.swtcl.emit_prediction < rmesa->radeon.cmdbuf.cs->cdw ) - WARN_ONCE("Rendering was %d commands larger than predicted size." - " We might overflow command buffer.\n", - rmesa->radeon.cmdbuf.cs->cdw - rmesa->radeon.swtcl.emit_prediction ); - - rmesa->radeon.swtcl.emit_prediction = 0; - -} - -/**************************************************************************/ - - -static inline GLuint reduced_hw_prim( struct gl_context *ctx, GLuint prim) -{ - switch (prim) { - case GL_POINTS: - return ((!ctx->Point.SmoothFlag) ? - R200_VF_PRIM_POINT_SPRITES : R200_VF_PRIM_POINTS); - case GL_LINES: - FALLTHROUGH; - case GL_LINE_LOOP: - FALLTHROUGH; - case GL_LINE_STRIP: - return R200_VF_PRIM_LINES; - default: - /* all others reduced to triangles */ - return R200_VF_PRIM_TRIANGLES; - } -} - - -static void r200RasterPrimitive( struct gl_context *ctx, GLuint hwprim ); -static void r200RenderPrimitive( struct gl_context *ctx, GLenum prim ); -static void r200ResetLineStipple( struct gl_context *ctx ); - -/*********************************************************************** - * Emit primitives as inline vertices * - ***********************************************************************/ - -#define HAVE_POINTS 1 -#define HAVE_LINES 1 -#define HAVE_LINE_STRIPS 1 -#define HAVE_TRIANGLES 1 -#define HAVE_TRI_STRIPS 1 -#define HAVE_TRI_FANS 1 -#define HAVE_QUADS 0 -#define HAVE_QUAD_STRIPS 0 -#define HAVE_POLYGONS 1 -#define HAVE_ELTS 0 - -static void* r200_alloc_verts( r200ContextPtr rmesa, GLuint n, GLuint size) -{ - void *rv; - do { - r200_predict_emit_size( rmesa ); - rv = rcommonAllocDmaLowVerts( &rmesa->radeon, n, size * 4 ); - } while(!rv); - return rv; -} - -#undef LOCAL_VARS -#undef ALLOC_VERTS -#define CTX_ARG r200ContextPtr rmesa -#define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size -#define ALLOC_VERTS( n, size ) r200_alloc_verts(rmesa, n, size) -#define LOCAL_VARS \ - r200ContextPtr rmesa = R200_CONTEXT(ctx); \ - const char *r200verts = (char *)rmesa->radeon.swtcl.verts; -#define VERT(x) (radeonVertex *)(r200verts + ((x) * vertsize * sizeof(int))) -#define VERTEX radeonVertex -#define DO_DEBUG_VERTS (1 && (R200_DEBUG & RADEON_VERTS)) - -#undef TAG -#define TAG(x) r200_##x -#include "tnl_dd/t_dd_triemit.h" - - -/*********************************************************************** - * Macros for t_dd_tritmp.h to draw basic primitives * - ***********************************************************************/ - -#define QUAD( a, b, c, d ) r200_quad( rmesa, a, b, c, d ) -#define TRI( a, b, c ) r200_triangle( rmesa, a, b, c ) -#define LINE( a, b ) r200_line( rmesa, a, b ) -#define POINT( a ) r200_point( rmesa, a ) - -/*********************************************************************** - * Build render functions from dd templates * - ***********************************************************************/ - -#define R200_TWOSIDE_BIT 0x01 -#define R200_UNFILLED_BIT 0x02 -#define R200_MAX_TRIFUNC 0x04 - - -static struct { - tnl_points_func points; - tnl_line_func line; - tnl_triangle_func triangle; - tnl_quad_func quad; -} rast_tab[R200_MAX_TRIFUNC]; - - -#define DO_FALLBACK 0 -#define DO_UNFILLED ((IND & R200_UNFILLED_BIT) != 0) -#define DO_TWOSIDE ((IND & R200_TWOSIDE_BIT) != 0) -#define DO_FLAT 0 -#define DO_OFFSET 0 -#define DO_TRI 1 -#define DO_QUAD 1 -#define DO_LINE 1 -#define DO_POINTS 1 -#define DO_FULL_QUAD 1 - -#define HAVE_SPEC 1 -#define HAVE_BACK_COLORS 0 -#define HAVE_HW_FLATSHADE 1 -#define TAB rast_tab - -#define DEPTH_SCALE 1.0 -#define UNFILLED_TRI unfilled_tri -#define UNFILLED_QUAD unfilled_quad -#define VERT_X(_v) _v->v.x -#define VERT_Y(_v) _v->v.y -#define VERT_Z(_v) _v->v.z -#define AREA_IS_CCW( a ) (a < 0) -#define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + (e*rmesa->radeon.swtcl.vertex_size*sizeof(int))) - -#define VERT_SET_RGBA( v, c ) \ -do { \ - radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]); \ - UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]); \ - UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]); \ - UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]); \ - UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]); \ -} while (0) - -#define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset] - -#define VERT_SET_SPEC( v, c ) \ -do { \ - if (specoffset) { \ - radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]); \ - UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]); \ - UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]); \ - UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]); \ - } \ -} while (0) -#define VERT_COPY_SPEC( v0, v1 ) \ -do { \ - if (specoffset) { \ - radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]); \ - radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]); \ - spec0->red = spec1->red; \ - spec0->green = spec1->green; \ - spec0->blue = spec1->blue; \ - } \ -} while (0) - -/* These don't need LE32_TO_CPU() as they used to save and restore - * colors which are already in the correct format. - */ -#define VERT_SAVE_RGBA( idx ) color[idx] = v[idx]->ui[coloroffset] -#define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx] -#define VERT_SAVE_SPEC( idx ) if (specoffset) spec[idx] = v[idx]->ui[specoffset] -#define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx] - -#undef LOCAL_VARS -#undef TAG -#undef INIT - -#define LOCAL_VARS(n) \ - r200ContextPtr rmesa = R200_CONTEXT(ctx); \ - GLuint color[n] = {0}, spec[n] = {0}; \ - GLuint coloroffset = rmesa->swtcl.coloroffset; \ - GLuint specoffset = rmesa->swtcl.specoffset; \ - (void) color; (void) spec; (void) coloroffset; (void) specoffset; - -/*********************************************************************** - * Helpers for rendering unfilled primitives * - ***********************************************************************/ - -#define RASTERIZE(x) r200RasterPrimitive( ctx, reduced_hw_prim(ctx, x) ) -#define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive -#undef TAG -#define TAG(x) x -#include "tnl_dd/t_dd_unfilled.h" -#undef IND - - -/*********************************************************************** - * Generate GL render functions * - ***********************************************************************/ - - -#define IND (0) -#define TAG(x) x -#include "tnl_dd/t_dd_tritmp.h" - -#define IND (R200_TWOSIDE_BIT) -#define TAG(x) x##_twoside -#include "tnl_dd/t_dd_tritmp.h" - -#define IND (R200_UNFILLED_BIT) -#define TAG(x) x##_unfilled -#include "tnl_dd/t_dd_tritmp.h" - -#define IND (R200_TWOSIDE_BIT|R200_UNFILLED_BIT) -#define TAG(x) x##_twoside_unfilled -#include "tnl_dd/t_dd_tritmp.h" - - -static void init_rast_tab( void ) -{ - init(); - init_twoside(); - init_unfilled(); - init_twoside_unfilled(); -} - -/**********************************************************************/ -/* Render unclipped begin/end objects */ -/**********************************************************************/ - -#define RENDER_POINTS( start, count ) \ - for ( ; start < count ; start++) \ - r200_point( rmesa, VERT(start) ) -#define RENDER_LINE( v0, v1 ) \ - r200_line( rmesa, VERT(v0), VERT(v1) ) -#define RENDER_TRI( v0, v1, v2 ) \ - r200_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) ) -#define RENDER_QUAD( v0, v1, v2, v3 ) \ - r200_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) ) -#define INIT(x) do { \ - r200RenderPrimitive( ctx, x ); \ -} while (0) -#undef LOCAL_VARS -#define LOCAL_VARS \ - r200ContextPtr rmesa = R200_CONTEXT(ctx); \ - const GLuint vertsize = rmesa->radeon.swtcl.vertex_size; \ - const char *r200verts = (char *)rmesa->radeon.swtcl.verts; \ - const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \ - const GLboolean stipple = ctx->Line.StippleFlag; \ - (void) elt; (void) stipple; -#define RESET_STIPPLE if ( stipple ) r200ResetLineStipple( ctx ); -#define RESET_OCCLUSION -#define PRESERVE_VB_DEFS -#define ELT(x) (x) -#define TAG(x) r200_##x##_verts -#include "tnl/t_vb_rendertmp.h" -#undef ELT -#undef TAG -#define TAG(x) r200_##x##_elts -#define ELT(x) elt[x] -#include "tnl/t_vb_rendertmp.h" - - - -/**********************************************************************/ -/* Choose render functions */ -/**********************************************************************/ - -void r200ChooseRenderState( struct gl_context *ctx ) -{ - TNLcontext *tnl = TNL_CONTEXT(ctx); - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint index = 0; - GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL || - ctx->Polygon.BackMode != GL_FILL); - GLboolean twosided = ctx->Light.Enabled && ctx->Light.Model.TwoSide; - - if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback) - return; - - if (twosided) - index |= R200_TWOSIDE_BIT; - if (unfilled) - index |= R200_UNFILLED_BIT; - - if (index != rmesa->radeon.swtcl.RenderIndex) { - tnl->Driver.Render.Points = rast_tab[index].points; - tnl->Driver.Render.Line = rast_tab[index].line; - tnl->Driver.Render.ClippedLine = rast_tab[index].line; - tnl->Driver.Render.Triangle = rast_tab[index].triangle; - tnl->Driver.Render.Quad = rast_tab[index].quad; - - if (index == 0) { - tnl->Driver.Render.PrimTabVerts = r200_render_tab_verts; - tnl->Driver.Render.PrimTabElts = r200_render_tab_elts; - tnl->Driver.Render.ClippedPolygon = r200_fast_clipped_poly; - } else { - tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts; - tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts; - tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon; - } - - rmesa->radeon.swtcl.RenderIndex = index; - } -} - - -/**********************************************************************/ -/* High level hooks for t_vb_render.c */ -/**********************************************************************/ - - -static void r200RasterPrimitive( struct gl_context *ctx, GLuint hwprim ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - radeon_prepare_render(&rmesa->radeon); - if (rmesa->radeon.NewGLState) - r200ValidateState( ctx ); - - - if (rmesa->radeon.swtcl.hw_primitive != hwprim) { - /* need to disable perspective-correct texturing for point sprites */ - if ((hwprim & 0xf) == R200_VF_PRIM_POINT_SPRITES && ctx->Point.PointSprite) { - if (rmesa->hw.set.cmd[SET_RE_CNTL] & R200_PERSPECTIVE_ENABLE) { - R200_STATECHANGE( rmesa, set ); - rmesa->hw.set.cmd[SET_RE_CNTL] &= ~R200_PERSPECTIVE_ENABLE; - } - } - else if (!(rmesa->hw.set.cmd[SET_RE_CNTL] & R200_PERSPECTIVE_ENABLE)) { - R200_STATECHANGE( rmesa, set ); - rmesa->hw.set.cmd[SET_RE_CNTL] |= R200_PERSPECTIVE_ENABLE; - } - R200_NEWPRIM( rmesa ); - rmesa->radeon.swtcl.hw_primitive = hwprim; - } -} - -static void r200RenderPrimitive( struct gl_context *ctx, GLenum prim ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL || - ctx->Polygon.BackMode != GL_FILL); - - rmesa->radeon.swtcl.render_primitive = prim; - if (prim < GL_TRIANGLES || !unfilled) - r200RasterPrimitive( ctx, reduced_hw_prim(ctx, prim) ); -} - -static void r200RenderFinish( struct gl_context *ctx ) -{ -} - -static void r200ResetLineStipple( struct gl_context *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - R200_STATECHANGE( rmesa, lin ); -} - - -/**********************************************************************/ -/* Transition to/from hardware rasterization. */ -/**********************************************************************/ - -static const char * const fallbackStrings[] = { - "Texture mode", - "glDrawBuffer(GL_FRONT_AND_BACK)", - "glEnable(GL_STENCIL) without hw stencil buffer", - "glRenderMode(selection or feedback)", - "R200_NO_RAST", - "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)" -}; - - -static const char *getFallbackString(GLuint bit) -{ - int i = 0; - while (bit > 1) { - i++; - bit >>= 1; - } - return fallbackStrings[i]; -} - - -void r200Fallback( struct gl_context *ctx, GLuint bit, GLboolean mode ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - TNLcontext *tnl = TNL_CONTEXT(ctx); - GLuint oldfallback = rmesa->radeon.Fallback; - - if (mode) { - rmesa->radeon.Fallback |= bit; - if (oldfallback == 0) { - radeon_firevertices(&rmesa->radeon); - TCL_FALLBACK( ctx, R200_TCL_FALLBACK_RASTER, GL_TRUE ); - _swsetup_Wakeup( ctx ); - rmesa->radeon.swtcl.RenderIndex = ~0; - if (R200_DEBUG & RADEON_FALLBACKS) { - fprintf(stderr, "R200 begin rasterization fallback: 0x%x %s\n", - bit, getFallbackString(bit)); - } - } - } - else { - rmesa->radeon.Fallback &= ~bit; - if (oldfallback == bit) { - - _swrast_flush( ctx ); - tnl->Driver.Render.Start = r200RenderStart; - tnl->Driver.Render.PrimitiveNotify = r200RenderPrimitive; - tnl->Driver.Render.Finish = r200RenderFinish; - - tnl->Driver.Render.BuildVertices = _tnl_build_vertices; - tnl->Driver.Render.CopyPV = _tnl_copy_pv; - tnl->Driver.Render.Interp = _tnl_interp; - - tnl->Driver.Render.ResetLineStipple = r200ResetLineStipple; - TCL_FALLBACK( ctx, R200_TCL_FALLBACK_RASTER, GL_FALSE ); - if (rmesa->radeon.TclFallback) { - /* These are already done if rmesa->radeon.TclFallback goes to - * zero above. But not if it doesn't (R200_NO_TCL for - * example?) - */ - _tnl_invalidate_vertex_state( ctx, ~0 ); - _tnl_invalidate_vertices( ctx, ~0 ); - rmesa->radeon.tnl_index_bitset = 0; - r200ChooseVertexState( ctx ); - r200ChooseRenderState( ctx ); - } - if (R200_DEBUG & RADEON_FALLBACKS) { - fprintf(stderr, "R200 end rasterization fallback: 0x%x %s\n", - bit, getFallbackString(bit)); - } - } - } -} - - - - -/** - * Cope with depth operations by drawing individual pixels as points. - * - * \todo - * The way the vertex state is set in this routine is hokey. It seems to - * work, but it's very hackish. This whole routine is pretty hackish. If - * the bitmap is small enough, it seems like it would be faster to copy it - * to AGP memory and use it as a non-power-of-two texture (i.e., - * NV_texture_rectangle). - */ -void -r200PointsBitmap( struct gl_context *ctx, GLint px, GLint py, - GLsizei width, GLsizei height, - const struct gl_pixelstore_attrib *unpack, - const GLubyte *bitmap ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - const GLfloat *rc = ctx->Current.RasterColor; - GLint row, col; - radeonVertex vert; - GLuint orig_vte; - GLuint h; - - - /* Turn off tcl. - */ - TCL_FALLBACK( ctx, R200_TCL_FALLBACK_BITMAP, 1 ); - - /* Choose tiny vertex format - */ - { - const GLuint fmt_0 = R200_VTX_XY | R200_VTX_Z0 | R200_VTX_W0 - | (R200_VTX_PK_RGBA << R200_VTX_COLOR_0_SHIFT); - const GLuint fmt_1 = 0; - GLuint vte = rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL]; - GLuint vap = rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL]; - - vte &= ~(R200_VTX_XY_FMT | R200_VTX_Z_FMT); - vte |= R200_VTX_W0_FMT; - vap &= ~R200_VAP_FORCE_W_TO_ONE; - - rmesa->radeon.swtcl.vertex_size = 5; - - if ( (rmesa->hw.vtx.cmd[VTX_VTXFMT_0] != fmt_0) - || (rmesa->hw.vtx.cmd[VTX_VTXFMT_1] != fmt_1) ) { - R200_NEWPRIM(rmesa); - R200_STATECHANGE( rmesa, vtx ); - rmesa->hw.vtx.cmd[VTX_VTXFMT_0] = fmt_0; - rmesa->hw.vtx.cmd[VTX_VTXFMT_1] = fmt_1; - } - - if (vte != rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL]) { - R200_STATECHANGE( rmesa, vte ); - rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] = vte; - } - - if (vap != rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL]) { - R200_STATECHANGE( rmesa, vap ); - rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] = vap; - } - } - - /* Ready for point primitives: - */ - r200RenderPrimitive( ctx, GL_POINTS ); - - /* Turn off the hw viewport transformation: - */ - R200_STATECHANGE( rmesa, vte ); - orig_vte = rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL]; - rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] &= ~(R200_VPORT_X_SCALE_ENA | - R200_VPORT_Y_SCALE_ENA | - R200_VPORT_Z_SCALE_ENA | - R200_VPORT_X_OFFSET_ENA | - R200_VPORT_Y_OFFSET_ENA | - R200_VPORT_Z_OFFSET_ENA); - - /* Turn off other stuff: Stipple?, texture?, blending?, etc. - */ - - - /* Populate the vertex - * - * Incorporate FOG into RGBA - */ - if (ctx->Fog.Enabled) { - const GLfloat *fc = ctx->Fog.Color; - GLfloat color[4]; - GLfloat f; - - if (ctx->Fog.FogCoordinateSource == GL_FOG_COORDINATE_EXT) - f = _swrast_z_to_fogfactor(ctx, ctx->Current.Attrib[VERT_ATTRIB_FOG][0]); - else - f = _swrast_z_to_fogfactor(ctx, ctx->Current.RasterDistance); - - color[0] = f * rc[0] + (1.F - f) * fc[0]; - color[1] = f * rc[1] + (1.F - f) * fc[1]; - color[2] = f * rc[2] + (1.F - f) * fc[2]; - color[3] = rc[3]; - - UNCLAMPED_FLOAT_TO_CHAN(vert.tv.color.red, color[0]); - UNCLAMPED_FLOAT_TO_CHAN(vert.tv.color.green, color[1]); - UNCLAMPED_FLOAT_TO_CHAN(vert.tv.color.blue, color[2]); - UNCLAMPED_FLOAT_TO_CHAN(vert.tv.color.alpha, color[3]); - } - else { - UNCLAMPED_FLOAT_TO_CHAN(vert.tv.color.red, rc[0]); - UNCLAMPED_FLOAT_TO_CHAN(vert.tv.color.green, rc[1]); - UNCLAMPED_FLOAT_TO_CHAN(vert.tv.color.blue, rc[2]); - UNCLAMPED_FLOAT_TO_CHAN(vert.tv.color.alpha, rc[3]); - } - - - vert.tv.z = ctx->Current.RasterPos[2]; - - - /* Update window height - */ - h = radeon_get_drawable(&rmesa->radeon)->h; - - /* Clipping handled by existing mechansims in r200_ioctl.c? - */ - for (row=0; row<height; row++) { - const GLubyte *src = (const GLubyte *) - _mesa_image_address2d(unpack, bitmap, width, height, - GL_COLOR_INDEX, GL_BITMAP, row, 0 ); - - if (unpack->LsbFirst) { - /* Lsb first */ - GLubyte mask = 1U << (unpack->SkipPixels & 0x7); - for (col=0; col<width; col++) { - if (*src & mask) { - vert.tv.x = px+col; - vert.tv.y = h - (py+row) - 1; - r200_point( rmesa, &vert ); - } - src += (mask >> 7); - mask = ((mask << 1) & 0xff) | (mask >> 7); - } - - /* get ready for next row */ - if (mask != 1) - src++; - } - else { - /* Msb first */ - GLubyte mask = 128U >> (unpack->SkipPixels & 0x7); - for (col=0; col<width; col++) { - if (*src & mask) { - vert.tv.x = px+col; - vert.tv.y = h - (py+row) - 1; - r200_point( rmesa, &vert ); - } - src += mask & 1; - mask = ((mask << 7) & 0xff) | (mask >> 1); - } - /* get ready for next row */ - if (mask != 128) - src++; - } - } - - /* Fire outstanding vertices, restore state - */ - R200_STATECHANGE( rmesa, vte ); - rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] = orig_vte; - - /* Unfallback - */ - TCL_FALLBACK( ctx, R200_TCL_FALLBACK_BITMAP, 0 ); - - /* Need to restore vertexformat? - */ - if (rmesa->radeon.TclFallback) - r200ChooseVertexState( ctx ); -} - - - -/**********************************************************************/ -/* Initialization. */ -/**********************************************************************/ - -void r200InitSwtcl( struct gl_context *ctx ) -{ - TNLcontext *tnl = TNL_CONTEXT(ctx); - r200ContextPtr rmesa = R200_CONTEXT(ctx); - static int firsttime = 1; - - if (firsttime) { - init_rast_tab(); - firsttime = 0; - } - rmesa->radeon.swtcl.emit_prediction = 0; - - tnl->Driver.Render.Start = r200RenderStart; - tnl->Driver.Render.Finish = r200RenderFinish; - tnl->Driver.Render.PrimitiveNotify = r200RenderPrimitive; - tnl->Driver.Render.ResetLineStipple = r200ResetLineStipple; - tnl->Driver.Render.BuildVertices = _tnl_build_vertices; - tnl->Driver.Render.CopyPV = _tnl_copy_pv; - tnl->Driver.Render.Interp = _tnl_interp; - - /* FIXME: what are these numbers? */ - _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12, - 36 * sizeof(GLfloat) ); - - rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf; - rmesa->radeon.swtcl.RenderIndex = ~0; - rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES; - rmesa->radeon.swtcl.hw_primitive = 0; -} - diff --git a/src/mesa/drivers/dri/r200/r200_swtcl.h b/src/mesa/drivers/dri/r200/r200_swtcl.h deleted file mode 100644 index c12204536e4..00000000000 --- a/src/mesa/drivers/dri/r200/r200_swtcl.h +++ /dev/null @@ -1,69 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - -/* - * Authors: - * Keith Whitwell <keithw@vmware.com> - */ - -#ifndef __R200_SWTCL_H__ -#define __R200_SWTCL_H__ - -#include "main/mtypes.h" -#include "swrast/swrast.h" -#include "r200_context.h" - -extern void r200InitSwtcl( struct gl_context *ctx ); - -extern void r200ChooseRenderState( struct gl_context *ctx ); -extern void r200ChooseVertexState( struct gl_context *ctx ); - -extern void r200CheckTexSizes( struct gl_context *ctx ); - -extern void r200BuildVertices( struct gl_context *ctx, GLuint start, GLuint count, - GLuint newinputs ); - -extern void r200PrintSetupFlags(char *msg, GLuint flags ); - - -extern void r200_translate_vertex( struct gl_context *ctx, - const radeonVertex *src, - SWvertex *dst ); - -extern void r200_print_vertex( struct gl_context *ctx, const radeonVertex *v ); - -extern void r200_import_float_colors( struct gl_context *ctx ); -extern void r200_import_float_spec_colors( struct gl_context *ctx ); - -extern void r200PointsBitmap( struct gl_context *ctx, GLint px, GLint py, - GLsizei width, GLsizei height, - const struct gl_pixelstore_attrib *unpack, - const GLubyte *bitmap ); - -void r200_swtcl_flush(struct gl_context *ctx, uint32_t current_offset); -#endif diff --git a/src/mesa/drivers/dri/r200/r200_tcl.c b/src/mesa/drivers/dri/r200/r200_tcl.c deleted file mode 100644 index d7b2479773d..00000000000 --- a/src/mesa/drivers/dri/r200/r200_tcl.c +++ /dev/null @@ -1,638 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell <keithw@vmware.com> - */ - -#include "main/glheader.h" - -#include "main/mtypes.h" -#include "main/enums.h" -#include "main/light.h" -#include "main/state.h" - -#include "vbo/vbo.h" -#include "tnl/tnl.h" -#include "tnl/t_pipeline.h" - -#include "r200_context.h" -#include "r200_state.h" -#include "r200_ioctl.h" -#include "r200_tcl.h" -#include "r200_swtcl.h" -#include "r200_maos.h" - -#include "radeon_common_context.h" - - - -#define HAVE_POINTS 1 -#define HAVE_LINES 1 -#define HAVE_LINE_LOOP 0 -#define HAVE_LINE_STRIPS 1 -#define HAVE_TRIANGLES 1 -#define HAVE_TRI_STRIPS 1 -#define HAVE_TRI_FANS 1 -#define HAVE_QUADS 1 -#define HAVE_QUAD_STRIPS 1 -#define HAVE_POLYGONS 1 -#define HAVE_ELTS 1 - - -#define HW_POINTS ((!ctx->Point.SmoothFlag) ? \ - R200_VF_PRIM_POINT_SPRITES : R200_VF_PRIM_POINTS) -#define HW_LINES R200_VF_PRIM_LINES -#define HW_LINE_LOOP 0 -#define HW_LINE_STRIP R200_VF_PRIM_LINE_STRIP -#define HW_TRIANGLES R200_VF_PRIM_TRIANGLES -#define HW_TRIANGLE_STRIP_0 R200_VF_PRIM_TRIANGLE_STRIP -#define HW_TRIANGLE_STRIP_1 0 -#define HW_TRIANGLE_FAN R200_VF_PRIM_TRIANGLE_FAN -#define HW_QUADS R200_VF_PRIM_QUADS -#define HW_QUAD_STRIP R200_VF_PRIM_QUAD_STRIP -#define HW_POLYGON R200_VF_PRIM_POLYGON - - -static GLboolean discrete_prim[0x10] = { - 0, /* 0 none */ - 1, /* 1 points */ - 1, /* 2 lines */ - 0, /* 3 line_strip */ - 1, /* 4 tri_list */ - 0, /* 5 tri_fan */ - 0, /* 6 tri_strip */ - 0, /* 7 tri_w_flags */ - 1, /* 8 rect list (unused) */ - 1, /* 9 3vert point */ - 1, /* a 3vert line */ - 0, /* b point sprite */ - 0, /* c line loop */ - 1, /* d quads */ - 0, /* e quad strip */ - 0, /* f polygon */ -}; - - -#define LOCAL_VARS r200ContextPtr rmesa = R200_CONTEXT(ctx) -#define ELT_TYPE GLushort - -#define ELT_INIT(prim, hw_prim) \ - r200TclPrimitive( ctx, prim, hw_prim | R200_VF_PRIM_WALK_IND ) - -#define GET_MESA_ELTS() TNL_CONTEXT(ctx)->vb.Elts - - -/* Don't really know how many elts will fit in what's left of cmdbuf, - * as there is state to emit, etc: - */ - -/* Testing on isosurf shows a maximum around here. Don't know if it's - * the card or driver or kernel module that is causing the behaviour. - */ -#define GET_MAX_HW_ELTS() 300 - -#define RESET_STIPPLE() do { \ - R200_STATECHANGE( rmesa, lin ); \ - radeonEmitState(&rmesa->radeon); \ -} while (0) - -#define AUTO_STIPPLE( mode ) do { \ - R200_STATECHANGE( rmesa, lin ); \ - if (mode) \ - rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] |= \ - R200_LINE_PATTERN_AUTO_RESET; \ - else \ - rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \ - ~R200_LINE_PATTERN_AUTO_RESET; \ - radeonEmitState(&rmesa->radeon); \ -} while (0) - - -#define ALLOC_ELTS(nr) r200AllocElts( rmesa, nr ) - -static GLushort *r200AllocElts( r200ContextPtr rmesa, GLuint nr ) -{ - if (rmesa->radeon.dma.flush == r200FlushElts && - rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) { - - GLushort *dest = (GLushort *)(rmesa->radeon.tcl.elt_dma_bo->ptr + - rmesa->radeon.tcl.elt_dma_offset + rmesa->tcl.elt_used); - - rmesa->tcl.elt_used += nr*2; - - return dest; - } - else { - if (rmesa->radeon.dma.flush) - rmesa->radeon.dma.flush( &rmesa->radeon.glCtx ); - - r200EmitAOS( rmesa, - rmesa->radeon.tcl.aos_count, 0 ); - - r200EmitMaxVtxIndex(rmesa, rmesa->radeon.tcl.aos[0].count); - return r200AllocEltsOpenEnded( rmesa, rmesa->tcl.hw_primitive, nr ); - } -} - - -#define CLOSE_ELTS() \ -do { \ - if (0) R200_NEWPRIM( rmesa ); \ -} \ -while (0) - - -/* TODO: Try to extend existing primitive if both are identical, - * discrete and there are no intervening state changes. (Somewhat - * duplicates changes to DrawArrays code) - */ -static void r200EmitPrim( struct gl_context *ctx, - GLenum prim, - GLuint hwprim, - GLuint start, - GLuint count) -{ - r200ContextPtr rmesa = R200_CONTEXT( ctx ); - r200TclPrimitive( ctx, prim, hwprim ); - - // fprintf(stderr,"Emit prim %d\n", rmesa->radeon.tcl.aos_count); - - r200EmitAOS( rmesa, - rmesa->radeon.tcl.aos_count, - start ); - - /* Why couldn't this packet have taken an offset param? - */ - r200EmitVbufPrim( rmesa, - rmesa->tcl.hw_primitive, - count - start ); -} - -#define EMIT_PRIM(ctx, prim, hwprim, start, count) do { \ - r200EmitPrim( ctx, prim, hwprim, start, count ); \ - (void) rmesa; } while (0) - -#define MAX_CONVERSION_SIZE 40 -/* Try & join small primitives - */ -#if 0 -#define PREFER_DISCRETE_ELT_PRIM( NR, PRIM ) 0 -#else -#define PREFER_DISCRETE_ELT_PRIM( NR, PRIM ) \ - ((NR) < 20 || \ - ((NR) < 40 && \ - rmesa->tcl.hw_primitive == (PRIM| \ - R200_VF_TCL_OUTPUT_VTX_ENABLE| \ - R200_VF_PRIM_WALK_IND))) -#endif - -#ifdef MESA_BIG_ENDIAN -/* We could do without (most of) this ugliness if dest was always 32 bit word aligned... */ -#define EMIT_ELT(dest, offset, x) do { \ - int off = offset + ( ( (uintptr_t)dest & 0x2 ) >> 1 ); \ - GLushort *des = (GLushort *)( (uintptr_t)dest & ~0x2 ); \ - (des)[ off + 1 - 2 * ( off & 1 ) ] = (GLushort)(x); \ - (void)rmesa; } while (0) -#else -#define EMIT_ELT(dest, offset, x) do { \ - (dest)[offset] = (GLushort) (x); \ - (void)rmesa; } while (0) -#endif - -#define EMIT_TWO_ELTS(dest, offset, x, y) *(GLuint *)((dest)+offset) = ((y)<<16)|(x); - - - -#define TAG(x) tcl_##x -#include "tnl_dd/t_dd_dmatmp2.h" - -/**********************************************************************/ -/* External entrypoints */ -/**********************************************************************/ - -void r200EmitPrimitive( struct gl_context *ctx, - GLuint first, - GLuint last, - GLuint flags ) -{ - tcl_render_tab_verts[flags&PRIM_MODE_MASK]( ctx, first, last, flags ); -} - -void r200EmitEltPrimitive( struct gl_context *ctx, - GLuint first, - GLuint last, - GLuint flags ) -{ - tcl_render_tab_elts[flags&PRIM_MODE_MASK]( ctx, first, last, flags ); -} - -void r200TclPrimitive( struct gl_context *ctx, - GLenum prim, - int hw_prim ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint newprim = hw_prim | R200_VF_TCL_OUTPUT_VTX_ENABLE; - - radeon_prepare_render(&rmesa->radeon); - if (rmesa->radeon.NewGLState) - r200ValidateState( ctx ); - - if (newprim != rmesa->tcl.hw_primitive || - !discrete_prim[hw_prim&0xf]) { - /* need to disable perspective-correct texturing for point sprites */ - if ((prim & PRIM_MODE_MASK) == GL_POINTS && ctx->Point.PointSprite) { - if (rmesa->hw.set.cmd[SET_RE_CNTL] & R200_PERSPECTIVE_ENABLE) { - R200_STATECHANGE( rmesa, set ); - rmesa->hw.set.cmd[SET_RE_CNTL] &= ~R200_PERSPECTIVE_ENABLE; - } - } - else if (!(rmesa->hw.set.cmd[SET_RE_CNTL] & R200_PERSPECTIVE_ENABLE)) { - R200_STATECHANGE( rmesa, set ); - rmesa->hw.set.cmd[SET_RE_CNTL] |= R200_PERSPECTIVE_ENABLE; - } - R200_NEWPRIM( rmesa ); - rmesa->tcl.hw_primitive = newprim; - } -} - -/** - * Predict total emit size for next rendering operation so there is no flush in middle of rendering - * Prediction has to aim towards the best possible value that is worse than worst case scenario - */ -static GLuint r200EnsureEmitSize( struct gl_context * ctx , GLubyte* vimap_rev ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *VB = &tnl->vb; - GLuint space_required; - GLuint state_size; - GLuint nr_aos = 0; - int i; - /* predict number of aos to emit */ - for (i = 0; i < 15; ++i) - { - if (vimap_rev[i] != 255) - { - ++nr_aos; - } - } - - { - /* count the prediction for state size */ - space_required = 0; - state_size = radeonCountStateEmitSize( &rmesa->radeon ); - /* vtx may be changed in r200EmitArrays so account for it if not dirty */ - if (!rmesa->hw.vtx.dirty) - state_size += rmesa->hw.vtx.check(&rmesa->radeon.glCtx, &rmesa->hw.vtx); - /* predict size for elements */ - for (i = 0; i < VB->PrimitiveCount; ++i) - { - if (!VB->Primitive[i].count) - continue; - /* If primitive.count is less than MAX_CONVERSION_SIZE - rendering code may decide convert to elts. - In that case we have to make pessimistic prediction. - and use larger of 2 paths. */ - const GLuint elt_count =(VB->Primitive[i].count/GET_MAX_HW_ELTS() + 1); - const GLuint elts = ELTS_BUFSZ(nr_aos) * elt_count; - const GLuint index = INDEX_BUFSZ * elt_count; - const GLuint vbuf = VBUF_BUFSZ; - if ( (!VB->Elts && VB->Primitive[i].count >= MAX_CONVERSION_SIZE) - || vbuf > index + elts) - space_required += vbuf; - else - space_required += index + elts; - space_required += AOS_BUFSZ(nr_aos); - } - } - - radeon_print(RADEON_RENDER,RADEON_VERBOSE, - "%s space %u, aos %d\n", - __func__, space_required, AOS_BUFSZ(nr_aos) ); - /* flush the buffer in case we need more than is left. */ - if (rcommonEnsureCmdBufSpace(&rmesa->radeon, space_required + state_size, __func__)) - return space_required + radeonCountStateEmitSize( &rmesa->radeon ); - else - return space_required + state_size; -} - - -/**********************************************************************/ -/* Render pipeline stage */ -/**********************************************************************/ - - -/* TCL render. - */ -static GLboolean r200_run_tcl_render( struct gl_context *ctx, - struct tnl_pipeline_stage *stage ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - TNLcontext *tnl = TNL_CONTEXT(ctx); - struct vertex_buffer *VB = &tnl->vb; - GLuint i; - GLubyte *vimap_rev; -/* use hw fixed order for simplicity, pos 0, weight 1, normal 2, fog 3, - color0 - color3 4-7, texcoord0 - texcoord5 8-13, pos 1 14. Must not use - more than 12 of those at the same time. */ - GLubyte map_rev_fixed[15] = {255, 255, 255, 255, 255, 255, 255, 255, - 255, 255, 255, 255, 255, 255, 255}; - - - /* TODO: separate this from the swtnl pipeline - */ - if (rmesa->radeon.TclFallback) - return GL_TRUE; /* fallback to software t&l */ - - radeon_print(RADEON_RENDER, RADEON_NORMAL, "%s\n", __func__); - - if (VB->Count == 0) - return GL_FALSE; - - /* Validate state: - */ - if (rmesa->radeon.NewGLState) - if (!r200ValidateState( ctx )) - return GL_TRUE; /* fallback to sw t&l */ - - if (!_mesa_arb_vertex_program_enabled(ctx)) { - /* NOTE: inputs != tnl->render_inputs - these are the untransformed - * inputs. - */ - map_rev_fixed[0] = VERT_ATTRIB_POS; - /* technically there is no reason we always need VA_COLOR0. In theory - could disable it depending on lighting, color materials, texturing... */ - map_rev_fixed[4] = VERT_ATTRIB_COLOR0; - - if (ctx->Light.Enabled) { - map_rev_fixed[2] = VERT_ATTRIB_NORMAL; - } - - /* this also enables VA_COLOR1 when using separate specular - lighting model, which is unnecessary. - FIXME: OTOH, we're missing the case where a ATI_fragment_shader accesses - the secondary color (if lighting is disabled). The chip seems - misconfigured for that though elsewhere (tcl output, might lock up) */ - if (_mesa_need_secondary_color(ctx)) { - map_rev_fixed[5] = VERT_ATTRIB_COLOR1; - } - - if ( (ctx->Fog.FogCoordinateSource == GL_FOG_COORD) && ctx->Fog.Enabled ) { - map_rev_fixed[3] = VERT_ATTRIB_FOG; - } - - for (i = 0 ; i < ctx->Const.MaxTextureUnits; i++) { - if (ctx->Texture.Unit[i]._Current) { - if (rmesa->TexGenNeedNormals[i]) { - map_rev_fixed[2] = VERT_ATTRIB_NORMAL; - } - map_rev_fixed[8 + i] = VERT_ATTRIB_TEX0 + i; - } - } - vimap_rev = &map_rev_fixed[0]; - } - else { - /* vtx_tcl_output_vtxfmt_0/1 need to match configuration of "fragment - part", since using some vertex interpolator later which is not in - out_vtxfmt0/1 will lock up. It seems to be ok to write in vertex - prog to a not enabled output however, so just don't mess with it. - We only need to change compsel. */ - GLuint out_compsel = 0; - const GLbitfield64 vp_out = - rmesa->curr_vp_hw->mesa_program.info.outputs_written; - - vimap_rev = &rmesa->curr_vp_hw->inputmap_rev[0]; - assert(vp_out & BITFIELD64_BIT(VARYING_SLOT_POS)); - out_compsel = R200_OUTPUT_XYZW; - if (vp_out & BITFIELD64_BIT(VARYING_SLOT_COL0)) { - out_compsel |= R200_OUTPUT_COLOR_0; - } - if (vp_out & BITFIELD64_BIT(VARYING_SLOT_COL1)) { - out_compsel |= R200_OUTPUT_COLOR_1; - } - if (vp_out & BITFIELD64_BIT(VARYING_SLOT_FOGC)) { - out_compsel |= R200_OUTPUT_DISCRETE_FOG; - } - if (vp_out & BITFIELD64_BIT(VARYING_SLOT_PSIZ)) { - out_compsel |= R200_OUTPUT_PT_SIZE; - } - for (i = VARYING_SLOT_TEX0; i < VARYING_SLOT_TEX6; i++) { - if (vp_out & BITFIELD64_BIT(i)) { - out_compsel |= R200_OUTPUT_TEX_0 << (i - VARYING_SLOT_TEX0); - } - } - if (rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] != out_compsel) { - R200_STATECHANGE( rmesa, vtx ); - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_COMPSEL] = out_compsel; - } - } - - /* Do the actual work: - */ - radeonReleaseArrays( ctx, ~0 /* stage->changed_inputs */ ); - GLuint emit_end = r200EnsureEmitSize( ctx, vimap_rev ) - + rmesa->radeon.cmdbuf.cs->cdw; - r200EmitArrays( ctx, vimap_rev ); - - for (i = 0 ; i < VB->PrimitiveCount ; i++) - { - GLuint prim = _tnl_translate_prim(&VB->Primitive[i]); - GLuint start = VB->Primitive[i].start; - GLuint length = VB->Primitive[i].count; - - if (!length) - continue; - - if (VB->Elts) - r200EmitEltPrimitive( ctx, start, start+length, prim ); - else - r200EmitPrimitive( ctx, start, start+length, prim ); - } - if ( emit_end < rmesa->radeon.cmdbuf.cs->cdw ) - WARN_ONCE("Rendering was %d commands larger than predicted size." - " We might overflow command buffer.\n", rmesa->radeon.cmdbuf.cs->cdw - emit_end); - - return GL_FALSE; /* finished the pipe */ -} - - - -/* Initial state for tcl stage. - */ -const struct tnl_pipeline_stage _r200_tcl_stage = -{ - "r200 render", - NULL, /* private */ - NULL, - NULL, - NULL, - r200_run_tcl_render /* run */ -}; - - - -/**********************************************************************/ -/* Validate state at pipeline start */ -/**********************************************************************/ - - -/*----------------------------------------------------------------------- - * Manage TCL fallbacks - */ - - -static void transition_to_swtnl( struct gl_context *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - TNLcontext *tnl = TNL_CONTEXT(ctx); - - R200_NEWPRIM( rmesa ); - - r200ChooseVertexState( ctx ); - r200ChooseRenderState( ctx ); - - _tnl_validate_shine_tables( ctx ); - - tnl->Driver.NotifyMaterialChange = - _tnl_validate_shine_tables; - - radeonReleaseArrays( ctx, ~0 ); - - /* Still using the D3D based hardware-rasterizer from the radeon; - * need to put the card into D3D mode to make it work: - */ - R200_STATECHANGE( rmesa, vap ); - rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] &= ~(R200_VAP_TCL_ENABLE|R200_VAP_PROG_VTX_SHADER_ENABLE); -} - -static void transition_to_hwtnl( struct gl_context *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - TNLcontext *tnl = TNL_CONTEXT(ctx); - - _tnl_need_projected_coords( ctx, GL_FALSE ); - - r200UpdateMaterial( ctx ); - - tnl->Driver.NotifyMaterialChange = r200UpdateMaterial; - - if ( rmesa->radeon.dma.flush ) - rmesa->radeon.dma.flush( &rmesa->radeon.glCtx ); - - rmesa->radeon.dma.flush = NULL; - - R200_STATECHANGE( rmesa, vap ); - rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] |= R200_VAP_TCL_ENABLE; - rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] &= ~R200_VAP_FORCE_W_TO_ONE; - - if (_mesa_arb_vertex_program_enabled(ctx)) { - rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] |= R200_VAP_PROG_VTX_SHADER_ENABLE; - } - - if ( ((rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] & R200_FOG_USE_MASK) - == R200_FOG_USE_SPEC_ALPHA) && - (ctx->Fog.FogCoordinateSource == GL_FOG_COORD )) { - R200_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] &= ~R200_FOG_USE_MASK; - rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] |= R200_FOG_USE_VTX_FOG; - } - - R200_STATECHANGE( rmesa, vte ); - rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] &= ~(R200_VTX_XY_FMT|R200_VTX_Z_FMT); - rmesa->hw.vte.cmd[VTE_SE_VTE_CNTL] |= R200_VTX_W0_FMT; - - if (R200_DEBUG & RADEON_FALLBACKS) - fprintf(stderr, "R200 end tcl fallback\n"); -} - - -static char *fallbackStrings[] = { - "Rasterization fallback", - "Unfilled triangles", - "Twosided lighting, differing materials", - "Materials in VB (maybe between begin/end)", - "Texgen unit 0", - "Texgen unit 1", - "Texgen unit 2", - "Texgen unit 3", - "Texgen unit 4", - "Texgen unit 5", - "User disable", - "Bitmap as points", - "Vertex program" -}; - - -static char *getFallbackString(GLuint bit) -{ - int i = 0; - while (bit > 1) { - i++; - bit >>= 1; - } - return fallbackStrings[i]; -} - - - -void r200TclFallback( struct gl_context *ctx, GLuint bit, GLboolean mode ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint oldfallback = rmesa->radeon.TclFallback; - - if (mode) { - if (oldfallback == 0) { - /* We have to flush before transition */ - if ( rmesa->radeon.dma.flush ) - rmesa->radeon.dma.flush( &rmesa->radeon.glCtx ); - - if (R200_DEBUG & RADEON_FALLBACKS) - fprintf(stderr, "R200 begin tcl fallback %s\n", - getFallbackString( bit )); - rmesa->radeon.TclFallback |= bit; - transition_to_swtnl( ctx ); - } else - rmesa->radeon.TclFallback |= bit; - } else { - if (oldfallback == bit) { - /* We have to flush before transition */ - if ( rmesa->radeon.dma.flush ) - rmesa->radeon.dma.flush( &rmesa->radeon.glCtx ); - - if (R200_DEBUG & RADEON_FALLBACKS) - fprintf(stderr, "R200 end tcl fallback %s\n", - getFallbackString( bit )); - rmesa->radeon.TclFallback &= ~bit; - transition_to_hwtnl( ctx ); - } else - rmesa->radeon.TclFallback &= ~bit; - } -} diff --git a/src/mesa/drivers/dri/r200/r200_tcl.h b/src/mesa/drivers/dri/r200/r200_tcl.h deleted file mode 100644 index e36806574fa..00000000000 --- a/src/mesa/drivers/dri/r200/r200_tcl.h +++ /dev/null @@ -1,64 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell <keithw@vmware.com> - */ - -#ifndef __R200_TCL_H__ -#define __R200_TCL_H__ - -#include "r200_context.h" - -extern void r200TclPrimitive( struct gl_context *ctx, GLenum prim, int hw_prim ); -extern void r200EmitEltPrimitive( struct gl_context *ctx, GLuint first, GLuint last, - GLuint flags ); -extern void r200EmitPrimitive( struct gl_context *ctx, GLuint first, GLuint last, - GLuint flags ); - -extern void r200TclFallback( struct gl_context *ctx, GLuint bit, GLboolean mode ); - -#define R200_TCL_FALLBACK_RASTER 0x1 /* rasterization */ -#define R200_TCL_FALLBACK_UNFILLED 0x2 /* unfilled tris */ -#define R200_TCL_FALLBACK_LIGHT_TWOSIDE 0x4 /* twoside tris */ -#define R200_TCL_FALLBACK_MATERIAL 0x8 /* material in vb */ -#define R200_TCL_FALLBACK_TEXGEN_0 0x10 /* texgen, unit 0 */ -#define R200_TCL_FALLBACK_TEXGEN_1 0x20 /* texgen, unit 1 */ -#define R200_TCL_FALLBACK_TEXGEN_2 0x40 /* texgen, unit 2 */ -#define R200_TCL_FALLBACK_TEXGEN_3 0x80 /* texgen, unit 3 */ -#define R200_TCL_FALLBACK_TEXGEN_4 0x100 /* texgen, unit 4 */ -#define R200_TCL_FALLBACK_TEXGEN_5 0x200 /* texgen, unit 5 */ -#define R200_TCL_FALLBACK_TCL_DISABLE 0x400 /* user disable */ -#define R200_TCL_FALLBACK_BITMAP 0x800 /* draw bitmap with points */ -#define R200_TCL_FALLBACK_VERTEX_PROGRAM 0x1000/* vertex program active */ - -#define TCL_FALLBACK( ctx, bit, mode ) r200TclFallback( ctx, bit, mode ) - -#endif diff --git a/src/mesa/drivers/dri/r200/r200_tex.c b/src/mesa/drivers/dri/r200/r200_tex.c deleted file mode 100644 index e4d55b54d2b..00000000000 --- a/src/mesa/drivers/dri/r200/r200_tex.c +++ /dev/null @@ -1,519 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -*/ - -/* - * Authors: - * Keith Whitwell <keithw@vmware.com> - */ - -#include "main/glheader.h" - -#include "main/context.h" -#include "main/enums.h" -#include "main/image.h" -#include "main/teximage.h" -#include "main/texobj.h" -#include "main/samplerobj.h" - -#include "radeon_mipmap_tree.h" -#include "r200_context.h" -#include "r200_ioctl.h" -#include "r200_tex.h" - -#include "util/u_memory.h" -#include "util/driconf.h" - - - -/** - * Set the texture wrap modes. - * - * \param t Texture object whose wrap modes are to be set - * \param swrap Wrap mode for the \a s texture coordinate - * \param twrap Wrap mode for the \a t texture coordinate - */ - -static void r200SetTexWrap( radeonTexObjPtr t, GLenum swrap, GLenum twrap, GLenum rwrap ) -{ - GLboolean is_clamp = GL_FALSE; - GLboolean is_clamp_to_border = GL_FALSE; - struct gl_texture_object *tObj = &t->base; - - radeon_print(RADEON_TEXTURE, RADEON_TRACE, - "%s(tex %p) sw %s, tw %s, rw %s\n", - __func__, t, - _mesa_enum_to_string(swrap), - _mesa_enum_to_string(twrap), - _mesa_enum_to_string(rwrap)); - - t->pp_txfilter &= ~(R200_CLAMP_S_MASK | R200_CLAMP_T_MASK | R200_BORDER_MODE_D3D); - - switch ( swrap ) { - case GL_REPEAT: - t->pp_txfilter |= R200_CLAMP_S_WRAP; - break; - case GL_CLAMP: - t->pp_txfilter |= R200_CLAMP_S_CLAMP_GL; - is_clamp = GL_TRUE; - break; - case GL_CLAMP_TO_EDGE: - t->pp_txfilter |= R200_CLAMP_S_CLAMP_LAST; - break; - case GL_CLAMP_TO_BORDER: - t->pp_txfilter |= R200_CLAMP_S_CLAMP_GL; - is_clamp_to_border = GL_TRUE; - break; - case GL_MIRRORED_REPEAT: - t->pp_txfilter |= R200_CLAMP_S_MIRROR; - break; - case GL_MIRROR_CLAMP_EXT: - t->pp_txfilter |= R200_CLAMP_S_MIRROR_CLAMP_GL; - is_clamp = GL_TRUE; - break; - case GL_MIRROR_CLAMP_TO_EDGE_EXT: - t->pp_txfilter |= R200_CLAMP_S_MIRROR_CLAMP_LAST; - break; - case GL_MIRROR_CLAMP_TO_BORDER_EXT: - t->pp_txfilter |= R200_CLAMP_S_MIRROR_CLAMP_GL; - is_clamp_to_border = GL_TRUE; - break; - default: - _mesa_problem(NULL, "bad S wrap mode in %s", __func__); - } - - if (tObj->Target != GL_TEXTURE_1D) { - switch ( twrap ) { - case GL_REPEAT: - t->pp_txfilter |= R200_CLAMP_T_WRAP; - break; - case GL_CLAMP: - t->pp_txfilter |= R200_CLAMP_T_CLAMP_GL; - is_clamp = GL_TRUE; - break; - case GL_CLAMP_TO_EDGE: - t->pp_txfilter |= R200_CLAMP_T_CLAMP_LAST; - break; - case GL_CLAMP_TO_BORDER: - t->pp_txfilter |= R200_CLAMP_T_CLAMP_GL; - is_clamp_to_border = GL_TRUE; - break; - case GL_MIRRORED_REPEAT: - t->pp_txfilter |= R200_CLAMP_T_MIRROR; - break; - case GL_MIRROR_CLAMP_EXT: - t->pp_txfilter |= R200_CLAMP_T_MIRROR_CLAMP_GL; - is_clamp = GL_TRUE; - break; - case GL_MIRROR_CLAMP_TO_EDGE_EXT: - t->pp_txfilter |= R200_CLAMP_T_MIRROR_CLAMP_LAST; - break; - case GL_MIRROR_CLAMP_TO_BORDER_EXT: - t->pp_txfilter |= R200_CLAMP_T_MIRROR_CLAMP_GL; - is_clamp_to_border = GL_TRUE; - break; - default: - _mesa_problem(NULL, "bad T wrap mode in %s", __func__); - } - } - - t->pp_txformat_x &= ~R200_CLAMP_Q_MASK; - - switch ( rwrap ) { - case GL_REPEAT: - t->pp_txformat_x |= R200_CLAMP_Q_WRAP; - break; - case GL_CLAMP: - t->pp_txformat_x |= R200_CLAMP_Q_CLAMP_GL; - is_clamp = GL_TRUE; - break; - case GL_CLAMP_TO_EDGE: - t->pp_txformat_x |= R200_CLAMP_Q_CLAMP_LAST; - break; - case GL_CLAMP_TO_BORDER: - t->pp_txformat_x |= R200_CLAMP_Q_CLAMP_GL; - is_clamp_to_border = GL_TRUE; - break; - case GL_MIRRORED_REPEAT: - t->pp_txformat_x |= R200_CLAMP_Q_MIRROR; - break; - case GL_MIRROR_CLAMP_EXT: - t->pp_txformat_x |= R200_CLAMP_Q_MIRROR_CLAMP_GL; - is_clamp = GL_TRUE; - break; - case GL_MIRROR_CLAMP_TO_EDGE_EXT: - t->pp_txformat_x |= R200_CLAMP_Q_MIRROR_CLAMP_LAST; - break; - case GL_MIRROR_CLAMP_TO_BORDER_EXT: - t->pp_txformat_x |= R200_CLAMP_Q_MIRROR_CLAMP_GL; - is_clamp_to_border = GL_TRUE; - break; - default: - _mesa_problem(NULL, "bad R wrap mode in %s", __func__); - } - - if ( is_clamp_to_border ) { - t->pp_txfilter |= R200_BORDER_MODE_D3D; - } - - t->border_fallback = (is_clamp && is_clamp_to_border); -} - -static void r200SetTexMaxAnisotropy( radeonTexObjPtr t, GLfloat max ) -{ - t->pp_txfilter &= ~R200_MAX_ANISO_MASK; - radeon_print(RADEON_TEXTURE, RADEON_TRACE, - "%s(tex %p) max %f.\n", - __func__, t, max); - - if ( max <= 1.0 ) { - t->pp_txfilter |= R200_MAX_ANISO_1_TO_1; - } else if ( max <= 2.0 ) { - t->pp_txfilter |= R200_MAX_ANISO_2_TO_1; - } else if ( max <= 4.0 ) { - t->pp_txfilter |= R200_MAX_ANISO_4_TO_1; - } else if ( max <= 8.0 ) { - t->pp_txfilter |= R200_MAX_ANISO_8_TO_1; - } else { - t->pp_txfilter |= R200_MAX_ANISO_16_TO_1; - } -} - -/** - * Set the texture magnification and minification modes. - * - * \param t Texture whose filter modes are to be set - * \param minf Texture minification mode - * \param magf Texture magnification mode - */ - -static void r200SetTexFilter( radeonTexObjPtr t, GLenum minf, GLenum magf ) -{ - GLuint anisotropy = (t->pp_txfilter & R200_MAX_ANISO_MASK); - - /* Force revalidation to account for switches from/to mipmapping. */ - t->validated = GL_FALSE; - - t->pp_txfilter &= ~(R200_MIN_FILTER_MASK | R200_MAG_FILTER_MASK); - t->pp_txformat_x &= ~R200_VOLUME_FILTER_MASK; - - radeon_print(RADEON_TEXTURE, RADEON_TRACE, - "%s(tex %p) minf %s, maxf %s, anisotropy %d.\n", - __func__, t, - _mesa_enum_to_string(minf), - _mesa_enum_to_string(magf), - anisotropy); - - if ( anisotropy == R200_MAX_ANISO_1_TO_1 ) { - switch ( minf ) { - case GL_NEAREST: - t->pp_txfilter |= R200_MIN_FILTER_NEAREST; - break; - case GL_LINEAR: - t->pp_txfilter |= R200_MIN_FILTER_LINEAR; - break; - case GL_NEAREST_MIPMAP_NEAREST: - t->pp_txfilter |= R200_MIN_FILTER_NEAREST_MIP_NEAREST; - break; - case GL_NEAREST_MIPMAP_LINEAR: - t->pp_txfilter |= R200_MIN_FILTER_LINEAR_MIP_NEAREST; - break; - case GL_LINEAR_MIPMAP_NEAREST: - t->pp_txfilter |= R200_MIN_FILTER_NEAREST_MIP_LINEAR; - break; - case GL_LINEAR_MIPMAP_LINEAR: - t->pp_txfilter |= R200_MIN_FILTER_LINEAR_MIP_LINEAR; - break; - } - } else { - switch ( minf ) { - case GL_NEAREST: - t->pp_txfilter |= R200_MIN_FILTER_ANISO_NEAREST; - break; - case GL_LINEAR: - t->pp_txfilter |= R200_MIN_FILTER_ANISO_LINEAR; - break; - case GL_NEAREST_MIPMAP_NEAREST: - case GL_LINEAR_MIPMAP_NEAREST: - t->pp_txfilter |= R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST; - break; - case GL_NEAREST_MIPMAP_LINEAR: - case GL_LINEAR_MIPMAP_LINEAR: - t->pp_txfilter |= R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR; - break; - } - } - - /* Note we don't have 3D mipmaps so only use the mag filter setting - * to set the 3D texture filter mode. - */ - switch ( magf ) { - case GL_NEAREST: - t->pp_txfilter |= R200_MAG_FILTER_NEAREST; - t->pp_txformat_x |= R200_VOLUME_FILTER_NEAREST; - break; - case GL_LINEAR: - t->pp_txfilter |= R200_MAG_FILTER_LINEAR; - t->pp_txformat_x |= R200_VOLUME_FILTER_LINEAR; - break; - } -} - -static void r200SetTexBorderColor( radeonTexObjPtr t, const GLfloat color[4] ) -{ - GLubyte c[4]; - CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]); - CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]); - CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]); - CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]); - t->pp_border_color = radeonPackColor( 4, c[0], c[1], c[2], c[3] ); -} - -static void r200TexEnv( struct gl_context *ctx, GLenum target, - GLenum pname, const GLfloat *param ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint unit = ctx->Texture.CurrentUnit; - struct gl_fixedfunc_texture_unit *texUnit = - &ctx->Texture.FixedFuncUnit[unit]; - - radeon_print(RADEON_TEXTURE | RADEON_STATE, RADEON_VERBOSE, "%s( %s )\n", - __func__, _mesa_enum_to_string( pname ) ); - - /* This is incorrect: Need to maintain this data for each of - * GL_TEXTURE_{123}D, GL_TEXTURE_RECTANGLE_NV, etc, and switch - * between them according to _Current->Target. - */ - switch ( pname ) { - case GL_TEXTURE_ENV_COLOR: { - GLubyte c[4]; - GLuint envColor; - _mesa_unclamped_float_rgba_to_ubyte(c, texUnit->EnvColor); - envColor = radeonPackColor( 4, c[0], c[1], c[2], c[3] ); - if ( rmesa->hw.tf.cmd[TF_TFACTOR_0 + unit] != envColor ) { - R200_STATECHANGE( rmesa, tf ); - rmesa->hw.tf.cmd[TF_TFACTOR_0 + unit] = envColor; - } - break; - } - - case GL_TEXTURE_LOD_BIAS_EXT: { - GLfloat bias, min; - GLuint b; - const int fixed_one = R200_LOD_BIAS_FIXED_ONE; - - /* The R200's LOD bias is a signed 2's complement value with a - * range of -16.0 <= bias < 16.0. - * - * NOTE: Add a small bias to the bias for conform mipsel.c test. - */ - bias = *param; - min = driQueryOptionb (&rmesa->radeon.optionCache, "no_neg_lod_bias") ? - 0.0 : -16.0; - bias = CLAMP( bias, min, 16.0 ); - b = ((int)(bias * fixed_one) - + R200_LOD_BIAS_CORRECTION) & R200_LOD_BIAS_MASK; - - if ( (rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT_X] & R200_LOD_BIAS_MASK) != b ) { - R200_STATECHANGE( rmesa, tex[unit] ); - rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT_X] &= ~R200_LOD_BIAS_MASK; - rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT_X] |= b; - } - break; - } - case GL_COORD_REPLACE_ARB: - if (ctx->Point.PointSprite) { - R200_STATECHANGE( rmesa, spr ); - if ((GLenum)param[0]) { - rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] |= R200_PS_GEN_TEX_0 << unit; - } else { - rmesa->hw.spr.cmd[SPR_POINT_SPRITE_CNTL] &= ~(R200_PS_GEN_TEX_0 << unit); - } - } - break; - default: - return; - } -} - -void r200TexUpdateParameters(struct gl_context *ctx, GLuint unit) -{ - struct gl_sampler_object *samp = _mesa_get_samplerobj(ctx, unit); - radeonTexObj* t = radeon_tex_obj(ctx->Texture.Unit[unit]._Current); - - r200SetTexMaxAnisotropy(t , samp->Attrib.MaxAnisotropy); - r200SetTexFilter(t, samp->Attrib.MinFilter, samp->Attrib.MagFilter); - r200SetTexWrap(t, samp->Attrib.WrapS, samp->Attrib.WrapT, samp->Attrib.WrapR); - r200SetTexBorderColor(t, samp->Attrib.state.border_color.f); -} - -/** - * Changes variables and flags for a state update, which will happen at the - * next UpdateTextureState - */ -static void r200TexParameter(struct gl_context *ctx, - struct gl_texture_object *texObj, - GLenum pname) -{ - radeonTexObj* t = radeon_tex_obj(texObj); - - radeon_print(RADEON_TEXTURE | RADEON_STATE, RADEON_VERBOSE, - "%s(%p, tex %p) pname %s\n", - __func__, ctx, texObj, - _mesa_enum_to_string( pname ) ); - - switch ( pname ) { - case GL_ALL_ATTRIB_BITS: /* meaning is all pnames, internal */ - case GL_TEXTURE_MIN_FILTER: - case GL_TEXTURE_MAG_FILTER: - case GL_TEXTURE_MAX_ANISOTROPY_EXT: - case GL_TEXTURE_WRAP_S: - case GL_TEXTURE_WRAP_T: - case GL_TEXTURE_WRAP_R: - case GL_TEXTURE_BORDER_COLOR: - case GL_TEXTURE_BASE_LEVEL: - case GL_TEXTURE_MAX_LEVEL: - case GL_TEXTURE_MIN_LOD: - case GL_TEXTURE_MAX_LOD: - t->validated = GL_FALSE; - break; - - default: - return; - } -} - - -static void r200DeleteTexture(struct gl_context * ctx, struct gl_texture_object *texObj) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - radeonTexObj* t = radeon_tex_obj(texObj); - - radeon_print(RADEON_TEXTURE | RADEON_STATE, RADEON_NORMAL, - "%s( %p (target = %s) )\n", __func__, - (void *)texObj, - _mesa_enum_to_string(texObj->Target)); - - if (rmesa) { - int i; - radeon_firevertices(&rmesa->radeon); - for ( i = 0 ; i < rmesa->radeon.glCtx.Const.MaxTextureUnits ; i++ ) { - if ( t == rmesa->state.texture.unit[i].texobj ) { - rmesa->state.texture.unit[i].texobj = NULL; - rmesa->hw.tex[i].dirty = GL_FALSE; - rmesa->hw.cube[i].dirty = GL_FALSE; - } - } - } - - radeon_miptree_unreference(&t->mt); - - _mesa_delete_texture_object(ctx, texObj); -} - -/* Need: - * - Same GEN_MODE for all active bits - * - Same EyePlane/ObjPlane for all active bits when using Eye/Obj - * - STRQ presumably all supported (matrix means incoming R values - * can end up in STQ, this has implications for vertex support, - * presumably ok if maos is used, though?) - * - * Basically impossible to do this on the fly - just collect some - * basic info & do the checks from ValidateState(). - */ -static void r200TexGen( struct gl_context *ctx, - GLenum coord, - GLenum pname, - const GLfloat *params ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint unit = ctx->Texture.CurrentUnit; - rmesa->recheck_texgen[unit] = GL_TRUE; -} - - -/** - * Allocate a new texture object. - * Called via ctx->Driver.NewTextureObject. - * Note: this function will be called during context creation to - * allocate the default texture objects. - * Fixup MaxAnisotropy according to user preference. - */ -static struct gl_texture_object *r200NewTextureObject(struct gl_context * ctx, - GLuint name, - GLenum target) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj); - - - radeon_print(RADEON_STATE | RADEON_TEXTURE, RADEON_NORMAL, - "%s(%p) target %s, new texture %p.\n", - __func__, ctx, - _mesa_enum_to_string(target), t); - - _mesa_initialize_texture_object(ctx, &t->base, name, target); - t->base.Sampler.Attrib.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy; - - /* Initialize hardware state */ - r200SetTexWrap( t, t->base.Sampler.Attrib.WrapS, t->base.Sampler.Attrib.WrapT, t->base.Sampler.Attrib.WrapR ); - r200SetTexMaxAnisotropy( t, t->base.Sampler.Attrib.MaxAnisotropy ); - r200SetTexFilter(t, t->base.Sampler.Attrib.MinFilter, t->base.Sampler.Attrib.MagFilter); - r200SetTexBorderColor(t, t->base.Sampler.Attrib.state.border_color.f); - - return &t->base; -} - -static struct gl_sampler_object * -r200NewSamplerObject(struct gl_context *ctx, GLuint name) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - struct gl_sampler_object *samp = _mesa_new_sampler_object(ctx, name); - if (samp) - samp->Attrib.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy; - return samp; -} - - - -void r200InitTextureFuncs( radeonContextPtr radeon, struct dd_function_table *functions ) -{ - /* Note: we only plug in the functions we implement in the driver - * since _mesa_init_driver_functions() was already called. - */ - - radeon_init_common_texture_funcs(radeon, functions); - - functions->NewTextureObject = r200NewTextureObject; - // functions->BindTexture = r200BindTexture; - functions->DeleteTexture = r200DeleteTexture; - - functions->TexEnv = r200TexEnv; - functions->TexParameter = r200TexParameter; - functions->TexGen = r200TexGen; - functions->NewSamplerObject = r200NewSamplerObject; -} diff --git a/src/mesa/drivers/dri/r200/r200_tex.h b/src/mesa/drivers/dri/r200/r200_tex.h deleted file mode 100644 index c13998df03b..00000000000 --- a/src/mesa/drivers/dri/r200/r200_tex.h +++ /dev/null @@ -1,121 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell <keithw@vmware.com> - */ - -#ifndef __R200_TEX_H__ -#define __R200_TEX_H__ - -extern void r200SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv); -extern void r200SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, - __DRIdrawable *dPriv); - -extern void r200UpdateTextureState( struct gl_context *ctx ); - -extern int r200UploadTexImages( r200ContextPtr rmesa, radeonTexObjPtr t, GLuint face ); - -extern void r200DestroyTexObj( r200ContextPtr rmesa, radeonTexObjPtr t ); - -extern void r200InitTextureFuncs( radeonContextPtr radeon, struct dd_function_table *functions ); - -extern void r200UpdateFragmentShader( struct gl_context *ctx ); -extern void r200TexUpdateParameters(struct gl_context *ctx, GLuint unit); - -extern void set_re_cntl_d3d( struct gl_context *ctx, int unit, GLboolean use_d3d ); - -struct tx_table { - GLuint format, filter; -}; - -/* Note the tables (have to) contain invalid entries (if they are only valid - * for either be/le) */ -static const struct tx_table tx_table_be[] = -{ - [ MESA_FORMAT_A8B8G8R8_UNORM ] = { R200_TXFORMAT_ABGR8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_R8G8B8A8_UNORM ] = { R200_TXFORMAT_RGBA8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_B8G8R8A8_UNORM ] = { R200_TXFORMAT_ARGB8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_B8G8R8X8_UNORM ] = { R200_TXFORMAT_ARGB8888, 0 }, - [ MESA_FORMAT_A8R8G8B8_UNORM ] = { R200_TXFORMAT_ARGB8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_X8R8G8B8_UNORM ] = { R200_TXFORMAT_ARGB8888, 0 }, - [ MESA_FORMAT_BGR_UNORM8 ] = { 0xffffffff, 0 }, - [ MESA_FORMAT_B5G6R5_UNORM ] = { R200_TXFORMAT_RGB565, 0 }, - [ MESA_FORMAT_R5G6B5_UNORM ] = { R200_TXFORMAT_RGB565, 0 }, - [ MESA_FORMAT_B4G4R4A4_UNORM ] = { R200_TXFORMAT_ARGB4444 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_A4R4G4B4_UNORM ] = { R200_TXFORMAT_ARGB4444 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_B5G5R5A1_UNORM ] = { R200_TXFORMAT_ARGB1555 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_A1R5G5B5_UNORM ] = { R200_TXFORMAT_ARGB1555 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_A_UNORM8 ] = { R200_TXFORMAT_I8 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_L_UNORM8 ] = { R200_TXFORMAT_I8, 0 }, - [ MESA_FORMAT_LA_UNORM8 ] = { R200_TXFORMAT_AI88 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_I_UNORM8 ] = { R200_TXFORMAT_I8 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_YCBCR ] = { R200_TXFORMAT_YVYU422, R200_YUV_TO_RGB }, - [ MESA_FORMAT_YCBCR_REV ] = { R200_TXFORMAT_VYUY422, R200_YUV_TO_RGB }, - [ MESA_FORMAT_RGB_FXT1 ] = { 0xffffffff, 0 }, - [ MESA_FORMAT_RGBA_FXT1 ] = { 0xffffffff, 0 }, - [ MESA_FORMAT_RGB_DXT1 ] = { R200_TXFORMAT_DXT1, 0 }, - [ MESA_FORMAT_RGBA_DXT1 ] = { R200_TXFORMAT_DXT1 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_RGBA_DXT3 ] = { R200_TXFORMAT_DXT23 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_RGBA_DXT5 ] = { R200_TXFORMAT_DXT45 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, -}; - -static const struct tx_table tx_table_le[] = -{ - [ MESA_FORMAT_A8B8G8R8_UNORM ] = { R200_TXFORMAT_RGBA8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_R8G8B8A8_UNORM ] = { R200_TXFORMAT_ABGR8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_B8G8R8A8_UNORM ] = { R200_TXFORMAT_ARGB8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_B8G8R8X8_UNORM ] = { R200_TXFORMAT_ARGB8888, 0 }, - [ MESA_FORMAT_A8R8G8B8_UNORM ] = { R200_TXFORMAT_ARGB8888 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_X8R8G8B8_UNORM ] = { R200_TXFORMAT_ARGB8888, 0 }, - [ MESA_FORMAT_BGR_UNORM8 ] = { R200_TXFORMAT_ARGB8888, 0 }, - [ MESA_FORMAT_B5G6R5_UNORM ] = { R200_TXFORMAT_RGB565, 0 }, - [ MESA_FORMAT_R5G6B5_UNORM ] = { R200_TXFORMAT_RGB565, 0 }, - [ MESA_FORMAT_B4G4R4A4_UNORM ] = { R200_TXFORMAT_ARGB4444 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_A4R4G4B4_UNORM ] = { R200_TXFORMAT_ARGB4444 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_B5G5R5A1_UNORM ] = { R200_TXFORMAT_ARGB1555 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_A1R5G5B5_UNORM ] = { R200_TXFORMAT_ARGB1555 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_A_UNORM8 ] = { R200_TXFORMAT_I8 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_L_UNORM8 ] = { R200_TXFORMAT_I8, 0 }, - [ MESA_FORMAT_LA_UNORM8 ] = { R200_TXFORMAT_AI88 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_I_UNORM8 ] = { R200_TXFORMAT_I8 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_YCBCR ] = { R200_TXFORMAT_YVYU422, R200_YUV_TO_RGB }, - [ MESA_FORMAT_YCBCR_REV ] = { R200_TXFORMAT_VYUY422, R200_YUV_TO_RGB }, - [ MESA_FORMAT_RGB_FXT1 ] = { 0xffffffff, 0 }, - [ MESA_FORMAT_RGBA_FXT1 ] = { 0xffffffff, 0 }, - [ MESA_FORMAT_RGB_DXT1 ] = { R200_TXFORMAT_DXT1, 0 }, - [ MESA_FORMAT_RGBA_DXT1 ] = { R200_TXFORMAT_DXT1 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_RGBA_DXT3 ] = { R200_TXFORMAT_DXT23 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, - [ MESA_FORMAT_RGBA_DXT5 ] = { R200_TXFORMAT_DXT45 | R200_TXFORMAT_ALPHA_IN_MAP, 0 }, -}; - - - -#endif /* __R200_TEX_H__ */ diff --git a/src/mesa/drivers/dri/r200/r200_texstate.c b/src/mesa/drivers/dri/r200/r200_texstate.c deleted file mode 100644 index f8e45e12b63..00000000000 --- a/src/mesa/drivers/dri/r200/r200_texstate.c +++ /dev/null @@ -1,1622 +0,0 @@ -/* -Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. - -The Weather Channel (TM) funded Tungsten Graphics to develop the -initial release of the Radeon 8500 driver under the XFree86 license. -This notice must be preserved. - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Keith Whitwell <keithw@vmware.com> - */ - -#include "main/glheader.h" - -#include "main/context.h" -#include "main/macros.h" -#include "main/state.h" -#include "main/teximage.h" -#include "main/texobj.h" -#include "main/enums.h" - -#include "radeon_common.h" -#include "radeon_mipmap_tree.h" -#include "r200_context.h" -#include "r200_state.h" -#include "r200_ioctl.h" -#include "r200_swtcl.h" -#include "r200_tex.h" -#include "r200_tcl.h" - -#define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5) \ - && (tx_table_be[f].format != 0xffffffff) ) - -/* ================================================================ - * Texture combine functions - */ - -/* GL_ARB_texture_env_combine support - */ - -/* The color tables have combine functions for GL_SRC_COLOR, - * GL_ONE_MINUS_SRC_COLOR, GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA. - */ -static GLuint r200_register_color[][R200_MAX_TEXTURE_UNITS] = -{ - { - R200_TXC_ARG_A_R0_COLOR, - R200_TXC_ARG_A_R1_COLOR, - R200_TXC_ARG_A_R2_COLOR, - R200_TXC_ARG_A_R3_COLOR, - R200_TXC_ARG_A_R4_COLOR, - R200_TXC_ARG_A_R5_COLOR - }, - { - R200_TXC_ARG_A_R0_COLOR | R200_TXC_COMP_ARG_A, - R200_TXC_ARG_A_R1_COLOR | R200_TXC_COMP_ARG_A, - R200_TXC_ARG_A_R2_COLOR | R200_TXC_COMP_ARG_A, - R200_TXC_ARG_A_R3_COLOR | R200_TXC_COMP_ARG_A, - R200_TXC_ARG_A_R4_COLOR | R200_TXC_COMP_ARG_A, - R200_TXC_ARG_A_R5_COLOR | R200_TXC_COMP_ARG_A - }, - { - R200_TXC_ARG_A_R0_ALPHA, - R200_TXC_ARG_A_R1_ALPHA, - R200_TXC_ARG_A_R2_ALPHA, - R200_TXC_ARG_A_R3_ALPHA, - R200_TXC_ARG_A_R4_ALPHA, - R200_TXC_ARG_A_R5_ALPHA - }, - { - R200_TXC_ARG_A_R0_ALPHA | R200_TXC_COMP_ARG_A, - R200_TXC_ARG_A_R1_ALPHA | R200_TXC_COMP_ARG_A, - R200_TXC_ARG_A_R2_ALPHA | R200_TXC_COMP_ARG_A, - R200_TXC_ARG_A_R3_ALPHA | R200_TXC_COMP_ARG_A, - R200_TXC_ARG_A_R4_ALPHA | R200_TXC_COMP_ARG_A, - R200_TXC_ARG_A_R5_ALPHA | R200_TXC_COMP_ARG_A - }, -}; - -static GLuint r200_tfactor_color[] = -{ - R200_TXC_ARG_A_TFACTOR_COLOR, - R200_TXC_ARG_A_TFACTOR_COLOR | R200_TXC_COMP_ARG_A, - R200_TXC_ARG_A_TFACTOR_ALPHA, - R200_TXC_ARG_A_TFACTOR_ALPHA | R200_TXC_COMP_ARG_A -}; - -static GLuint r200_tfactor1_color[] = -{ - R200_TXC_ARG_A_TFACTOR1_COLOR, - R200_TXC_ARG_A_TFACTOR1_COLOR | R200_TXC_COMP_ARG_A, - R200_TXC_ARG_A_TFACTOR1_ALPHA, - R200_TXC_ARG_A_TFACTOR1_ALPHA | R200_TXC_COMP_ARG_A -}; - -static GLuint r200_primary_color[] = -{ - R200_TXC_ARG_A_DIFFUSE_COLOR, - R200_TXC_ARG_A_DIFFUSE_COLOR | R200_TXC_COMP_ARG_A, - R200_TXC_ARG_A_DIFFUSE_ALPHA, - R200_TXC_ARG_A_DIFFUSE_ALPHA | R200_TXC_COMP_ARG_A -}; - -/* GL_ZERO table - indices 0-3 - * GL_ONE table - indices 1-4 - */ -static GLuint r200_zero_color[] = -{ - R200_TXC_ARG_A_ZERO, - R200_TXC_ARG_A_ZERO | R200_TXC_COMP_ARG_A, - R200_TXC_ARG_A_ZERO, - R200_TXC_ARG_A_ZERO | R200_TXC_COMP_ARG_A, - R200_TXC_ARG_A_ZERO -}; - -/* The alpha tables only have GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA. - */ -static GLuint r200_register_alpha[][R200_MAX_TEXTURE_UNITS] = -{ - { - R200_TXA_ARG_A_R0_ALPHA, - R200_TXA_ARG_A_R1_ALPHA, - R200_TXA_ARG_A_R2_ALPHA, - R200_TXA_ARG_A_R3_ALPHA, - R200_TXA_ARG_A_R4_ALPHA, - R200_TXA_ARG_A_R5_ALPHA - }, - { - R200_TXA_ARG_A_R0_ALPHA | R200_TXA_COMP_ARG_A, - R200_TXA_ARG_A_R1_ALPHA | R200_TXA_COMP_ARG_A, - R200_TXA_ARG_A_R2_ALPHA | R200_TXA_COMP_ARG_A, - R200_TXA_ARG_A_R3_ALPHA | R200_TXA_COMP_ARG_A, - R200_TXA_ARG_A_R4_ALPHA | R200_TXA_COMP_ARG_A, - R200_TXA_ARG_A_R5_ALPHA | R200_TXA_COMP_ARG_A - }, -}; - -static GLuint r200_tfactor_alpha[] = -{ - R200_TXA_ARG_A_TFACTOR_ALPHA, - R200_TXA_ARG_A_TFACTOR_ALPHA | R200_TXA_COMP_ARG_A -}; - -static GLuint r200_tfactor1_alpha[] = -{ - R200_TXA_ARG_A_TFACTOR1_ALPHA, - R200_TXA_ARG_A_TFACTOR1_ALPHA | R200_TXA_COMP_ARG_A -}; - -static GLuint r200_primary_alpha[] = -{ - R200_TXA_ARG_A_DIFFUSE_ALPHA, - R200_TXA_ARG_A_DIFFUSE_ALPHA | R200_TXA_COMP_ARG_A -}; - -/* GL_ZERO table - indices 0-1 - * GL_ONE table - indices 1-2 - */ -static GLuint r200_zero_alpha[] = -{ - R200_TXA_ARG_A_ZERO, - R200_TXA_ARG_A_ZERO | R200_TXA_COMP_ARG_A, - R200_TXA_ARG_A_ZERO, -}; - - -/* Extract the arg from slot A, shift it into the correct argument slot - * and set the corresponding complement bit. - */ -#define R200_COLOR_ARG( n, arg ) \ -do { \ - color_combine |= \ - ((color_arg[n] & R200_TXC_ARG_A_MASK) \ - << R200_TXC_ARG_##arg##_SHIFT); \ - color_combine |= \ - ((color_arg[n] >> R200_TXC_COMP_ARG_A_SHIFT) \ - << R200_TXC_COMP_ARG_##arg##_SHIFT); \ -} while (0) - -#define R200_ALPHA_ARG( n, arg ) \ -do { \ - alpha_combine |= \ - ((alpha_arg[n] & R200_TXA_ARG_A_MASK) \ - << R200_TXA_ARG_##arg##_SHIFT); \ - alpha_combine |= \ - ((alpha_arg[n] >> R200_TXA_COMP_ARG_A_SHIFT) \ - << R200_TXA_COMP_ARG_##arg##_SHIFT); \ -} while (0) - - -/* ================================================================ - * Texture unit state management - */ - -static GLboolean r200UpdateTextureEnv( struct gl_context *ctx, int unit, int slot, GLuint replaceargs ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - const struct gl_texture_unit *rtexUnit = &ctx->Texture.Unit[unit]; - const struct gl_fixedfunc_texture_unit *texUnit = - &ctx->Texture.FixedFuncUnit[unit]; - GLuint color_combine, alpha_combine; - GLuint color_scale = rmesa->hw.pix[slot].cmd[PIX_PP_TXCBLEND2] & - ~(R200_TXC_SCALE_MASK | R200_TXC_OUTPUT_REG_MASK | R200_TXC_TFACTOR_SEL_MASK | - R200_TXC_TFACTOR1_SEL_MASK); - GLuint alpha_scale = rmesa->hw.pix[slot].cmd[PIX_PP_TXABLEND2] & - ~(R200_TXA_DOT_ALPHA | R200_TXA_SCALE_MASK | R200_TXA_OUTPUT_REG_MASK | - R200_TXA_TFACTOR_SEL_MASK | R200_TXA_TFACTOR1_SEL_MASK); - - if ( R200_DEBUG & RADEON_TEXTURE ) { - fprintf( stderr, "%s( %p, %d )\n", __func__, (void *)ctx, unit ); - } - - /* Set the texture environment state. Isn't this nice and clean? - * The chip will automagically set the texture alpha to 0xff when - * the texture format does not include an alpha component. This - * reduces the amount of special-casing we have to do, alpha-only - * textures being a notable exception. - */ - - color_scale |= ((rmesa->state.texture.unit[unit].outputreg + 1) << R200_TXC_OUTPUT_REG_SHIFT) | - (unit << R200_TXC_TFACTOR_SEL_SHIFT) | - (replaceargs << R200_TXC_TFACTOR1_SEL_SHIFT); - alpha_scale |= ((rmesa->state.texture.unit[unit].outputreg + 1) << R200_TXA_OUTPUT_REG_SHIFT) | - (unit << R200_TXA_TFACTOR_SEL_SHIFT) | - (replaceargs << R200_TXA_TFACTOR1_SEL_SHIFT); - - if ( !rtexUnit->_Current ) { - assert( unit == 0); - color_combine = R200_TXC_ARG_A_ZERO | R200_TXC_ARG_B_ZERO - | R200_TXC_ARG_C_DIFFUSE_COLOR | R200_TXC_OP_MADD; - alpha_combine = R200_TXA_ARG_A_ZERO | R200_TXA_ARG_B_ZERO - | R200_TXA_ARG_C_DIFFUSE_ALPHA | R200_TXA_OP_MADD; - } - else { - GLuint color_arg[3], alpha_arg[3]; - GLuint i; - const GLuint numColorArgs = texUnit->_CurrentCombine->_NumArgsRGB; - const GLuint numAlphaArgs = texUnit->_CurrentCombine->_NumArgsA; - GLuint RGBshift = texUnit->_CurrentCombine->ScaleShiftRGB; - GLuint Ashift = texUnit->_CurrentCombine->ScaleShiftA; - - - const GLint replaceoprgb = - ctx->Texture.FixedFuncUnit[replaceargs]._CurrentCombine->OperandRGB[0] - GL_SRC_COLOR; - const GLint replaceopa = - ctx->Texture.FixedFuncUnit[replaceargs]._CurrentCombine->OperandA[0] - GL_SRC_ALPHA; - - /* Step 1: - * Extract the color and alpha combine function arguments. - */ - for ( i = 0 ; i < numColorArgs ; i++ ) { - GLint op = texUnit->_CurrentCombine->OperandRGB[i] - GL_SRC_COLOR; - const GLint srcRGBi = texUnit->_CurrentCombine->SourceRGB[i]; - assert(op >= 0); - assert(op <= 3); - switch ( srcRGBi ) { - case GL_TEXTURE: - color_arg[i] = r200_register_color[op][unit]; - break; - case GL_CONSTANT: - color_arg[i] = r200_tfactor_color[op]; - break; - case GL_PRIMARY_COLOR: - color_arg[i] = r200_primary_color[op]; - break; - case GL_PREVIOUS: - if (replaceargs != unit) { - const GLint srcRGBreplace = - ctx->Texture.FixedFuncUnit[replaceargs]._CurrentCombine->SourceRGB[0]; - if (op >= 2) { - op = op ^ replaceopa; - } - else { - op = op ^ replaceoprgb; - } - switch (srcRGBreplace) { - case GL_TEXTURE: - color_arg[i] = r200_register_color[op][replaceargs]; - break; - case GL_CONSTANT: - color_arg[i] = r200_tfactor1_color[op]; - break; - case GL_PRIMARY_COLOR: - color_arg[i] = r200_primary_color[op]; - break; - case GL_PREVIOUS: - if (slot == 0) - color_arg[i] = r200_primary_color[op]; - else - color_arg[i] = r200_register_color[op] - [rmesa->state.texture.unit[replaceargs - 1].outputreg]; - break; - case GL_ZERO: - color_arg[i] = r200_zero_color[op]; - break; - case GL_ONE: - color_arg[i] = r200_zero_color[op+1]; - break; - case GL_TEXTURE0: - case GL_TEXTURE1: - case GL_TEXTURE2: - case GL_TEXTURE3: - case GL_TEXTURE4: - case GL_TEXTURE5: - color_arg[i] = r200_register_color[op][srcRGBreplace - GL_TEXTURE0]; - break; - default: - return GL_FALSE; - } - } - else { - if (slot == 0) - color_arg[i] = r200_primary_color[op]; - else - color_arg[i] = r200_register_color[op] - [rmesa->state.texture.unit[unit - 1].outputreg]; - } - break; - case GL_ZERO: - color_arg[i] = r200_zero_color[op]; - break; - case GL_ONE: - color_arg[i] = r200_zero_color[op+1]; - break; - case GL_TEXTURE0: - case GL_TEXTURE1: - case GL_TEXTURE2: - case GL_TEXTURE3: - case GL_TEXTURE4: - case GL_TEXTURE5: - color_arg[i] = r200_register_color[op][srcRGBi - GL_TEXTURE0]; - break; - default: - return GL_FALSE; - } - } - - for ( i = 0 ; i < numAlphaArgs ; i++ ) { - GLint op = texUnit->_CurrentCombine->OperandA[i] - GL_SRC_ALPHA; - const GLint srcAi = texUnit->_CurrentCombine->SourceA[i]; - assert(op >= 0); - assert(op <= 1); - switch ( srcAi ) { - case GL_TEXTURE: - alpha_arg[i] = r200_register_alpha[op][unit]; - break; - case GL_CONSTANT: - alpha_arg[i] = r200_tfactor_alpha[op]; - break; - case GL_PRIMARY_COLOR: - alpha_arg[i] = r200_primary_alpha[op]; - break; - case GL_PREVIOUS: - if (replaceargs != unit) { - const GLint srcAreplace = - ctx->Texture.FixedFuncUnit[replaceargs]._CurrentCombine->SourceA[0]; - op = op ^ replaceopa; - switch (srcAreplace) { - case GL_TEXTURE: - alpha_arg[i] = r200_register_alpha[op][replaceargs]; - break; - case GL_CONSTANT: - alpha_arg[i] = r200_tfactor1_alpha[op]; - break; - case GL_PRIMARY_COLOR: - alpha_arg[i] = r200_primary_alpha[op]; - break; - case GL_PREVIOUS: - if (slot == 0) - alpha_arg[i] = r200_primary_alpha[op]; - else - alpha_arg[i] = r200_register_alpha[op] - [rmesa->state.texture.unit[replaceargs - 1].outputreg]; - break; - case GL_ZERO: - alpha_arg[i] = r200_zero_alpha[op]; - break; - case GL_ONE: - alpha_arg[i] = r200_zero_alpha[op+1]; - break; - case GL_TEXTURE0: - case GL_TEXTURE1: - case GL_TEXTURE2: - case GL_TEXTURE3: - case GL_TEXTURE4: - case GL_TEXTURE5: - alpha_arg[i] = r200_register_alpha[op][srcAreplace - GL_TEXTURE0]; - break; - default: - return GL_FALSE; - } - } - else { - if (slot == 0) - alpha_arg[i] = r200_primary_alpha[op]; - else - alpha_arg[i] = r200_register_alpha[op] - [rmesa->state.texture.unit[unit - 1].outputreg]; - } - break; - case GL_ZERO: - alpha_arg[i] = r200_zero_alpha[op]; - break; - case GL_ONE: - alpha_arg[i] = r200_zero_alpha[op+1]; - break; - case GL_TEXTURE0: - case GL_TEXTURE1: - case GL_TEXTURE2: - case GL_TEXTURE3: - case GL_TEXTURE4: - case GL_TEXTURE5: - alpha_arg[i] = r200_register_alpha[op][srcAi - GL_TEXTURE0]; - break; - default: - return GL_FALSE; - } - } - - /* Step 2: - * Build up the color and alpha combine functions. - */ - switch ( texUnit->_CurrentCombine->ModeRGB ) { - case GL_REPLACE: - color_combine = (R200_TXC_ARG_A_ZERO | - R200_TXC_ARG_B_ZERO | - R200_TXC_OP_MADD); - R200_COLOR_ARG( 0, C ); - break; - case GL_MODULATE: - color_combine = (R200_TXC_ARG_C_ZERO | - R200_TXC_OP_MADD); - R200_COLOR_ARG( 0, A ); - R200_COLOR_ARG( 1, B ); - break; - case GL_ADD: - color_combine = (R200_TXC_ARG_B_ZERO | - R200_TXC_COMP_ARG_B | - R200_TXC_OP_MADD); - R200_COLOR_ARG( 0, A ); - R200_COLOR_ARG( 1, C ); - break; - case GL_ADD_SIGNED: - color_combine = (R200_TXC_ARG_B_ZERO | - R200_TXC_COMP_ARG_B | - R200_TXC_BIAS_ARG_C | /* new */ - R200_TXC_OP_MADD); /* was ADDSIGNED */ - R200_COLOR_ARG( 0, A ); - R200_COLOR_ARG( 1, C ); - break; - case GL_SUBTRACT: - color_combine = (R200_TXC_ARG_B_ZERO | - R200_TXC_COMP_ARG_B | - R200_TXC_NEG_ARG_C | - R200_TXC_OP_MADD); - R200_COLOR_ARG( 0, A ); - R200_COLOR_ARG( 1, C ); - break; - case GL_INTERPOLATE: - color_combine = (R200_TXC_OP_LERP); - R200_COLOR_ARG( 0, B ); - R200_COLOR_ARG( 1, A ); - R200_COLOR_ARG( 2, C ); - break; - - case GL_DOT3_RGB_EXT: - case GL_DOT3_RGBA_EXT: - /* The EXT version of the DOT3 extension does not support the - * scale factor, but the ARB version (and the version in OpenGL - * 1.3) does. - */ - RGBshift = 0; - FALLTHROUGH; - - case GL_DOT3_RGB: - case GL_DOT3_RGBA: - /* DOT3 works differently on R200 than on R100. On R100, just - * setting the DOT3 mode did everything for you. On R200, the - * driver has to enable the biasing and scale in the inputs to - * put them in the proper [-1,1] range. This is what the 4x and - * the -0.5 in the DOT3 spec do. The post-scale is then set - * normally. - */ - - color_combine = (R200_TXC_ARG_C_ZERO | - R200_TXC_OP_DOT3 | - R200_TXC_BIAS_ARG_A | - R200_TXC_BIAS_ARG_B | - R200_TXC_SCALE_ARG_A | - R200_TXC_SCALE_ARG_B); - R200_COLOR_ARG( 0, A ); - R200_COLOR_ARG( 1, B ); - break; - - case GL_MODULATE_ADD_ATI: - color_combine = (R200_TXC_OP_MADD); - R200_COLOR_ARG( 0, A ); - R200_COLOR_ARG( 1, C ); - R200_COLOR_ARG( 2, B ); - break; - case GL_MODULATE_SIGNED_ADD_ATI: - color_combine = (R200_TXC_BIAS_ARG_C | /* new */ - R200_TXC_OP_MADD); /* was ADDSIGNED */ - R200_COLOR_ARG( 0, A ); - R200_COLOR_ARG( 1, C ); - R200_COLOR_ARG( 2, B ); - break; - case GL_MODULATE_SUBTRACT_ATI: - color_combine = (R200_TXC_NEG_ARG_C | - R200_TXC_OP_MADD); - R200_COLOR_ARG( 0, A ); - R200_COLOR_ARG( 1, C ); - R200_COLOR_ARG( 2, B ); - break; - default: - return GL_FALSE; - } - - switch ( texUnit->_CurrentCombine->ModeA ) { - case GL_REPLACE: - alpha_combine = (R200_TXA_ARG_A_ZERO | - R200_TXA_ARG_B_ZERO | - R200_TXA_OP_MADD); - R200_ALPHA_ARG( 0, C ); - break; - case GL_MODULATE: - alpha_combine = (R200_TXA_ARG_C_ZERO | - R200_TXA_OP_MADD); - R200_ALPHA_ARG( 0, A ); - R200_ALPHA_ARG( 1, B ); - break; - case GL_ADD: - alpha_combine = (R200_TXA_ARG_B_ZERO | - R200_TXA_COMP_ARG_B | - R200_TXA_OP_MADD); - R200_ALPHA_ARG( 0, A ); - R200_ALPHA_ARG( 1, C ); - break; - case GL_ADD_SIGNED: - alpha_combine = (R200_TXA_ARG_B_ZERO | - R200_TXA_COMP_ARG_B | - R200_TXA_BIAS_ARG_C | /* new */ - R200_TXA_OP_MADD); /* was ADDSIGNED */ - R200_ALPHA_ARG( 0, A ); - R200_ALPHA_ARG( 1, C ); - break; - case GL_SUBTRACT: - alpha_combine = (R200_TXA_ARG_B_ZERO | - R200_TXA_COMP_ARG_B | - R200_TXA_NEG_ARG_C | - R200_TXA_OP_MADD); - R200_ALPHA_ARG( 0, A ); - R200_ALPHA_ARG( 1, C ); - break; - case GL_INTERPOLATE: - alpha_combine = (R200_TXA_OP_LERP); - R200_ALPHA_ARG( 0, B ); - R200_ALPHA_ARG( 1, A ); - R200_ALPHA_ARG( 2, C ); - break; - - case GL_MODULATE_ADD_ATI: - alpha_combine = (R200_TXA_OP_MADD); - R200_ALPHA_ARG( 0, A ); - R200_ALPHA_ARG( 1, C ); - R200_ALPHA_ARG( 2, B ); - break; - case GL_MODULATE_SIGNED_ADD_ATI: - alpha_combine = (R200_TXA_BIAS_ARG_C | /* new */ - R200_TXA_OP_MADD); /* was ADDSIGNED */ - R200_ALPHA_ARG( 0, A ); - R200_ALPHA_ARG( 1, C ); - R200_ALPHA_ARG( 2, B ); - break; - case GL_MODULATE_SUBTRACT_ATI: - alpha_combine = (R200_TXA_NEG_ARG_C | - R200_TXA_OP_MADD); - R200_ALPHA_ARG( 0, A ); - R200_ALPHA_ARG( 1, C ); - R200_ALPHA_ARG( 2, B ); - break; - default: - return GL_FALSE; - } - - if ( (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGBA_EXT) - || (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGBA) ) { - alpha_scale |= R200_TXA_DOT_ALPHA; - Ashift = RGBshift; - } - - /* Step 3: - * Apply the scale factor. - */ - color_scale |= (RGBshift << R200_TXC_SCALE_SHIFT); - alpha_scale |= (Ashift << R200_TXA_SCALE_SHIFT); - - /* All done! - */ - } - - if ( rmesa->hw.pix[slot].cmd[PIX_PP_TXCBLEND] != color_combine || - rmesa->hw.pix[slot].cmd[PIX_PP_TXABLEND] != alpha_combine || - rmesa->hw.pix[slot].cmd[PIX_PP_TXCBLEND2] != color_scale || - rmesa->hw.pix[slot].cmd[PIX_PP_TXABLEND2] != alpha_scale) { - R200_STATECHANGE( rmesa, pix[slot] ); - rmesa->hw.pix[slot].cmd[PIX_PP_TXCBLEND] = color_combine; - rmesa->hw.pix[slot].cmd[PIX_PP_TXABLEND] = alpha_combine; - rmesa->hw.pix[slot].cmd[PIX_PP_TXCBLEND2] = color_scale; - rmesa->hw.pix[slot].cmd[PIX_PP_TXABLEND2] = alpha_scale; - } - - return GL_TRUE; -} - -void r200SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint texture_format, - __DRIdrawable *dPriv) -{ - struct gl_texture_object *texObj; - struct gl_texture_image *texImage; - struct radeon_renderbuffer *rb; - radeon_texture_image *rImage; - radeonContextPtr radeon; - struct radeon_framebuffer *rfb; - radeonTexObjPtr t; - uint32_t pitch_val; - mesa_format texFormat; - - radeon = pDRICtx->driverPrivate; - - rfb = dPriv->driverPrivate; - texObj = _mesa_get_current_tex_object(&radeon->glCtx, target); - texImage = _mesa_get_tex_image(&radeon->glCtx, texObj, target, 0); - - rImage = get_radeon_texture_image(texImage); - t = radeon_tex_obj(texObj); - if (t == NULL) { - return; - } - - radeon_update_renderbuffers(pDRICtx, dPriv, GL_TRUE); - rb = rfb->color_rb[0]; - if (rb->bo == NULL) { - /* Failed to BO for the buffer */ - return; - } - - _mesa_lock_texture(&radeon->glCtx, texObj); - if (t->bo) { - radeon_bo_unref(t->bo); - t->bo = NULL; - } - if (rImage->bo) { - radeon_bo_unref(rImage->bo); - rImage->bo = NULL; - } - - radeon_miptree_unreference(&t->mt); - radeon_miptree_unreference(&rImage->mt); - - rImage->bo = rb->bo; - radeon_bo_ref(rImage->bo); - t->bo = rb->bo; - radeon_bo_ref(t->bo); - t->tile_bits = 0; - t->image_override = GL_TRUE; - t->override_offset = 0; - t->pp_txpitch &= (1 << 13) -1; - pitch_val = rb->pitch; - switch (rb->cpp) { - case 4: - if (texture_format == __DRI_TEXTURE_FORMAT_RGB) - texFormat = MESA_FORMAT_BGR_UNORM8; - else - texFormat = MESA_FORMAT_B8G8R8A8_UNORM; - break; - case 3: - default: - texFormat = MESA_FORMAT_BGR_UNORM8; - break; - case 2: - texFormat = MESA_FORMAT_B5G6R5_UNORM; - break; - } - - t->pp_txformat = tx_table_le[texFormat].format; - t->pp_txfilter |= tx_table_le[texFormat].filter; - - _mesa_init_teximage_fields(&radeon->glCtx, texImage, - rb->base.Base.Width, rb->base.Base.Height, - 1, 0, - rb->cpp, texFormat); - rImage->base.RowStride = rb->pitch / rb->cpp; - - - t->pp_txsize = ((rb->base.Base.Width - 1) << RADEON_TEX_USIZE_SHIFT) - | ((rb->base.Base.Height - 1) << RADEON_TEX_VSIZE_SHIFT); - - if (target == GL_TEXTURE_RECTANGLE_NV) { - t->pp_txformat |= R200_TXFORMAT_NON_POWER2; - t->pp_txpitch = pitch_val; - t->pp_txpitch -= 32; - } else { - t->pp_txformat &= ~(R200_TXFORMAT_WIDTH_MASK | - R200_TXFORMAT_HEIGHT_MASK | - R200_TXFORMAT_CUBIC_MAP_ENABLE | - R200_TXFORMAT_F5_WIDTH_MASK | - R200_TXFORMAT_F5_HEIGHT_MASK); - t->pp_txformat |= ((texImage->WidthLog2 << R200_TXFORMAT_WIDTH_SHIFT) | - (texImage->HeightLog2 << R200_TXFORMAT_HEIGHT_SHIFT)); - } - - t->validated = GL_TRUE; - _mesa_unlock_texture(&radeon->glCtx, texObj); - return; -} - - -void r200SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv) -{ - r200SetTexBuffer2(pDRICtx, target, __DRI_TEXTURE_FORMAT_RGBA, dPriv); -} - - -#define REF_COLOR 1 -#define REF_ALPHA 2 - -static GLboolean r200UpdateAllTexEnv( struct gl_context *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLint i, j, currslot; - GLint maxunitused = -1; - GLboolean texregfree[6] = {GL_TRUE, GL_TRUE, GL_TRUE, GL_TRUE, GL_TRUE, GL_TRUE}; - GLubyte stageref[7] = {0, 0, 0, 0, 0, 0, 0}; - GLint nextunit[R200_MAX_TEXTURE_UNITS] = {0, 0, 0, 0, 0, 0}; - GLint currentnext = -1; - GLboolean ok; - - /* find highest used unit */ - for ( j = 0; j < R200_MAX_TEXTURE_UNITS; j++) { - if (ctx->Texture.Unit[j]._Current) { - maxunitused = j; - } - } - stageref[maxunitused + 1] = REF_COLOR | REF_ALPHA; - - for ( j = maxunitused; j >= 0; j-- ) { - const struct gl_texture_unit *rtexUnit = &ctx->Texture.Unit[j]; - const struct gl_fixedfunc_texture_unit *texUnit = - &ctx->Texture.FixedFuncUnit[j]; - - rmesa->state.texture.unit[j].outputreg = -1; - - if (stageref[j + 1]) { - - /* use the lowest available reg. That gets us automatically reg0 for the last stage. - need this even for disabled units, as it may get referenced due to the replace - optimization */ - for ( i = 0 ; i < R200_MAX_TEXTURE_UNITS; i++ ) { - if (texregfree[i]) { - rmesa->state.texture.unit[j].outputreg = i; - break; - } - } - if (rmesa->state.texture.unit[j].outputreg == -1) { - /* no more free regs we can use. Need a fallback :-( */ - return GL_FALSE; - } - - nextunit[j] = currentnext; - - if (!rtexUnit->_Current) { - /* the not enabled stages are referenced "indirectly", - must not cut off the lower stages */ - stageref[j] = REF_COLOR | REF_ALPHA; - continue; - } - currentnext = j; - - const GLuint numColorArgs = texUnit->_CurrentCombine->_NumArgsRGB; - const GLuint numAlphaArgs = texUnit->_CurrentCombine->_NumArgsA; - const GLboolean isdot3rgba = (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGBA) || - (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGBA_EXT); - - - /* check if we need the color part, special case for dot3_rgba - as if only the alpha part is referenced later on it still is using the color part */ - if ((stageref[j + 1] & REF_COLOR) || isdot3rgba) { - for ( i = 0 ; i < numColorArgs ; i++ ) { - const GLuint srcRGBi = texUnit->_CurrentCombine->SourceRGB[i]; - const GLuint op = texUnit->_CurrentCombine->OperandRGB[i]; - switch ( srcRGBi ) { - case GL_PREVIOUS: - /* op 0/1 are referencing color, op 2/3 alpha */ - stageref[j] |= (op >> 1) + 1; - break; - case GL_TEXTURE: - texregfree[j] = GL_FALSE; - break; - case GL_TEXTURE0: - case GL_TEXTURE1: - case GL_TEXTURE2: - case GL_TEXTURE3: - case GL_TEXTURE4: - case GL_TEXTURE5: - texregfree[srcRGBi - GL_TEXTURE0] = GL_FALSE; - break; - default: /* don't care about other sources here */ - break; - } - } - } - - /* alpha args are ignored for dot3_rgba */ - if ((stageref[j + 1] & REF_ALPHA) && !isdot3rgba) { - - for ( i = 0 ; i < numAlphaArgs ; i++ ) { - const GLuint srcAi = texUnit->_CurrentCombine->SourceA[i]; - switch ( srcAi ) { - case GL_PREVIOUS: - stageref[j] |= REF_ALPHA; - break; - case GL_TEXTURE: - texregfree[j] = GL_FALSE; - break; - case GL_TEXTURE0: - case GL_TEXTURE1: - case GL_TEXTURE2: - case GL_TEXTURE3: - case GL_TEXTURE4: - case GL_TEXTURE5: - texregfree[srcAi - GL_TEXTURE0] = GL_FALSE; - break; - default: /* don't care about other sources here */ - break; - } - } - } - } - } - - /* don't enable texture sampling for units if the result is not used */ - for (i = 0; i < R200_MAX_TEXTURE_UNITS; i++) { - if (ctx->Texture.Unit[i]._Current && !texregfree[i]) - rmesa->state.texture.unit[i].unitneeded = 1 << _mesa_tex_target_to_index(ctx, ctx->Texture.Unit[i]._Current->Target); - else rmesa->state.texture.unit[i].unitneeded = 0; - } - - ok = GL_TRUE; - currslot = 0; - rmesa->state.envneeded = 1; - - i = 0; - while ((i <= maxunitused) && (i >= 0)) { - /* only output instruction if the results are referenced */ - if (ctx->Texture.Unit[i]._Current && stageref[i+1]) { - GLuint replaceunit = i; - /* try to optimize GL_REPLACE away (only one level deep though) */ - if ( (ctx->Texture.FixedFuncUnit[i]._CurrentCombine->ModeRGB == GL_REPLACE) && - (ctx->Texture.FixedFuncUnit[i]._CurrentCombine->ModeA == GL_REPLACE) && - (ctx->Texture.FixedFuncUnit[i]._CurrentCombine->ScaleShiftRGB == 0) && - (ctx->Texture.FixedFuncUnit[i]._CurrentCombine->ScaleShiftA == 0) && - (nextunit[i] > 0) ) { - /* yippie! can optimize it away! */ - replaceunit = i; - i = nextunit[i]; - } - - /* need env instruction slot */ - rmesa->state.envneeded |= 1 << currslot; - ok = r200UpdateTextureEnv( ctx, i, currslot, replaceunit ); - if (!ok) return GL_FALSE; - currslot++; - } - i = i + 1; - } - - if (currslot == 0) { - /* need one stage at least */ - rmesa->state.texture.unit[0].outputreg = 0; - ok = r200UpdateTextureEnv( ctx, 0, 0, 0 ); - } - - R200_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~(R200_TEX_BLEND_ENABLE_MASK | R200_MULTI_PASS_ENABLE); - rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= rmesa->state.envneeded << R200_TEX_BLEND_0_ENABLE_SHIFT; - - return ok; -} - -#undef REF_COLOR -#undef REF_ALPHA - - -#define TEXOBJ_TXFILTER_MASK (R200_MAX_MIP_LEVEL_MASK | \ - R200_MIN_FILTER_MASK | \ - R200_MAG_FILTER_MASK | \ - R200_MAX_ANISO_MASK | \ - R200_YUV_TO_RGB | \ - R200_YUV_TEMPERATURE_MASK | \ - R200_CLAMP_S_MASK | \ - R200_CLAMP_T_MASK | \ - R200_BORDER_MODE_D3D ) - -#define TEXOBJ_TXFORMAT_MASK (R200_TXFORMAT_WIDTH_MASK | \ - R200_TXFORMAT_HEIGHT_MASK | \ - R200_TXFORMAT_FORMAT_MASK | \ - R200_TXFORMAT_F5_WIDTH_MASK | \ - R200_TXFORMAT_F5_HEIGHT_MASK | \ - R200_TXFORMAT_ALPHA_IN_MAP | \ - R200_TXFORMAT_CUBIC_MAP_ENABLE | \ - R200_TXFORMAT_NON_POWER2) - -#define TEXOBJ_TXFORMAT_X_MASK (R200_DEPTH_LOG2_MASK | \ - R200_TEXCOORD_MASK | \ - R200_MIN_MIP_LEVEL_MASK | \ - R200_CLAMP_Q_MASK | \ - R200_VOLUME_FILTER_MASK) - - -static void disable_tex_obj_state( r200ContextPtr rmesa, - int unit ) -{ - - R200_STATECHANGE( rmesa, vtx ); - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] &= ~(7 << (unit * 3)); - - R200_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~(R200_TEX_0_ENABLE << unit); - if (rmesa->radeon.TclFallback & (R200_TCL_FALLBACK_TEXGEN_0<<unit)) { - TCL_FALLBACK( &rmesa->radeon.glCtx, (R200_TCL_FALLBACK_TEXGEN_0<<unit), GL_FALSE); - } - - /* Actually want to keep all units less than max active texture - * enabled, right? Fix this for >2 texunits. - */ - - { - GLuint tmp = rmesa->TexGenEnabled; - - rmesa->TexGenEnabled &= ~(R200_TEXGEN_TEXMAT_0_ENABLE<<unit); - rmesa->TexGenEnabled &= ~(R200_TEXMAT_0_ENABLE<<unit); - rmesa->TexGenNeedNormals[unit] = GL_FALSE; - rmesa->TexGenCompSel &= ~(R200_OUTPUT_TEX_0 << unit); - - if (tmp != rmesa->TexGenEnabled) { - rmesa->recheck_texgen[unit] = GL_TRUE; - rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; - } - } -} -static void import_tex_obj_state( r200ContextPtr rmesa, - int unit, - radeonTexObjPtr texobj ) -{ -/* do not use RADEON_DB_STATE to avoid stale texture caches */ - GLuint *cmd = &rmesa->hw.tex[unit].cmd[TEX_CMD_0]; - - R200_STATECHANGE( rmesa, tex[unit] ); - - cmd[TEX_PP_TXFILTER] &= ~TEXOBJ_TXFILTER_MASK; - cmd[TEX_PP_TXFILTER] |= texobj->pp_txfilter & TEXOBJ_TXFILTER_MASK; - cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK; - cmd[TEX_PP_TXFORMAT] |= texobj->pp_txformat & TEXOBJ_TXFORMAT_MASK; - cmd[TEX_PP_TXFORMAT_X] &= ~TEXOBJ_TXFORMAT_X_MASK; - cmd[TEX_PP_TXFORMAT_X] |= texobj->pp_txformat_x & TEXOBJ_TXFORMAT_X_MASK; - cmd[TEX_PP_TXSIZE] = texobj->pp_txsize; /* NPOT only! */ - cmd[TEX_PP_TXPITCH] = texobj->pp_txpitch; /* NPOT only! */ - cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color; - - if (texobj->base.Target == GL_TEXTURE_CUBE_MAP) { - GLuint *cube_cmd = &rmesa->hw.cube[unit].cmd[CUBE_CMD_0]; - - R200_STATECHANGE( rmesa, cube[unit] ); - cube_cmd[CUBE_PP_CUBIC_FACES] = texobj->pp_cubic_faces; - /* that value is submitted twice. could change cube atom - to not include that command when new drm is used */ - cmd[TEX_PP_CUBIC_FACES] = texobj->pp_cubic_faces; - } - -} - -static void set_texgen_matrix( r200ContextPtr rmesa, - GLuint unit, - const GLfloat *s_plane, - const GLfloat *t_plane, - const GLfloat *r_plane, - const GLfloat *q_plane ) -{ - GLfloat m[16]; - - m[0] = s_plane[0]; - m[4] = s_plane[1]; - m[8] = s_plane[2]; - m[12] = s_plane[3]; - - m[1] = t_plane[0]; - m[5] = t_plane[1]; - m[9] = t_plane[2]; - m[13] = t_plane[3]; - - m[2] = r_plane[0]; - m[6] = r_plane[1]; - m[10] = r_plane[2]; - m[14] = r_plane[3]; - - m[3] = q_plane[0]; - m[7] = q_plane[1]; - m[11] = q_plane[2]; - m[15] = q_plane[3]; - - _math_matrix_loadf( &(rmesa->TexGenMatrix[unit]), m); - _math_matrix_analyse( &(rmesa->TexGenMatrix[unit]) ); - rmesa->TexGenEnabled |= R200_TEXMAT_0_ENABLE<<unit; -} - - -static GLuint r200_need_dis_texgen(const GLbitfield texGenEnabled, - const GLfloat *planeS, - const GLfloat *planeT, - const GLfloat *planeR, - const GLfloat *planeQ) -{ - GLuint needtgenable = 0; - - if (!(texGenEnabled & S_BIT)) { - if (((texGenEnabled & T_BIT) && planeT[0] != 0.0) || - ((texGenEnabled & R_BIT) && planeR[0] != 0.0) || - ((texGenEnabled & Q_BIT) && planeQ[0] != 0.0)) { - needtgenable |= S_BIT; - } - } - if (!(texGenEnabled & T_BIT)) { - if (((texGenEnabled & S_BIT) && planeS[1] != 0.0) || - ((texGenEnabled & R_BIT) && planeR[1] != 0.0) || - ((texGenEnabled & Q_BIT) && planeQ[1] != 0.0)) { - needtgenable |= T_BIT; - } - } - if (!(texGenEnabled & R_BIT)) { - if (((texGenEnabled & S_BIT) && planeS[2] != 0.0) || - ((texGenEnabled & T_BIT) && planeT[2] != 0.0) || - ((texGenEnabled & Q_BIT) && planeQ[2] != 0.0)) { - needtgenable |= R_BIT; - } - } - if (!(texGenEnabled & Q_BIT)) { - if (((texGenEnabled & S_BIT) && planeS[3] != 0.0) || - ((texGenEnabled & T_BIT) && planeT[3] != 0.0) || - ((texGenEnabled & R_BIT) && planeR[3] != 0.0)) { - needtgenable |= Q_BIT; - } - } - - return needtgenable; -} - - -/* - * Returns GL_FALSE if fallback required. - */ -static GLboolean r200_validate_texgen( struct gl_context *ctx, GLuint unit ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - const struct gl_fixedfunc_texture_unit *texUnit = - &ctx->Texture.FixedFuncUnit[unit]; - GLuint inputshift = R200_TEXGEN_0_INPUT_SHIFT + unit*4; - GLuint tgi, tgcm; - GLuint mode = 0; - GLboolean mixed_fallback = GL_FALSE; - static const GLfloat I[16] = { - 1, 0, 0, 0, - 0, 1, 0, 0, - 0, 0, 1, 0, - 0, 0, 0, 1 }; - static const GLfloat reflect[16] = { - -1, 0, 0, 0, - 0, -1, 0, 0, - 0, 0, -1, 0, - 0, 0, 0, 1 }; - - rmesa->TexGenCompSel &= ~(R200_OUTPUT_TEX_0 << unit); - rmesa->TexGenEnabled &= ~(R200_TEXGEN_TEXMAT_0_ENABLE<<unit); - rmesa->TexGenEnabled &= ~(R200_TEXMAT_0_ENABLE<<unit); - rmesa->TexGenNeedNormals[unit] = GL_FALSE; - tgi = rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] & ~(R200_TEXGEN_INPUT_MASK << - inputshift); - tgcm = rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] & ~(R200_TEXGEN_COMP_MASK << - (unit * 4)); - - if (0) - fprintf(stderr, "%s unit %d\n", __func__, unit); - - if (texUnit->TexGenEnabled & S_BIT) { - mode = texUnit->GenS.Mode; - } else { - tgcm |= R200_TEXGEN_COMP_S << (unit * 4); - } - - if (texUnit->TexGenEnabled & T_BIT) { - if (texUnit->GenT.Mode != mode) - mixed_fallback = GL_TRUE; - } else { - tgcm |= R200_TEXGEN_COMP_T << (unit * 4); - } - if (texUnit->TexGenEnabled & R_BIT) { - if (texUnit->GenR.Mode != mode) - mixed_fallback = GL_TRUE; - } else { - tgcm |= R200_TEXGEN_COMP_R << (unit * 4); - } - - if (texUnit->TexGenEnabled & Q_BIT) { - if (texUnit->GenQ.Mode != mode) - mixed_fallback = GL_TRUE; - } else { - tgcm |= R200_TEXGEN_COMP_Q << (unit * 4); - } - - if (mixed_fallback) { - if (R200_DEBUG & RADEON_FALLBACKS) - fprintf(stderr, "fallback mixed texgen, 0x%x (0x%x 0x%x 0x%x 0x%x)\n", - texUnit->TexGenEnabled, texUnit->GenS.Mode, texUnit->GenT.Mode, - texUnit->GenR.Mode, texUnit->GenQ.Mode); - return GL_FALSE; - } - -/* we CANNOT do mixed mode if the texgen mode requires a plane where the input - is not enabled for texgen, since the planes are concatenated into texmat, - and thus the input will come from texcoord rather than tex gen equation! - Either fallback or just hope that those texcoords aren't really needed... - Assuming the former will cause lots of unnecessary fallbacks, the latter will - generate bogus results sometimes - it's pretty much impossible to really know - when a fallback is needed, depends on texmat and what sort of texture is bound - etc, - for now fallback if we're missing either S or T bits, there's a high - probability we need the texcoords in that case. - That's a lot of work for some obscure texgen mixed mode fixup - why oh why - doesn't the chip just directly accept the plane parameters :-(. */ - switch (mode) { - case GL_OBJECT_LINEAR: { - GLuint needtgenable = r200_need_dis_texgen( texUnit->TexGenEnabled, - texUnit->ObjectPlane[GEN_S], - texUnit->ObjectPlane[GEN_T], - texUnit->ObjectPlane[GEN_R], - texUnit->ObjectPlane[GEN_Q] ); - if (needtgenable & (S_BIT | T_BIT)) { - if (R200_DEBUG & RADEON_FALLBACKS) - fprintf(stderr, "fallback mixed texgen / obj plane, 0x%x\n", - texUnit->TexGenEnabled); - return GL_FALSE; - } - if (needtgenable & (R_BIT)) { - tgcm &= ~(R200_TEXGEN_COMP_R << (unit * 4)); - } - if (needtgenable & (Q_BIT)) { - tgcm &= ~(R200_TEXGEN_COMP_Q << (unit * 4)); - } - - tgi |= R200_TEXGEN_INPUT_OBJ << inputshift; - set_texgen_matrix( rmesa, unit, - (texUnit->TexGenEnabled & S_BIT) ? texUnit->ObjectPlane[GEN_S] : I, - (texUnit->TexGenEnabled & T_BIT) ? texUnit->ObjectPlane[GEN_T] : I + 4, - (texUnit->TexGenEnabled & R_BIT) ? texUnit->ObjectPlane[GEN_R] : I + 8, - (texUnit->TexGenEnabled & Q_BIT) ? texUnit->ObjectPlane[GEN_Q] : I + 12); - } - break; - - case GL_EYE_LINEAR: { - GLuint needtgenable = r200_need_dis_texgen( texUnit->TexGenEnabled, - texUnit->EyePlane[GEN_S], - texUnit->EyePlane[GEN_T], - texUnit->EyePlane[GEN_R], - texUnit->EyePlane[GEN_Q] ); - if (needtgenable & (S_BIT | T_BIT)) { - if (R200_DEBUG & RADEON_FALLBACKS) - fprintf(stderr, "fallback mixed texgen / eye plane, 0x%x\n", - texUnit->TexGenEnabled); - return GL_FALSE; - } - if (needtgenable & (R_BIT)) { - tgcm &= ~(R200_TEXGEN_COMP_R << (unit * 4)); - } - if (needtgenable & (Q_BIT)) { - tgcm &= ~(R200_TEXGEN_COMP_Q << (unit * 4)); - } - tgi |= R200_TEXGEN_INPUT_EYE << inputshift; - set_texgen_matrix( rmesa, unit, - (texUnit->TexGenEnabled & S_BIT) ? texUnit->EyePlane[GEN_S] : I, - (texUnit->TexGenEnabled & T_BIT) ? texUnit->EyePlane[GEN_T] : I + 4, - (texUnit->TexGenEnabled & R_BIT) ? texUnit->EyePlane[GEN_R] : I + 8, - (texUnit->TexGenEnabled & Q_BIT) ? texUnit->EyePlane[GEN_Q] : I + 12); - } - break; - - case GL_REFLECTION_MAP_NV: - rmesa->TexGenNeedNormals[unit] = GL_TRUE; - tgi |= R200_TEXGEN_INPUT_EYE_REFLECT << inputshift; - /* pretty weird, must only negate when lighting is enabled? */ - if (ctx->Light.Enabled) - set_texgen_matrix( rmesa, unit, - (texUnit->TexGenEnabled & S_BIT) ? reflect : I, - (texUnit->TexGenEnabled & T_BIT) ? reflect + 4 : I + 4, - (texUnit->TexGenEnabled & R_BIT) ? reflect + 8 : I + 8, - I + 12); - break; - - case GL_NORMAL_MAP_NV: - rmesa->TexGenNeedNormals[unit] = GL_TRUE; - tgi |= R200_TEXGEN_INPUT_EYE_NORMAL<<inputshift; - break; - - case GL_SPHERE_MAP: - rmesa->TexGenNeedNormals[unit] = GL_TRUE; - tgi |= R200_TEXGEN_INPUT_SPHERE<<inputshift; - break; - - case 0: - /* All texgen units were disabled, so just pass coords through. */ - tgi |= unit << inputshift; - break; - - default: - /* Unsupported mode, fallback: - */ - if (R200_DEBUG & RADEON_FALLBACKS) - fprintf(stderr, "fallback unsupported texgen, %d\n", - texUnit->GenS.Mode); - return GL_FALSE; - } - - rmesa->TexGenEnabled |= R200_TEXGEN_TEXMAT_0_ENABLE << unit; - rmesa->TexGenCompSel |= R200_OUTPUT_TEX_0 << unit; - - if (tgi != rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] || - tgcm != rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2]) - { - R200_STATECHANGE(rmesa, tcg); - rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_1] = tgi; - rmesa->hw.tcg.cmd[TCG_TEX_PROC_CTL_2] = tgcm; - } - - return GL_TRUE; -} - -void set_re_cntl_d3d( struct gl_context *ctx, int unit, GLboolean use_d3d ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - GLuint re_cntl; - - re_cntl = rmesa->hw.set.cmd[SET_RE_CNTL] & ~(R200_VTX_STQ0_D3D << (2 * unit)); - if (use_d3d) - re_cntl |= R200_VTX_STQ0_D3D << (2 * unit); - - if ( re_cntl != rmesa->hw.set.cmd[SET_RE_CNTL] ) { - R200_STATECHANGE( rmesa, set ); - rmesa->hw.set.cmd[SET_RE_CNTL] = re_cntl; - } -} - -/** - * Compute the cached hardware register values for the given texture object. - * - * \param rmesa Context pointer - * \param t the r300 texture object - */ -static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t) -{ - const struct gl_texture_image *firstImage = t->base.Image[0][t->minLod]; - GLint log2Width, log2Height, log2Depth, texelBytes; - uint extra_size = 0; - - if ( t->bo ) { - return; - } - - log2Width = firstImage->WidthLog2; - log2Height = firstImage->HeightLog2; - log2Depth = firstImage->DepthLog2; - texelBytes = _mesa_get_format_bytes(firstImage->TexFormat); - - radeon_print(RADEON_TEXTURE, RADEON_TRACE, - "%s(%p, tex %p) log2(w %d, h %d, d %d), texelBytes %d. format %d\n", - __func__, rmesa, t, log2Width, log2Height, - log2Depth, texelBytes, firstImage->TexFormat); - - if (!t->image_override) { - if (VALID_FORMAT(firstImage->TexFormat)) { -#if UTIL_ARCH_LITTLE_ENDIAN - const struct tx_table *table = tx_table_le; -#else - const struct tx_table *table = tx_table_be; -#endif - - t->pp_txformat &= ~(R200_TXFORMAT_FORMAT_MASK | - R200_TXFORMAT_ALPHA_IN_MAP); - t->pp_txfilter &= ~R200_YUV_TO_RGB; - - t->pp_txformat |= table[ firstImage->TexFormat ].format; - t->pp_txfilter |= table[ firstImage->TexFormat ].filter; - - - } else { - _mesa_problem(NULL, "unexpected texture format in %s", - __func__); - return; - } - } - - t->pp_txfilter &= ~R200_MAX_MIP_LEVEL_MASK; - t->pp_txfilter |= ((t->maxLod) << R200_MAX_MIP_LEVEL_SHIFT) - & R200_MAX_MIP_LEVEL_MASK; - - if ( t->pp_txfilter & - (R200_MIN_FILTER_NEAREST_MIP_NEAREST - | R200_MIN_FILTER_NEAREST_MIP_LINEAR - | R200_MIN_FILTER_LINEAR_MIP_NEAREST - | R200_MIN_FILTER_LINEAR_MIP_LINEAR - | R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST - | R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR)) - extra_size = t->minLod; - - t->pp_txformat &= ~(R200_TXFORMAT_WIDTH_MASK | - R200_TXFORMAT_HEIGHT_MASK | - R200_TXFORMAT_CUBIC_MAP_ENABLE | - R200_TXFORMAT_F5_WIDTH_MASK | - R200_TXFORMAT_F5_HEIGHT_MASK); - t->pp_txformat |= (((log2Width + extra_size) << R200_TXFORMAT_WIDTH_SHIFT) | - ((log2Height + extra_size)<< R200_TXFORMAT_HEIGHT_SHIFT)); - - t->tile_bits = 0; - - t->pp_txformat_x &= ~(R200_DEPTH_LOG2_MASK | R200_TEXCOORD_MASK - | R200_MIN_MIP_LEVEL_MASK); - - t->pp_txformat_x |= (t->minLod << R200_MIN_MIP_LEVEL_SHIFT) - & R200_MIN_MIP_LEVEL_MASK; - - if (t->base.Target == GL_TEXTURE_3D) { - t->pp_txformat_x |= (log2Depth << R200_DEPTH_LOG2_SHIFT); - t->pp_txformat_x |= R200_TEXCOORD_VOLUME; - - } - else if (t->base.Target == GL_TEXTURE_CUBE_MAP) { - assert(log2Width == log2Height); - t->pp_txformat |= ((log2Width << R200_TXFORMAT_F5_WIDTH_SHIFT) | - (log2Height << R200_TXFORMAT_F5_HEIGHT_SHIFT) | - /* don't think we need this bit, if it exists at all - fglrx does not set it */ - (R200_TXFORMAT_CUBIC_MAP_ENABLE)); - t->pp_txformat_x |= R200_TEXCOORD_CUBIC_ENV; - t->pp_cubic_faces = ((log2Width << R200_FACE_WIDTH_1_SHIFT) | - (log2Height << R200_FACE_HEIGHT_1_SHIFT) | - (log2Width << R200_FACE_WIDTH_2_SHIFT) | - (log2Height << R200_FACE_HEIGHT_2_SHIFT) | - (log2Width << R200_FACE_WIDTH_3_SHIFT) | - (log2Height << R200_FACE_HEIGHT_3_SHIFT) | - (log2Width << R200_FACE_WIDTH_4_SHIFT) | - (log2Height << R200_FACE_HEIGHT_4_SHIFT)); - } - else { - /* If we don't in fact send enough texture coordinates, q will be 1, - * making TEXCOORD_PROJ act like TEXCOORD_NONPROJ (Right?) - */ - t->pp_txformat_x |= R200_TEXCOORD_PROJ; - } - /* FIXME: NPOT sizes, is it correct really? */ - t->pp_txsize = (((firstImage->Width - 1) << R200_PP_TX_WIDTHMASK_SHIFT) - | ((firstImage->Height - 1) << R200_PP_TX_HEIGHTMASK_SHIFT)); - - if ( !t->image_override ) { - if (_mesa_is_format_compressed(firstImage->TexFormat)) - t->pp_txpitch = (firstImage->Width + 63) & ~(63); - else - t->pp_txpitch = ((firstImage->Width * texelBytes) + 63) & ~(63); - t->pp_txpitch -= 32; - } - - if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) { - t->pp_txformat |= R200_TXFORMAT_NON_POWER2; - } - -} - -static GLboolean r200_validate_texture(struct gl_context *ctx, struct gl_texture_object *texObj, int unit) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - radeonTexObj *t = radeon_tex_obj(texObj); - - if (!radeon_validate_texture_miptree(ctx, _mesa_get_samplerobj(ctx, unit), texObj)) - return GL_FALSE; - - r200_validate_texgen(ctx, unit); - /* Configure the hardware registers (more precisely, the cached version - * of the hardware registers). */ - setup_hardware_state(rmesa, t); - - if (texObj->Target == GL_TEXTURE_RECTANGLE_NV || - texObj->Target == GL_TEXTURE_2D || - texObj->Target == GL_TEXTURE_1D) - set_re_cntl_d3d( ctx, unit, GL_FALSE ); - else - set_re_cntl_d3d( ctx, unit, GL_TRUE ); - R200_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_0_ENABLE << unit; - - R200_STATECHANGE( rmesa, vtx ); - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] &= ~(7 << (unit * 3)); - rmesa->hw.vtx.cmd[VTX_TCL_OUTPUT_VTXFMT_1] |= 4 << (unit * 3); - - rmesa->recheck_texgen[unit] = GL_TRUE; - r200TexUpdateParameters(ctx, unit); - import_tex_obj_state( rmesa, unit, t ); - - if (rmesa->recheck_texgen[unit]) { - GLboolean fallback = !r200_validate_texgen( ctx, unit ); - TCL_FALLBACK( ctx, (R200_TCL_FALLBACK_TEXGEN_0<<unit), fallback); - rmesa->recheck_texgen[unit] = 0; - rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX; - } - - t->validated = GL_TRUE; - - FALLBACK( rmesa, RADEON_FALLBACK_BORDER_MODE, t->border_fallback ); - - return !t->border_fallback; -} - -static GLboolean r200UpdateTextureUnit(struct gl_context *ctx, int unit) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLuint unitneeded = rmesa->state.texture.unit[unit].unitneeded; - - if (!unitneeded) { - /* disable the unit */ - disable_tex_obj_state(rmesa, unit); - return GL_TRUE; - } - - if (!r200_validate_texture(ctx, ctx->Texture.Unit[unit]._Current, unit)) { - _mesa_warning(ctx, - "failed to validate texture for unit %d.\n", - unit); - rmesa->state.texture.unit[unit].texobj = NULL; - return GL_FALSE; - } - - rmesa->state.texture.unit[unit].texobj = radeon_tex_obj(ctx->Texture.Unit[unit]._Current); - return GL_TRUE; -} - - -void r200UpdateTextureState( struct gl_context *ctx ) -{ - r200ContextPtr rmesa = R200_CONTEXT(ctx); - GLboolean ok; - GLuint dbg; - - /* NOTE: must not manipulate rmesa->state.texture.unit[].unitneeded or - rmesa->state.envneeded before a R200_STATECHANGE (or R200_NEWPRIM) since - we use these to determine if we want to emit the corresponding state - atoms. */ - R200_NEWPRIM( rmesa ); - - if (_mesa_ati_fragment_shader_enabled(ctx)) { - GLuint i; - for (i = 0; i < R200_MAX_TEXTURE_UNITS; i++) { - if (ctx->Texture.Unit[i]._Current) - rmesa->state.texture.unit[i].unitneeded = 1 << _mesa_tex_target_to_index(ctx, ctx->Texture.Unit[i]._Current->Target); - else - rmesa->state.texture.unit[i].unitneeded = 0; - } - ok = GL_TRUE; - } - else { - ok = r200UpdateAllTexEnv( ctx ); - } - if (ok) { - ok = (r200UpdateTextureUnit( ctx, 0 ) && - r200UpdateTextureUnit( ctx, 1 ) && - r200UpdateTextureUnit( ctx, 2 ) && - r200UpdateTextureUnit( ctx, 3 ) && - r200UpdateTextureUnit( ctx, 4 ) && - r200UpdateTextureUnit( ctx, 5 )); - } - - if (ok && _mesa_ati_fragment_shader_enabled(ctx)) { - r200UpdateFragmentShader(ctx); - } - - FALLBACK( rmesa, R200_FALLBACK_TEXTURE, !ok ); - - if (rmesa->radeon.TclFallback) - r200ChooseVertexState( ctx ); - - - if (rmesa->radeon.radeonScreen->chip_family == CHIP_FAMILY_R200) { - - /* - * T0 hang workaround ------------- - * not needed for r200 derivatives - */ - if ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_ENABLE_MASK) == R200_TEX_0_ENABLE && - (rmesa->hw.tex[0].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK) > R200_MIN_FILTER_LINEAR) { - - R200_STATECHANGE(rmesa, ctx); - R200_STATECHANGE(rmesa, tex[1]); - rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= R200_TEX_1_ENABLE; - if (!(rmesa->hw.cst.cmd[CST_PP_CNTL_X] & R200_PPX_TEX_1_ENABLE)) - rmesa->hw.tex[1].cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK; - rmesa->hw.tex[1].cmd[TEX_PP_TXFORMAT] |= R200_TXFORMAT_LOOKUP_DISABLE; - } - else if (!_mesa_ati_fragment_shader_enabled(ctx)) { - if ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_1_ENABLE) && - (rmesa->hw.tex[1].cmd[TEX_PP_TXFORMAT] & R200_TXFORMAT_LOOKUP_DISABLE)) { - R200_STATECHANGE(rmesa, tex[1]); - rmesa->hw.tex[1].cmd[TEX_PP_TXFORMAT] &= ~R200_TXFORMAT_LOOKUP_DISABLE; - } - } - /* do the same workaround for the first pass of a fragment shader. - * completely unknown if necessary / sufficient. - */ - if ((rmesa->hw.cst.cmd[CST_PP_CNTL_X] & R200_PPX_TEX_ENABLE_MASK) == R200_PPX_TEX_0_ENABLE && - (rmesa->hw.tex[0].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK) > R200_MIN_FILTER_LINEAR) { - - R200_STATECHANGE(rmesa, cst); - R200_STATECHANGE(rmesa, tex[1]); - rmesa->hw.cst.cmd[CST_PP_CNTL_X] |= R200_PPX_TEX_1_ENABLE; - if (!(rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_1_ENABLE)) - rmesa->hw.tex[1].cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK; - rmesa->hw.tex[1].cmd[TEX_PP_TXMULTI_CTL] |= R200_PASS1_TXFORMAT_LOOKUP_DISABLE; - } - - /* maybe needs to be done pairwise due to 2 parallel (physical) tex units ? - looks like that's not the case, if 8500/9100 owners don't complain remove this... - for ( i = 0; i < ctx->Const.MaxTextureUnits; i += 2) { - if (((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & ((R200_TEX_0_ENABLE | - R200_TEX_1_ENABLE ) << i)) == (R200_TEX_0_ENABLE << i)) && - ((rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK) > - R200_MIN_FILTER_LINEAR)) { - R200_STATECHANGE(rmesa, ctx); - R200_STATECHANGE(rmesa, tex[i+1]); - rmesa->hw.ctx.cmd[CTX_PP_CNTL] |= (R200_TEX_1_ENABLE << i); - rmesa->hw.tex[i+1].cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK; - rmesa->hw.tex[i+1].cmd[TEX_PP_TXFORMAT] |= 0x08000000; - } - else { - if ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & (R200_TEX_1_ENABLE << i)) && - (rmesa->hw.tex[i+1].cmd[TEX_PP_TXFORMAT] & 0x08000000)) { - R200_STATECHANGE(rmesa, tex[i+1]); - rmesa->hw.tex[i+1].cmd[TEX_PP_TXFORMAT] &= ~0x08000000; - } - } - } */ - - /* - * Texture cache LRU hang workaround ------------- - * not needed for r200 derivatives - * hopefully this covers first pass of a shader as well - */ - - /* While the cases below attempt to only enable the workaround in the - * specific cases necessary, they were insufficient. See bugzilla #1519, - * #729, #814. Tests with quake3 showed no impact on performance. - */ - dbg = 0x6; - - /* - if (((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & (R200_TEX_0_ENABLE )) && - ((((rmesa->hw.tex[0].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK)) & - 0x04) == 0)) || - ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_2_ENABLE) && - ((((rmesa->hw.tex[2].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK)) & - 0x04) == 0)) || - ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_4_ENABLE) && - ((((rmesa->hw.tex[4].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK)) & - 0x04) == 0))) - { - dbg |= 0x02; - } - - if (((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & (R200_TEX_1_ENABLE )) && - ((((rmesa->hw.tex[1].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK)) & - 0x04) == 0)) || - ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_3_ENABLE) && - ((((rmesa->hw.tex[3].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK)) & - 0x04) == 0)) || - ((rmesa->hw.ctx.cmd[CTX_PP_CNTL] & R200_TEX_5_ENABLE) && - ((((rmesa->hw.tex[5].cmd[TEX_PP_TXFILTER] & R200_MIN_FILTER_MASK)) & - 0x04) == 0))) - { - dbg |= 0x04; - }*/ - - if (dbg != rmesa->hw.tam.cmd[TAM_DEBUG3]) { - R200_STATECHANGE( rmesa, tam ); - rmesa->hw.tam.cmd[TAM_DEBUG3] = dbg; - if (0) printf("TEXCACHE LRU HANG WORKAROUND %x\n", dbg); - } - } -} diff --git a/src/mesa/drivers/dri/r200/r200_vertprog.c b/src/mesa/drivers/dri/r200/r200_vertprog.c deleted file mode 100644 index abd508d51d1..00000000000 --- a/src/mesa/drivers/dri/r200/r200_vertprog.c +++ /dev/null @@ -1,1261 +0,0 @@ -/************************************************************************** - -Copyright (C) 2005 Aapo Tahkola. - -All Rights Reserved. - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -on the rights to use, copy, modify, merge, publish, distribute, sub -license, and/or sell copies of the Software, and to permit persons to whom -the Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the next -paragraph) shall be included in all copies or substantial portions of the -Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, -DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR -OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE -USE OR OTHER DEALINGS IN THE SOFTWARE. - -**************************************************************************/ - -/* - * Authors: - * Aapo Tahkola <aet@rasterburn.org> - * Roland Scheidegger <rscheidegger_lists@hispeed.ch> - */ - -#include "main/errors.h" -#include "main/glheader.h" -#include "main/macros.h" -#include "main/enums.h" -#include "program/program.h" -#include "program/prog_instruction.h" -#include "program/prog_parameter.h" -#include "program/prog_statevars.h" -#include "program/programopt.h" -#include "tnl/tnl.h" - -#include "r200_context.h" -#include "r200_vertprog.h" -#include "r200_ioctl.h" -#include "r200_tcl.h" - -#if SWIZZLE_X != VSF_IN_COMPONENT_X || \ - SWIZZLE_Y != VSF_IN_COMPONENT_Y || \ - SWIZZLE_Z != VSF_IN_COMPONENT_Z || \ - SWIZZLE_W != VSF_IN_COMPONENT_W || \ - SWIZZLE_ZERO != VSF_IN_COMPONENT_ZERO || \ - SWIZZLE_ONE != VSF_IN_COMPONENT_ONE || \ - WRITEMASK_X != VSF_FLAG_X || \ - WRITEMASK_Y != VSF_FLAG_Y || \ - WRITEMASK_Z != VSF_FLAG_Z || \ - WRITEMASK_W != VSF_FLAG_W -#error Cannot change these! -#endif - -#define SCALAR_FLAG (1<<31) -#define FLAG_MASK (1<<31) -#define OP_MASK (0xf) /* we are unlikely to have more than 15 */ -#define OPN(operator, ip) {#operator, OPCODE_##operator, ip} - -static struct{ - char *name; - int opcode; - unsigned long ip; /* number of input operands and flags */ -}op_names[]={ - OPN(ABS, 1), - OPN(ADD, 2), - OPN(ARL, 1|SCALAR_FLAG), - OPN(DP3, 2), - OPN(DP4, 2), - OPN(DPH, 2), - OPN(DST, 2), - OPN(EX2, 1|SCALAR_FLAG), - OPN(EXP, 1|SCALAR_FLAG), - OPN(FLR, 1), - OPN(FRC, 1), - OPN(LG2, 1|SCALAR_FLAG), - OPN(LIT, 1), - OPN(LOG, 1|SCALAR_FLAG), - OPN(MAD, 3), - OPN(MAX, 2), - OPN(MIN, 2), - OPN(MOV, 1), - OPN(MUL, 2), - OPN(POW, 2|SCALAR_FLAG), - OPN(RCP, 1|SCALAR_FLAG), - OPN(RSQ, 1|SCALAR_FLAG), - OPN(SGE, 2), - OPN(SLT, 2), - OPN(SUB, 2), - OPN(SWZ, 1), - OPN(XPD, 2), - OPN(END, 0), -}; -#undef OPN - -static GLboolean r200VertexProgUpdateParams(struct gl_context *ctx, struct r200_vertex_program *vp) -{ - r200ContextPtr rmesa = R200_CONTEXT( ctx ); - GLfloat *fcmd = (GLfloat *)&rmesa->hw.vpp[0].cmd[VPP_CMD_0 + 1]; - int pi; - struct gl_program *mesa_vp = &vp->mesa_program; - struct gl_program_parameter_list *paramList; - drm_radeon_cmd_header_t tmp; - - R200_STATECHANGE( rmesa, vpp[0] ); - R200_STATECHANGE( rmesa, vpp[1] ); - assert(mesa_vp->Parameters); - _mesa_load_state_parameters(ctx, mesa_vp->Parameters); - paramList = mesa_vp->Parameters; - - if(paramList->NumParameters > R200_VSF_MAX_PARAM){ - fprintf(stderr, "%s:Params exhausted\n", __func__); - return GL_FALSE; - } - - for(pi = 0; pi < paramList->NumParameters; pi++) { - unsigned pvo = paramList->Parameters[pi].ValueOffset; - - switch(paramList->Parameters[pi].Type) { - case PROGRAM_STATE_VAR: - //fprintf(stderr, "%s", vp->Parameters->Parameters[pi].Name); - case PROGRAM_CONSTANT: - *fcmd++ = paramList->ParameterValues[pvo + 0].f; - *fcmd++ = paramList->ParameterValues[pvo + 1].f; - *fcmd++ = paramList->ParameterValues[pvo + 2].f; - *fcmd++ = paramList->ParameterValues[pvo + 3].f; - break; - default: - _mesa_problem(NULL, "Bad param type in %s", __func__); - break; - } - if (pi == 95) { - fcmd = (GLfloat *)&rmesa->hw.vpp[1].cmd[VPP_CMD_0 + 1]; - } - } - /* hack up the cmd_size so not the whole state atom is emitted always. */ - rmesa->hw.vpp[0].cmd_size = - 1 + 4 * ((paramList->NumParameters > 96) ? 96 : paramList->NumParameters); - tmp.i = rmesa->hw.vpp[0].cmd[VPP_CMD_0]; - tmp.veclinear.count = (paramList->NumParameters > 96) ? 96 : paramList->NumParameters; - rmesa->hw.vpp[0].cmd[VPP_CMD_0] = tmp.i; - if (paramList->NumParameters > 96) { - rmesa->hw.vpp[1].cmd_size = 1 + 4 * (paramList->NumParameters - 96); - tmp.i = rmesa->hw.vpp[1].cmd[VPP_CMD_0]; - tmp.veclinear.count = paramList->NumParameters - 96; - rmesa->hw.vpp[1].cmd[VPP_CMD_0] = tmp.i; - } - return GL_TRUE; -} - -static inline unsigned long t_dst_mask(GLuint mask) -{ - /* WRITEMASK_* is equivalent to VSF_FLAG_* */ - return mask & VSF_FLAG_ALL; -} - -static unsigned long t_dst(struct prog_dst_register *dst) -{ - switch(dst->File) { - case PROGRAM_TEMPORARY: - return ((dst->Index << R200_VPI_OUT_REG_INDEX_SHIFT) - | R200_VSF_OUT_CLASS_TMP); - case PROGRAM_OUTPUT: - switch (dst->Index) { - case VARYING_SLOT_POS: - return R200_VSF_OUT_CLASS_RESULT_POS; - case VARYING_SLOT_COL0: - return R200_VSF_OUT_CLASS_RESULT_COLOR; - case VARYING_SLOT_COL1: - return ((1 << R200_VPI_OUT_REG_INDEX_SHIFT) - | R200_VSF_OUT_CLASS_RESULT_COLOR); - case VARYING_SLOT_FOGC: - return R200_VSF_OUT_CLASS_RESULT_FOGC; - case VARYING_SLOT_TEX0: - case VARYING_SLOT_TEX1: - case VARYING_SLOT_TEX2: - case VARYING_SLOT_TEX3: - case VARYING_SLOT_TEX4: - case VARYING_SLOT_TEX5: - return (((dst->Index - VARYING_SLOT_TEX0) << R200_VPI_OUT_REG_INDEX_SHIFT) - | R200_VSF_OUT_CLASS_RESULT_TEXC); - case VARYING_SLOT_PSIZ: - return R200_VSF_OUT_CLASS_RESULT_POINTSIZE; - default: - fprintf(stderr, "problem in %s, unknown dst output reg %d\n", __func__, dst->Index); - exit(0); - return 0; - } - case PROGRAM_ADDRESS: - assert (dst->Index == 0); - return R200_VSF_OUT_CLASS_ADDR; - default: - fprintf(stderr, "problem in %s, unknown register type %d\n", __func__, dst->File); - exit(0); - return 0; - } -} - -static unsigned long t_src_class(gl_register_file file) -{ - - switch(file){ - case PROGRAM_TEMPORARY: - return VSF_IN_CLASS_TMP; - - case PROGRAM_INPUT: - return VSF_IN_CLASS_ATTR; - - case PROGRAM_CONSTANT: - case PROGRAM_STATE_VAR: - return VSF_IN_CLASS_PARAM; - /* - case PROGRAM_OUTPUT: - case PROGRAM_ADDRESS: - */ - default: - fprintf(stderr, "problem in %s", __func__); - exit(0); - } -} - -static inline unsigned long t_swizzle(GLubyte swizzle) -{ -/* this is in fact a NOP as the Mesa SWIZZLE_* are all identical to VSF_IN_COMPONENT_* */ - return swizzle; -} - -#if 0 -static void vp_dump_inputs(struct r200_vertex_program *vp, char *caller) -{ - int i; - - if(vp == NULL){ - fprintf(stderr, "vp null in call to %s from %s\n", __func__, caller); - return ; - } - - fprintf(stderr, "%s:<", caller); - for(i=0; i < VERT_ATTRIB_MAX; i++) - fprintf(stderr, "%d ", vp->inputs[i]); - fprintf(stderr, ">\n"); - -} -#endif - -static unsigned long t_src_index(struct r200_vertex_program *vp, struct prog_src_register *src) -{ -/* - int i; - int max_reg = -1; -*/ - if(src->File == PROGRAM_INPUT){ -/* if(vp->inputs[src->Index] != -1) - return vp->inputs[src->Index]; - - for(i=0; i < VERT_ATTRIB_MAX; i++) - if(vp->inputs[i] > max_reg) - max_reg = vp->inputs[i]; - - vp->inputs[src->Index] = max_reg+1;*/ - - //vp_dump_inputs(vp, __func__); - assert(vp->inputs[src->Index] != -1); - return vp->inputs[src->Index]; - } else { - if (src->Index < 0) { - fprintf(stderr, "WARNING negative offsets for indirect addressing do not work\n"); - return 0; - } - return src->Index; - } -} - -static unsigned long t_src(struct r200_vertex_program *vp, struct prog_src_register *src) -{ - - return MAKE_VSF_SOURCE(t_src_index(vp, src), - t_swizzle(GET_SWZ(src->Swizzle, 0)), - t_swizzle(GET_SWZ(src->Swizzle, 1)), - t_swizzle(GET_SWZ(src->Swizzle, 2)), - t_swizzle(GET_SWZ(src->Swizzle, 3)), - t_src_class(src->File), - src->Negate) | (src->RelAddr << 4); -} - -static unsigned long t_src_scalar(struct r200_vertex_program *vp, struct prog_src_register *src) -{ - - return MAKE_VSF_SOURCE(t_src_index(vp, src), - t_swizzle(GET_SWZ(src->Swizzle, 0)), - t_swizzle(GET_SWZ(src->Swizzle, 0)), - t_swizzle(GET_SWZ(src->Swizzle, 0)), - t_swizzle(GET_SWZ(src->Swizzle, 0)), - t_src_class(src->File), - src->Negate ? VSF_FLAG_ALL : VSF_FLAG_NONE) | (src->RelAddr << 4); -} - -static unsigned long t_opcode(enum prog_opcode opcode) -{ - - switch(opcode){ - case OPCODE_ADD: return R200_VPI_OUT_OP_ADD; - /* FIXME: ARL works fine, but negative offsets won't work - fglrx just - * seems to ignore neg offsets which isn't quite correct... - */ - case OPCODE_ARL: return R200_VPI_OUT_OP_ARL; - case OPCODE_DP4: return R200_VPI_OUT_OP_DOT; - case OPCODE_DST: return R200_VPI_OUT_OP_DST; - case OPCODE_EX2: return R200_VPI_OUT_OP_EX2; - case OPCODE_EXP: return R200_VPI_OUT_OP_EXP; - case OPCODE_FRC: return R200_VPI_OUT_OP_FRC; - case OPCODE_LG2: return R200_VPI_OUT_OP_LG2; - case OPCODE_LIT: return R200_VPI_OUT_OP_LIT; - case OPCODE_LOG: return R200_VPI_OUT_OP_LOG; - case OPCODE_MAX: return R200_VPI_OUT_OP_MAX; - case OPCODE_MIN: return R200_VPI_OUT_OP_MIN; - case OPCODE_MUL: return R200_VPI_OUT_OP_MUL; - case OPCODE_RCP: return R200_VPI_OUT_OP_RCP; - case OPCODE_RSQ: return R200_VPI_OUT_OP_RSQ; - case OPCODE_SGE: return R200_VPI_OUT_OP_SGE; - case OPCODE_SLT: return R200_VPI_OUT_OP_SLT; - - default: - fprintf(stderr, "%s: Should not be called with opcode %d!", __func__, opcode); - } - exit(-1); - return 0; -} - -static unsigned long op_operands(enum prog_opcode opcode) -{ - int i; - - /* Can we trust mesas opcodes to be in order ? */ - for(i=0; i < sizeof(op_names) / sizeof(*op_names); i++) - if(op_names[i].opcode == opcode) - return op_names[i].ip; - - fprintf(stderr, "op %d not found in op_names\n", opcode); - exit(-1); - return 0; -} - -/* TODO: Get rid of t_src_class call */ -#define CMP_SRCS(a, b) (((a.RelAddr != b.RelAddr) || (a.Index != b.Index)) && \ - ((t_src_class(a.File) == VSF_IN_CLASS_PARAM && \ - t_src_class(b.File) == VSF_IN_CLASS_PARAM) || \ - (t_src_class(a.File) == VSF_IN_CLASS_ATTR && \ - t_src_class(b.File) == VSF_IN_CLASS_ATTR))) - -/* fglrx on rv250 codes up unused sources as follows: - unused but necessary sources are same as previous source, zero-ed out. - unnecessary sources are same as previous source but with VSF_IN_CLASS_NONE set. - i.e. an add (2 args) has its 2nd arg (if you use it as mov) zero-ed out, and 3rd arg - set to VSF_IN_CLASS_NONE. Not sure if strictly necessary. */ - -/* use these simpler definitions. Must obviously not be used with not yet set up regs. - Those are NOT semantically equivalent to the r300 ones, requires code changes */ -#define ZERO_SRC_0 (((o_inst->src0 & ~(0xfff << R200_VPI_IN_X_SHIFT)) \ - | ((R200_VPI_IN_SELECT_ZERO << R200_VPI_IN_X_SHIFT) \ - | (R200_VPI_IN_SELECT_ZERO << R200_VPI_IN_Y_SHIFT) \ - | (R200_VPI_IN_SELECT_ZERO << R200_VPI_IN_Z_SHIFT) \ - | (R200_VPI_IN_SELECT_ZERO << R200_VPI_IN_W_SHIFT)))) - -#define ZERO_SRC_1 (((o_inst->src1 & ~(0xfff << R200_VPI_IN_X_SHIFT)) \ - | ((R200_VPI_IN_SELECT_ZERO << R200_VPI_IN_X_SHIFT) \ - | (R200_VPI_IN_SELECT_ZERO << R200_VPI_IN_Y_SHIFT) \ - | (R200_VPI_IN_SELECT_ZERO << R200_VPI_IN_Z_SHIFT) \ - | (R200_VPI_IN_SELECT_ZERO << R200_VPI_IN_W_SHIFT)))) - -#define ZERO_SRC_2 (((o_inst->src2 & ~(0xfff << R200_VPI_IN_X_SHIFT)) \ - | ((R200_VPI_IN_SELECT_ZERO << R200_VPI_IN_X_SHIFT) \ - | (R200_VPI_IN_SELECT_ZERO << R200_VPI_IN_Y_SHIFT) \ - | (R200_VPI_IN_SELECT_ZERO << R200_VPI_IN_Z_SHIFT) \ - | (R200_VPI_IN_SELECT_ZERO << R200_VPI_IN_W_SHIFT)))) - -#define UNUSED_SRC_0 ((o_inst->src0 & ~15) | 9) - -#define UNUSED_SRC_1 ((o_inst->src1 & ~15) | 9) - -#define UNUSED_SRC_2 ((o_inst->src2 & ~15) | 9) - - -/** - * Generate an R200 vertex program from Mesa's internal representation. - * - * \return GL_TRUE for success, GL_FALSE for failure. - */ -static GLboolean r200_translate_vertex_program(struct gl_context *ctx, struct r200_vertex_program *vp) -{ - struct gl_program *mesa_vp = &vp->mesa_program; - struct prog_instruction *vpi; - int i; - VERTEX_SHADER_INSTRUCTION *o_inst; - unsigned long operands; - int are_srcs_scalar; - unsigned long hw_op; - int dofogfix = 0; - int fog_temp_i = 0; - int free_inputs; - int array_count = 0; - int u_temp_used; - - vp->native = GL_FALSE; - vp->translated = GL_TRUE; - vp->fogmode = ctx->Fog.Mode; - - if (mesa_vp->arb.NumInstructions == 0) - return GL_FALSE; - -#if 0 - if ((mesa_vp->info.inputs_read & - ~(VERT_BIT_POS | VERT_BIT_NORMAL | VERT_BIT_COLOR0 | VERT_BIT_COLOR1 | - VERT_BIT_FOG | VERT_BIT_TEX0 | VERT_BIT_TEX1 | VERT_BIT_TEX2 | - VERT_BIT_TEX3 | VERT_BIT_TEX4 | VERT_BIT_TEX5)) != 0) { - if (R200_DEBUG & RADEON_FALLBACKS) { - fprintf(stderr, "can't handle vert prog inputs 0x%x\n", - mesa_vp->info.inputs_read); - } - return GL_FALSE; - } -#endif - - if ((mesa_vp->info.outputs_written & - ~((1 << VARYING_SLOT_POS) | (1 << VARYING_SLOT_COL0) | (1 << VARYING_SLOT_COL1) | - (1 << VARYING_SLOT_FOGC) | (1 << VARYING_SLOT_TEX0) | (1 << VARYING_SLOT_TEX1) | - (1 << VARYING_SLOT_TEX2) | (1 << VARYING_SLOT_TEX3) | (1 << VARYING_SLOT_TEX4) | - (1 << VARYING_SLOT_TEX5) | (1 << VARYING_SLOT_PSIZ))) != 0) { - if (R200_DEBUG & RADEON_FALLBACKS) { - fprintf(stderr, "can't handle vert prog outputs 0x%llx\n", - (unsigned long long) mesa_vp->info.outputs_written); - } - return GL_FALSE; - } - - /* Initial value should be last tmp reg that hw supports. - Strangely enough r300 doesnt mind even though these would be out of range. - Smart enough to realize that it doesnt need it? */ - int u_temp_i = R200_VSF_MAX_TEMPS - 1; - struct prog_src_register src[3]; - struct prog_dst_register dst; - -/* FIXME: is changing the prog safe to do here? */ - if (mesa_vp->arb.IsPositionInvariant && - /* make sure we only do this once */ - !(mesa_vp->info.outputs_written & (1 << VARYING_SLOT_POS))) { - _mesa_insert_mvp_code(ctx, mesa_vp); - } - - /* for fogc, can't change mesa_vp, as it would hose swtnl, and exp with - base e isn't directly available neither. */ - if ((mesa_vp->info.outputs_written & (1 << VARYING_SLOT_FOGC)) && - !vp->fogpidx) { - struct gl_program_parameter_list *paramList; - gl_state_index16 tokens[STATE_LENGTH] = { STATE_FOG_PARAMS, 0, 0, 0 }; - paramList = mesa_vp->Parameters; - vp->fogpidx = _mesa_add_state_reference(paramList, tokens); - } - - vp->pos_end = 0; - mesa_vp->arb.NumNativeInstructions = 0; - if (mesa_vp->Parameters) - mesa_vp->arb.NumNativeParameters = mesa_vp->Parameters->NumParameters; - else - mesa_vp->arb.NumNativeParameters = 0; - - for(i = 0; i < VERT_ATTRIB_MAX; i++) - vp->inputs[i] = -1; - for(i = 0; i < 15; i++) - vp->inputmap_rev[i] = 255; - free_inputs = 0x2ffd; - -/* fglrx uses fixed inputs as follows for conventional attribs. - generic attribs use non-fixed assignment, fglrx will always use the - lowest attrib values available. We'll just do the same. - There are 12 generic attribs possible, corresponding to attrib 0, 2-11 - and 13 in a hw vertex prog. - attr 1 and 12 aren't used for generic attribs as those cannot be made vec4 - (correspond to vertex normal/weight - maybe weight actually could be made vec4). - Additionally, not more than 12 arrays in total are possible I think. - attr 0 is pos, R200_VTX_XY1|R200_VTX_Z1|R200_VTX_W1 in R200_SE_VTX_FMT_0 - attr 2-5 use colors 0-3 (R200_VTX_FP_RGBA << R200_VTX_COLOR_0/1/2/3_SHIFT in R200_SE_VTX_FMT_0) - attr 6-11 use tex 0-5 (4 << R200_VTX_TEX0/1/2/3/4/5_COMP_CNT_SHIFT in R200_SE_VTX_FMT_1) - attr 13 uses vtx1 pos (R200_VTX_XY1|R200_VTX_Z1|R200_VTX_W1 in R200_SE_VTX_FMT_0) -*/ - -/* attr 4,5 and 13 are only used with generic attribs. - Haven't seen attr 14 used, maybe that's for the hw pointsize vec1 (which is - not possibe to use with vertex progs as it is lacking in vert prog specification) */ -/* may look different when using idx buf / input_route instead of se_vtx_fmt? */ - if (mesa_vp->info.inputs_read & VERT_BIT_POS) { - vp->inputs[VERT_ATTRIB_POS] = 0; - vp->inputmap_rev[0] = VERT_ATTRIB_POS; - free_inputs &= ~(1 << 0); - array_count++; - } - if (mesa_vp->info.inputs_read & VERT_BIT_NORMAL) { - vp->inputs[VERT_ATTRIB_NORMAL] = 1; - vp->inputmap_rev[2] = VERT_ATTRIB_NORMAL; - array_count++; - } - if (mesa_vp->info.inputs_read & VERT_BIT_COLOR0) { - vp->inputs[VERT_ATTRIB_COLOR0] = 2; - vp->inputmap_rev[4] = VERT_ATTRIB_COLOR0; - free_inputs &= ~(1 << 2); - array_count++; - } - if (mesa_vp->info.inputs_read & VERT_BIT_COLOR1) { - vp->inputs[VERT_ATTRIB_COLOR1] = 3; - vp->inputmap_rev[5] = VERT_ATTRIB_COLOR1; - free_inputs &= ~(1 << 3); - array_count++; - } - if (mesa_vp->info.inputs_read & VERT_BIT_FOG) { - vp->inputs[VERT_ATTRIB_FOG] = 15; array_count++; - vp->inputmap_rev[3] = VERT_ATTRIB_FOG; - array_count++; - } - /* VERT_ATTRIB_TEX0-5 */ - for (i = 0; i <= 5; i++) { - if (mesa_vp->info.inputs_read & VERT_BIT_TEX(i)) { - vp->inputs[VERT_ATTRIB_TEX(i)] = i + 6; - vp->inputmap_rev[8 + i] = VERT_ATTRIB_TEX(i); - free_inputs &= ~(1 << (i + 6)); - array_count++; - } - } - /* using VERT_ATTRIB_TEX6/7 would be illegal */ - for (; i < VERT_ATTRIB_TEX_MAX; i++) { - if (mesa_vp->info.inputs_read & VERT_BIT_TEX(i)) { - if (R200_DEBUG & RADEON_FALLBACKS) { - fprintf(stderr, "texture attribute %d in vert prog\n", i); - } - return GL_FALSE; - } - } - /* completely ignore aliasing? */ - for (i = 0; i < VERT_ATTRIB_GENERIC_MAX; i++) { - int j; - /* completely ignore aliasing? */ - if (mesa_vp->info.inputs_read & VERT_BIT_GENERIC(i)) { - array_count++; - if (array_count > 12) { - if (R200_DEBUG & RADEON_FALLBACKS) { - fprintf(stderr, "more than 12 attribs used in vert prog\n"); - } - return GL_FALSE; - } - for (j = 0; j < 14; j++) { - /* will always find one due to limited array_count */ - if (free_inputs & (1 << j)) { - free_inputs &= ~(1 << j); - vp->inputs[VERT_ATTRIB_GENERIC(i)] = j; - if (j == 0) { - /* mapped to pos */ - vp->inputmap_rev[j] = VERT_ATTRIB_GENERIC(i); - } else if (j < 12) { - /* mapped to col/tex */ - vp->inputmap_rev[j + 2] = VERT_ATTRIB_GENERIC(i); - } else { - /* mapped to pos1 */ - vp->inputmap_rev[j + 1] = VERT_ATTRIB_GENERIC(i); - } - break; - } - } - } - } - - if (!(mesa_vp->info.outputs_written & (1 << VARYING_SLOT_POS))) { - if (R200_DEBUG & RADEON_FALLBACKS) { - fprintf(stderr, "can't handle vert prog without position output\n"); - } - return GL_FALSE; - } - if (free_inputs & 1) { - if (R200_DEBUG & RADEON_FALLBACKS) { - fprintf(stderr, "can't handle vert prog without position input\n"); - } - return GL_FALSE; - } - - o_inst = vp->instr; - for (vpi = mesa_vp->arb.Instructions; vpi->Opcode != OPCODE_END; vpi++, o_inst++){ - operands = op_operands(vpi->Opcode); - are_srcs_scalar = operands & SCALAR_FLAG; - operands &= OP_MASK; - - for(i = 0; i < operands; i++) { - src[i] = vpi->SrcReg[i]; - /* hack up default attrib values as per spec as swizzling. - normal, fog, secondary color. Crazy? - May need more if we don't submit vec4 elements? */ - if (src[i].File == PROGRAM_INPUT) { - if (src[i].Index == VERT_ATTRIB_NORMAL) { - int j; - for (j = 0; j < 4; j++) { - if (GET_SWZ(src[i].Swizzle, j) == SWIZZLE_W) { - src[i].Swizzle &= ~(SWIZZLE_W << (j*3)); - src[i].Swizzle |= SWIZZLE_ONE << (j*3); - } - } - } - else if (src[i].Index == VERT_ATTRIB_COLOR1) { - int j; - for (j = 0; j < 4; j++) { - if (GET_SWZ(src[i].Swizzle, j) == SWIZZLE_W) { - src[i].Swizzle &= ~(SWIZZLE_W << (j*3)); - src[i].Swizzle |= SWIZZLE_ZERO << (j*3); - } - } - } - else if (src[i].Index == VERT_ATTRIB_FOG) { - int j; - for (j = 0; j < 4; j++) { - if (GET_SWZ(src[i].Swizzle, j) == SWIZZLE_W) { - src[i].Swizzle &= ~(SWIZZLE_W << (j*3)); - src[i].Swizzle |= SWIZZLE_ONE << (j*3); - } - else if ((GET_SWZ(src[i].Swizzle, j) == SWIZZLE_Y) || - GET_SWZ(src[i].Swizzle, j) == SWIZZLE_Z) { - src[i].Swizzle &= ~(SWIZZLE_W << (j*3)); - src[i].Swizzle |= SWIZZLE_ZERO << (j*3); - } - } - } - } - } - - if(operands == 3){ - if( CMP_SRCS(src[1], src[2]) || CMP_SRCS(src[0], src[2]) ){ - o_inst->op = MAKE_VSF_OP(R200_VPI_OUT_OP_ADD, - (u_temp_i << R200_VPI_OUT_REG_INDEX_SHIFT) | R200_VSF_OUT_CLASS_TMP, - VSF_FLAG_ALL); - - o_inst->src0 = MAKE_VSF_SOURCE(t_src_index(vp, &src[2]), - SWIZZLE_X, SWIZZLE_Y, - SWIZZLE_Z, SWIZZLE_W, - t_src_class(src[2].File), VSF_FLAG_NONE) | (src[2].RelAddr << 4); - - o_inst->src1 = ZERO_SRC_0; - o_inst->src2 = UNUSED_SRC_1; - o_inst++; - - src[2].File = PROGRAM_TEMPORARY; - src[2].Index = u_temp_i; - src[2].RelAddr = 0; - u_temp_i--; - } - } - - if(operands >= 2){ - if( CMP_SRCS(src[1], src[0]) ){ - o_inst->op = MAKE_VSF_OP(R200_VPI_OUT_OP_ADD, - (u_temp_i << R200_VPI_OUT_REG_INDEX_SHIFT) | R200_VSF_OUT_CLASS_TMP, - VSF_FLAG_ALL); - - o_inst->src0 = MAKE_VSF_SOURCE(t_src_index(vp, &src[0]), - SWIZZLE_X, SWIZZLE_Y, - SWIZZLE_Z, SWIZZLE_W, - t_src_class(src[0].File), VSF_FLAG_NONE) | (src[0].RelAddr << 4); - - o_inst->src1 = ZERO_SRC_0; - o_inst->src2 = UNUSED_SRC_1; - o_inst++; - - src[0].File = PROGRAM_TEMPORARY; - src[0].Index = u_temp_i; - src[0].RelAddr = 0; - u_temp_i--; - } - } - - dst = vpi->DstReg; - if (dst.File == PROGRAM_OUTPUT && - dst.Index == VARYING_SLOT_FOGC && - dst.WriteMask & WRITEMASK_X) { - fog_temp_i = u_temp_i; - dst.File = PROGRAM_TEMPORARY; - dst.Index = fog_temp_i; - dofogfix = 1; - u_temp_i--; - } - - /* These ops need special handling. */ - switch(vpi->Opcode){ - case OPCODE_POW: -/* pow takes only one argument, first scalar is in slot x, 2nd in slot z (other slots don't matter). - So may need to insert additional instruction */ - if ((src[0].File == src[1].File) && - (src[0].Index == src[1].Index)) { - o_inst->op = MAKE_VSF_OP(R200_VPI_OUT_OP_POW, t_dst(&dst), - t_dst_mask(dst.WriteMask)); - o_inst->src0 = MAKE_VSF_SOURCE(t_src_index(vp, &src[0]), - t_swizzle(GET_SWZ(src[0].Swizzle, 0)), - SWIZZLE_ZERO, - t_swizzle(GET_SWZ(src[1].Swizzle, 0)), - SWIZZLE_ZERO, - t_src_class(src[0].File), - src[0].Negate) | (src[0].RelAddr << 4); - o_inst->src1 = UNUSED_SRC_0; - o_inst->src2 = UNUSED_SRC_0; - } - else { - o_inst->op = MAKE_VSF_OP(R200_VPI_OUT_OP_ADD, - (u_temp_i << R200_VPI_OUT_REG_INDEX_SHIFT) | R200_VSF_OUT_CLASS_TMP, - VSF_FLAG_ALL); - o_inst->src0 = MAKE_VSF_SOURCE(t_src_index(vp, &src[0]), - t_swizzle(GET_SWZ(src[0].Swizzle, 0)), - SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO, - t_src_class(src[0].File), - src[0].Negate ? VSF_FLAG_ALL : VSF_FLAG_NONE) | (src[0].RelAddr << 4); - o_inst->src1 = MAKE_VSF_SOURCE(t_src_index(vp, &src[1]), - SWIZZLE_ZERO, SWIZZLE_ZERO, - t_swizzle(GET_SWZ(src[1].Swizzle, 0)), SWIZZLE_ZERO, - t_src_class(src[1].File), - src[1].Negate ? VSF_FLAG_ALL : VSF_FLAG_NONE) | (src[1].RelAddr << 4); - o_inst->src2 = UNUSED_SRC_1; - o_inst++; - - o_inst->op = MAKE_VSF_OP(R200_VPI_OUT_OP_POW, t_dst(&dst), - t_dst_mask(dst.WriteMask)); - o_inst->src0 = MAKE_VSF_SOURCE(u_temp_i, - VSF_IN_COMPONENT_X, - VSF_IN_COMPONENT_Y, - VSF_IN_COMPONENT_Z, - VSF_IN_COMPONENT_W, - VSF_IN_CLASS_TMP, - VSF_FLAG_NONE); - o_inst->src1 = UNUSED_SRC_0; - o_inst->src2 = UNUSED_SRC_0; - u_temp_i--; - } - goto next; - - case OPCODE_MOV://ADD RESULT 1.X Y Z W PARAM 0{} {X Y Z W} PARAM 0{} {ZERO ZERO ZERO ZERO} - case OPCODE_SWZ: - o_inst->op = MAKE_VSF_OP(R200_VPI_OUT_OP_ADD, t_dst(&dst), - t_dst_mask(dst.WriteMask)); - o_inst->src0 = t_src(vp, &src[0]); - o_inst->src1 = ZERO_SRC_0; - o_inst->src2 = UNUSED_SRC_1; - goto next; - - case OPCODE_MAD: - /* only 2 read ports into temp memory thus may need the macro op MAD_2 - instead (requiring 2 clocks) if all inputs are in temp memory - (and, only if they actually reference 3 distinct temps) */ - hw_op=(src[0].File == PROGRAM_TEMPORARY && - src[1].File == PROGRAM_TEMPORARY && - src[2].File == PROGRAM_TEMPORARY && - (((src[0].RelAddr << 8) | src[0].Index) != ((src[1].RelAddr << 8) | src[1].Index)) && - (((src[0].RelAddr << 8) | src[0].Index) != ((src[2].RelAddr << 8) | src[2].Index)) && - (((src[1].RelAddr << 8) | src[1].Index) != ((src[2].RelAddr << 8) | src[2].Index))) ? - R200_VPI_OUT_OP_MAD_2 : R200_VPI_OUT_OP_MAD; - - o_inst->op = MAKE_VSF_OP(hw_op, t_dst(&dst), - t_dst_mask(dst.WriteMask)); - o_inst->src0 = t_src(vp, &src[0]); -#if 0 -if ((o_inst - vp->instr) == 31) { -/* fix up the broken vertex program of quake4 demo... */ -o_inst->src1 = MAKE_VSF_SOURCE(t_src_index(vp, &src[1]), - SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, - t_src_class(src[1].File), - src[1].Negate) | (src[1].RelAddr << 4); -o_inst->src2 = MAKE_VSF_SOURCE(t_src_index(vp, &src[1]), - SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y, - t_src_class(src[1].File), - src[1].Negate) | (src[1].RelAddr << 4); -} -else { - o_inst->src1 = t_src(vp, &src[1]); - o_inst->src2 = t_src(vp, &src[2]); -} -#else - o_inst->src1 = t_src(vp, &src[1]); - o_inst->src2 = t_src(vp, &src[2]); -#endif - goto next; - - case OPCODE_DP3://DOT RESULT 1.X Y Z W PARAM 0{} {X Y Z ZERO} PARAM 0{} {X Y Z ZERO} - o_inst->op = MAKE_VSF_OP(R200_VPI_OUT_OP_DOT, t_dst(&dst), - t_dst_mask(dst.WriteMask)); - - o_inst->src0 = MAKE_VSF_SOURCE(t_src_index(vp, &src[0]), - t_swizzle(GET_SWZ(src[0].Swizzle, 0)), - t_swizzle(GET_SWZ(src[0].Swizzle, 1)), - t_swizzle(GET_SWZ(src[0].Swizzle, 2)), - SWIZZLE_ZERO, - t_src_class(src[0].File), - src[0].Negate) | (src[0].RelAddr << 4); - - o_inst->src1 = MAKE_VSF_SOURCE(t_src_index(vp, &src[1]), - t_swizzle(GET_SWZ(src[1].Swizzle, 0)), - t_swizzle(GET_SWZ(src[1].Swizzle, 1)), - t_swizzle(GET_SWZ(src[1].Swizzle, 2)), - SWIZZLE_ZERO, - t_src_class(src[1].File), - src[1].Negate) | (src[1].RelAddr << 4); - - o_inst->src2 = UNUSED_SRC_1; - goto next; - - case OPCODE_DPH://DOT RESULT 1.X Y Z W PARAM 0{} {X Y Z ONE} PARAM 0{} {X Y Z W} - o_inst->op = MAKE_VSF_OP(R200_VPI_OUT_OP_DOT, t_dst(&dst), - t_dst_mask(dst.WriteMask)); - - o_inst->src0 = MAKE_VSF_SOURCE(t_src_index(vp, &src[0]), - t_swizzle(GET_SWZ(src[0].Swizzle, 0)), - t_swizzle(GET_SWZ(src[0].Swizzle, 1)), - t_swizzle(GET_SWZ(src[0].Swizzle, 2)), - VSF_IN_COMPONENT_ONE, - t_src_class(src[0].File), - src[0].Negate) | (src[0].RelAddr << 4); - o_inst->src1 = t_src(vp, &src[1]); - o_inst->src2 = UNUSED_SRC_1; - goto next; - - case OPCODE_SUB://ADD RESULT 1.X Y Z W TMP 0{} {X Y Z W} PARAM 1{X Y Z W } {X Y Z W} neg Xneg Yneg Zneg W - o_inst->op = MAKE_VSF_OP(R200_VPI_OUT_OP_ADD, t_dst(&dst), - t_dst_mask(dst.WriteMask)); - - o_inst->src0 = t_src(vp, &src[0]); - o_inst->src1 = MAKE_VSF_SOURCE(t_src_index(vp, &src[1]), - t_swizzle(GET_SWZ(src[1].Swizzle, 0)), - t_swizzle(GET_SWZ(src[1].Swizzle, 1)), - t_swizzle(GET_SWZ(src[1].Swizzle, 2)), - t_swizzle(GET_SWZ(src[1].Swizzle, 3)), - t_src_class(src[1].File), - (!src[1].Negate) ? VSF_FLAG_ALL : VSF_FLAG_NONE) | (src[1].RelAddr << 4); - o_inst->src2 = UNUSED_SRC_1; - goto next; - - case OPCODE_ABS://MAX RESULT 1.X Y Z W PARAM 0{} {X Y Z W} PARAM 0{X Y Z W } {X Y Z W} neg Xneg Yneg Zneg W - o_inst->op=MAKE_VSF_OP(R200_VPI_OUT_OP_MAX, t_dst(&dst), - t_dst_mask(dst.WriteMask)); - - o_inst->src0=t_src(vp, &src[0]); - o_inst->src1=MAKE_VSF_SOURCE(t_src_index(vp, &src[0]), - t_swizzle(GET_SWZ(src[0].Swizzle, 0)), - t_swizzle(GET_SWZ(src[0].Swizzle, 1)), - t_swizzle(GET_SWZ(src[0].Swizzle, 2)), - t_swizzle(GET_SWZ(src[0].Swizzle, 3)), - t_src_class(src[0].File), - (!src[0].Negate) ? VSF_FLAG_ALL : VSF_FLAG_NONE) | (src[0].RelAddr << 4); - o_inst->src2 = UNUSED_SRC_1; - goto next; - - case OPCODE_FLR: - /* FRC TMP 0.X Y Z W PARAM 0{} {X Y Z W} - ADD RESULT 1.X Y Z W PARAM 0{} {X Y Z W} TMP 0{X Y Z W } {X Y Z W} neg Xneg Yneg Zneg W */ - - o_inst->op = MAKE_VSF_OP(R200_VPI_OUT_OP_FRC, - (u_temp_i << R200_VPI_OUT_REG_INDEX_SHIFT) | R200_VSF_OUT_CLASS_TMP, - t_dst_mask(dst.WriteMask)); - - o_inst->src0 = t_src(vp, &src[0]); - o_inst->src1 = UNUSED_SRC_0; - o_inst->src2 = UNUSED_SRC_1; - o_inst++; - - o_inst->op = MAKE_VSF_OP(R200_VPI_OUT_OP_ADD, t_dst(&dst), - t_dst_mask(dst.WriteMask)); - - o_inst->src0 = t_src(vp, &src[0]); - o_inst->src1 = MAKE_VSF_SOURCE(u_temp_i, - VSF_IN_COMPONENT_X, - VSF_IN_COMPONENT_Y, - VSF_IN_COMPONENT_Z, - VSF_IN_COMPONENT_W, - VSF_IN_CLASS_TMP, - /* Not 100% sure about this */ - (!src[0].Negate) ? VSF_FLAG_ALL : VSF_FLAG_NONE/*VSF_FLAG_ALL*/); - - o_inst->src2 = UNUSED_SRC_0; - u_temp_i--; - goto next; - - case OPCODE_XPD: - /* mul r0, r1.yzxw, r2.zxyw - mad r0, -r2.yzxw, r1.zxyw, r0 - */ - hw_op=(src[0].File == PROGRAM_TEMPORARY && - src[1].File == PROGRAM_TEMPORARY && - (((src[0].RelAddr << 8) | src[0].Index) != ((src[1].RelAddr << 8) | src[1].Index))) ? - R200_VPI_OUT_OP_MAD_2 : R200_VPI_OUT_OP_MAD; - - o_inst->op = MAKE_VSF_OP(R200_VPI_OUT_OP_MUL, - (u_temp_i << R200_VPI_OUT_REG_INDEX_SHIFT) | R200_VSF_OUT_CLASS_TMP, - t_dst_mask(dst.WriteMask)); - - o_inst->src0 = MAKE_VSF_SOURCE(t_src_index(vp, &src[0]), - t_swizzle(GET_SWZ(src[0].Swizzle, 1)), // y - t_swizzle(GET_SWZ(src[0].Swizzle, 2)), // z - t_swizzle(GET_SWZ(src[0].Swizzle, 0)), // x - t_swizzle(GET_SWZ(src[0].Swizzle, 3)), // w - t_src_class(src[0].File), - src[0].Negate) | (src[0].RelAddr << 4); - - o_inst->src1 = MAKE_VSF_SOURCE(t_src_index(vp, &src[1]), - t_swizzle(GET_SWZ(src[1].Swizzle, 2)), // z - t_swizzle(GET_SWZ(src[1].Swizzle, 0)), // x - t_swizzle(GET_SWZ(src[1].Swizzle, 1)), // y - t_swizzle(GET_SWZ(src[1].Swizzle, 3)), // w - t_src_class(src[1].File), - src[1].Negate) | (src[1].RelAddr << 4); - - o_inst->src2 = UNUSED_SRC_1; - o_inst++; - u_temp_i--; - - o_inst->op = MAKE_VSF_OP(hw_op, t_dst(&dst), - t_dst_mask(dst.WriteMask)); - - o_inst->src0 = MAKE_VSF_SOURCE(t_src_index(vp, &src[1]), - t_swizzle(GET_SWZ(src[1].Swizzle, 1)), // y - t_swizzle(GET_SWZ(src[1].Swizzle, 2)), // z - t_swizzle(GET_SWZ(src[1].Swizzle, 0)), // x - t_swizzle(GET_SWZ(src[1].Swizzle, 3)), // w - t_src_class(src[1].File), - (!src[1].Negate) ? VSF_FLAG_ALL : VSF_FLAG_NONE) | (src[1].RelAddr << 4); - - o_inst->src1 = MAKE_VSF_SOURCE(t_src_index(vp, &src[0]), - t_swizzle(GET_SWZ(src[0].Swizzle, 2)), // z - t_swizzle(GET_SWZ(src[0].Swizzle, 0)), // x - t_swizzle(GET_SWZ(src[0].Swizzle, 1)), // y - t_swizzle(GET_SWZ(src[0].Swizzle, 3)), // w - t_src_class(src[0].File), - src[0].Negate) | (src[0].RelAddr << 4); - - o_inst->src2 = MAKE_VSF_SOURCE(u_temp_i+1, - VSF_IN_COMPONENT_X, - VSF_IN_COMPONENT_Y, - VSF_IN_COMPONENT_Z, - VSF_IN_COMPONENT_W, - VSF_IN_CLASS_TMP, - VSF_FLAG_NONE); - goto next; - - case OPCODE_END: - assert(0); - default: - break; - } - - o_inst->op = MAKE_VSF_OP(t_opcode(vpi->Opcode), t_dst(&dst), - t_dst_mask(dst.WriteMask)); - - if(are_srcs_scalar){ - switch(operands){ - case 1: - o_inst->src0 = t_src_scalar(vp, &src[0]); - o_inst->src1 = UNUSED_SRC_0; - o_inst->src2 = UNUSED_SRC_1; - break; - - case 2: - o_inst->src0 = t_src_scalar(vp, &src[0]); - o_inst->src1 = t_src_scalar(vp, &src[1]); - o_inst->src2 = UNUSED_SRC_1; - break; - - case 3: - o_inst->src0 = t_src_scalar(vp, &src[0]); - o_inst->src1 = t_src_scalar(vp, &src[1]); - o_inst->src2 = t_src_scalar(vp, &src[2]); - break; - - default: - fprintf(stderr, "illegal number of operands %lu\n", operands); - exit(-1); - break; - } - } else { - switch(operands){ - case 1: - o_inst->src0 = t_src(vp, &src[0]); - o_inst->src1 = UNUSED_SRC_0; - o_inst->src2 = UNUSED_SRC_1; - break; - - case 2: - o_inst->src0 = t_src(vp, &src[0]); - o_inst->src1 = t_src(vp, &src[1]); - o_inst->src2 = UNUSED_SRC_1; - break; - - case 3: - o_inst->src0 = t_src(vp, &src[0]); - o_inst->src1 = t_src(vp, &src[1]); - o_inst->src2 = t_src(vp, &src[2]); - break; - - default: - fprintf(stderr, "illegal number of operands %lu\n", operands); - exit(-1); - break; - } - } - next: - - if (dofogfix) { - o_inst++; - if (vp->fogmode == GL_EXP) { - o_inst->op = MAKE_VSF_OP(R200_VPI_OUT_OP_MUL, - (fog_temp_i << R200_VPI_OUT_REG_INDEX_SHIFT) | R200_VSF_OUT_CLASS_TMP, - VSF_FLAG_X); - o_inst->src0 = EASY_VSF_SOURCE(fog_temp_i, X, X, X, X, TMP, NONE); - o_inst->src1 = EASY_VSF_SOURCE(vp->fogpidx, X, X, X, X, PARAM, NONE); - o_inst->src2 = UNUSED_SRC_1; - o_inst++; - o_inst->op = MAKE_VSF_OP(R200_VPI_OUT_OP_EXP_E, - R200_VSF_OUT_CLASS_RESULT_FOGC, - VSF_FLAG_X); - o_inst->src0 = EASY_VSF_SOURCE(fog_temp_i, X, X, X, X, TMP, ALL); - o_inst->src1 = UNUSED_SRC_0; - o_inst->src2 = UNUSED_SRC_1; - } - else if (vp->fogmode == GL_EXP2) { - o_inst->op = MAKE_VSF_OP(R200_VPI_OUT_OP_MUL, - (fog_temp_i << R200_VPI_OUT_REG_INDEX_SHIFT) | R200_VSF_OUT_CLASS_TMP, - VSF_FLAG_X); - o_inst->src0 = EASY_VSF_SOURCE(fog_temp_i, X, X, X, X, TMP, NONE); - o_inst->src1 = EASY_VSF_SOURCE(vp->fogpidx, X, X, X, X, PARAM, NONE); - o_inst->src2 = UNUSED_SRC_1; - o_inst++; - o_inst->op = MAKE_VSF_OP(R200_VPI_OUT_OP_MUL, - (fog_temp_i << R200_VPI_OUT_REG_INDEX_SHIFT) | R200_VSF_OUT_CLASS_TMP, - VSF_FLAG_X); - o_inst->src0 = EASY_VSF_SOURCE(fog_temp_i, X, X, X, X, TMP, NONE); - o_inst->src1 = EASY_VSF_SOURCE(fog_temp_i, X, X, X, X, TMP, NONE); - o_inst->src2 = UNUSED_SRC_1; - o_inst++; - o_inst->op = MAKE_VSF_OP(R200_VPI_OUT_OP_EXP_E, - R200_VSF_OUT_CLASS_RESULT_FOGC, - VSF_FLAG_X); - o_inst->src0 = EASY_VSF_SOURCE(fog_temp_i, X, X, X, X, TMP, ALL); - o_inst->src1 = UNUSED_SRC_0; - o_inst->src2 = UNUSED_SRC_1; - } - else { /* fogmode == GL_LINEAR */ - /* could do that with single op (dot) if using params like - with fixed function pipeline fog */ - o_inst->op = MAKE_VSF_OP(R200_VPI_OUT_OP_ADD, - (fog_temp_i << R200_VPI_OUT_REG_INDEX_SHIFT) | R200_VSF_OUT_CLASS_TMP, - VSF_FLAG_X); - o_inst->src0 = EASY_VSF_SOURCE(fog_temp_i, X, X, X, X, TMP, ALL); - o_inst->src1 = EASY_VSF_SOURCE(vp->fogpidx, Z, Z, Z, Z, PARAM, NONE); - o_inst->src2 = UNUSED_SRC_1; - o_inst++; - o_inst->op = MAKE_VSF_OP(R200_VPI_OUT_OP_MUL, - R200_VSF_OUT_CLASS_RESULT_FOGC, - VSF_FLAG_X); - o_inst->src0 = EASY_VSF_SOURCE(fog_temp_i, X, X, X, X, TMP, NONE); - o_inst->src1 = EASY_VSF_SOURCE(vp->fogpidx, W, W, W, W, PARAM, NONE); - o_inst->src2 = UNUSED_SRC_1; - - } - dofogfix = 0; - } - - u_temp_used = (R200_VSF_MAX_TEMPS - 1) - u_temp_i; - if (mesa_vp->arb.NumNativeTemporaries < - (mesa_vp->arb.NumTemporaries + u_temp_used)) { - mesa_vp->arb.NumNativeTemporaries = - mesa_vp->arb.NumTemporaries + u_temp_used; - } - if ((mesa_vp->arb.NumTemporaries + u_temp_used) > R200_VSF_MAX_TEMPS) { - if (R200_DEBUG & RADEON_FALLBACKS) { - fprintf(stderr, "Ran out of temps, num temps %d, us %d\n", mesa_vp->arb.NumTemporaries, u_temp_used); - } - return GL_FALSE; - } - u_temp_i = R200_VSF_MAX_TEMPS - 1; - if(o_inst - vp->instr >= R200_VSF_MAX_INST) { - mesa_vp->arb.NumNativeInstructions = 129; - if (R200_DEBUG & RADEON_FALLBACKS) { - fprintf(stderr, "more than 128 native instructions\n"); - } - return GL_FALSE; - } - if ((o_inst->op & R200_VSF_OUT_CLASS_MASK) == R200_VSF_OUT_CLASS_RESULT_POS) { - vp->pos_end = (o_inst - vp->instr); - } - } - - vp->native = GL_TRUE; - mesa_vp->arb.NumNativeInstructions = (o_inst - vp->instr); -#if 0 - fprintf(stderr, "hw program:\n"); - for(i=0; i < vp->program.length; i++) - fprintf(stderr, "%08x\n", vp->instr[i]); -#endif - return GL_TRUE; -} - -void r200SetupVertexProg( struct gl_context *ctx ) { - r200ContextPtr rmesa = R200_CONTEXT(ctx); - struct r200_vertex_program *vp = (struct r200_vertex_program *)ctx->VertexProgram.Current; - GLboolean fallback; - GLint i; - - if (!vp->translated || (ctx->Fog.Enabled && ctx->Fog.Mode != vp->fogmode)) { - rmesa->curr_vp_hw = NULL; - r200_translate_vertex_program(ctx, vp); - } - /* could optimize setting up vertex progs away for non-tcl hw */ - fallback = !(vp->native && r200VertexProgUpdateParams(ctx, vp)); - TCL_FALLBACK(ctx, R200_TCL_FALLBACK_VERTEX_PROGRAM, fallback); - if (rmesa->radeon.TclFallback) return; - - R200_STATECHANGE( rmesa, vap ); - /* FIXME: fglrx sets R200_VAP_SINGLE_BUF_STATE_ENABLE too. Do we need it? - maybe only when using more than 64 inst / 96 param? */ - rmesa->hw.vap.cmd[VAP_SE_VAP_CNTL] |= R200_VAP_PROG_VTX_SHADER_ENABLE /*| R200_VAP_SINGLE_BUF_STATE_ENABLE*/; - - R200_STATECHANGE( rmesa, pvs ); - - rmesa->hw.pvs.cmd[PVS_CNTL_1] = (0 << R200_PVS_CNTL_1_PROGRAM_START_SHIFT) | - ((vp->mesa_program.arb.NumNativeInstructions - 1) << R200_PVS_CNTL_1_PROGRAM_END_SHIFT) | - (vp->pos_end << R200_PVS_CNTL_1_POS_END_SHIFT); - rmesa->hw.pvs.cmd[PVS_CNTL_2] = (0 << R200_PVS_CNTL_2_PARAM_OFFSET_SHIFT) | - (vp->mesa_program.arb.NumNativeParameters << R200_PVS_CNTL_2_PARAM_COUNT_SHIFT); - - /* maybe user clip planes just work with vertex progs... untested */ - if (ctx->Transform.ClipPlanesEnabled) { - R200_STATECHANGE( rmesa, tcl ); - if (vp->mesa_program.arb.IsPositionInvariant) { - rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= (ctx->Transform.ClipPlanesEnabled << 2); - } - else { - rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~(0xfc); - } - } - - if (vp != rmesa->curr_vp_hw) { - GLuint count = vp->mesa_program.arb.NumNativeInstructions; - drm_radeon_cmd_header_t tmp; - - R200_STATECHANGE( rmesa, vpi[0] ); - R200_STATECHANGE( rmesa, vpi[1] ); - - /* FIXME: what about using a memcopy... */ - for (i = 0; (i < 64) && i < count; i++) { - rmesa->hw.vpi[0].cmd[VPI_OPDST_0 + 4 * i] = vp->instr[i].op; - rmesa->hw.vpi[0].cmd[VPI_SRC0_0 + 4 * i] = vp->instr[i].src0; - rmesa->hw.vpi[0].cmd[VPI_SRC1_0 + 4 * i] = vp->instr[i].src1; - rmesa->hw.vpi[0].cmd[VPI_SRC2_0 + 4 * i] = vp->instr[i].src2; - } - /* hack up the cmd_size so not the whole state atom is emitted always. - This may require some more thought, we may emit half progs on lost state, but - hopefully it won't matter? - WARNING: must not use R200_DB_STATECHANGE, this will produce bogus (and rejected) - packet emits (due to the mismatched cmd_size and count in cmd/last_cmd) */ - rmesa->hw.vpi[0].cmd_size = 1 + 4 * ((count > 64) ? 64 : count); - tmp.i = rmesa->hw.vpi[0].cmd[VPI_CMD_0]; - tmp.veclinear.count = (count > 64) ? 64 : count; - rmesa->hw.vpi[0].cmd[VPI_CMD_0] = tmp.i; - if (count > 64) { - for (i = 0; i < (count - 64); i++) { - rmesa->hw.vpi[1].cmd[VPI_OPDST_0 + 4 * i] = vp->instr[i + 64].op; - rmesa->hw.vpi[1].cmd[VPI_SRC0_0 + 4 * i] = vp->instr[i + 64].src0; - rmesa->hw.vpi[1].cmd[VPI_SRC1_0 + 4 * i] = vp->instr[i + 64].src1; - rmesa->hw.vpi[1].cmd[VPI_SRC2_0 + 4 * i] = vp->instr[i + 64].src2; - } - rmesa->hw.vpi[1].cmd_size = 1 + 4 * (count - 64); - tmp.i = rmesa->hw.vpi[1].cmd[VPI_CMD_0]; - tmp.veclinear.count = count - 64; - rmesa->hw.vpi[1].cmd[VPI_CMD_0] = tmp.i; - } - rmesa->curr_vp_hw = vp; - } -} - - -static struct gl_program * -r200NewProgram(struct gl_context *ctx, gl_shader_stage stage, GLuint id, - bool is_arb_asm) -{ - switch(stage){ - case MESA_SHADER_VERTEX: { - struct r200_vertex_program *vp = rzalloc(NULL, - struct r200_vertex_program); - return _mesa_init_gl_program(&vp->mesa_program, stage, id, is_arb_asm); - } - case MESA_SHADER_FRAGMENT: { - struct gl_program *prog = rzalloc(NULL, struct gl_program); - return _mesa_init_gl_program(prog, stage, id, is_arb_asm); - } - default: - _mesa_problem(ctx, "Bad target in r200NewProgram"); - return NULL; - } -} - - -static void -r200DeleteProgram(struct gl_context *ctx, struct gl_program *prog) -{ - _mesa_delete_program(ctx, prog); -} - -static GLboolean -r200ProgramStringNotify(struct gl_context *ctx, GLenum target, struct gl_program *prog) -{ - struct r200_vertex_program *vp = (void *)prog; - r200ContextPtr rmesa = R200_CONTEXT(ctx); - - switch(target) { - case GL_VERTEX_PROGRAM_ARB: - vp->translated = GL_FALSE; - vp->fogpidx = 0; -/* memset(&vp->translated, 0, sizeof(struct r200_vertex_program) - sizeof(struct gl_program));*/ - r200_translate_vertex_program(ctx, vp); - rmesa->curr_vp_hw = NULL; - break; - case GL_FRAGMENT_SHADER_ATI: - rmesa->afs_loaded = NULL; - break; - } - /* need this for tcl fallbacks */ - (void) _tnl_program_string(ctx, target, prog); - - /* XXX check if program is legal, within limits */ - return GL_TRUE; -} - -static GLboolean -r200IsProgramNative(struct gl_context *ctx, GLenum target, struct gl_program *prog) -{ - struct r200_vertex_program *vp = (void *)prog; - - switch(target){ - case GL_VERTEX_PROGRAM_ARB: - if (!vp->translated) { - r200_translate_vertex_program(ctx, vp); - } - /* does not take parameters etc. into account */ - return vp->native; - default: - _mesa_problem(ctx, "Bad target in r200NewProgram"); - } - return 0; -} - -void r200InitShaderFuncs(struct dd_function_table *functions) -{ - functions->NewProgram = r200NewProgram; - functions->DeleteProgram = r200DeleteProgram; - functions->ProgramStringNotify = r200ProgramStringNotify; - functions->IsProgramNative = r200IsProgramNative; -} diff --git a/src/mesa/drivers/dri/r200/r200_vertprog.h b/src/mesa/drivers/dri/r200/r200_vertprog.h deleted file mode 100644 index 4757f4b32bc..00000000000 --- a/src/mesa/drivers/dri/r200/r200_vertprog.h +++ /dev/null @@ -1,163 +0,0 @@ -#ifndef __VERTEX_SHADER_H__ -#define __VERTEX_SHADER_H__ - -#include "r200_reg.h" - -typedef struct { - uint32_t op; - uint32_t src0; - uint32_t src1; - uint32_t src2; -} VERTEX_SHADER_INSTRUCTION; - -extern void r200InitShaderFuncs(struct dd_function_table *functions); -extern void r200SetupVertexProg( struct gl_context *ctx ); - -#define VSF_FLAG_X 1 -#define VSF_FLAG_Y 2 -#define VSF_FLAG_Z 4 -#define VSF_FLAG_W 8 -#define VSF_FLAG_XYZ (VSF_FLAG_X | VSF_FLAG_Y | VSF_FLAG_Z) -#define VSF_FLAG_ALL 0xf -#define VSF_FLAG_NONE 0 - -#define R200_VSF_MAX_INST 128 -#define R200_VSF_MAX_PARAM 192 -#define R200_VSF_MAX_TEMPS 12 - -#define R200_VPI_OUT_REG_INDEX_SHIFT 13 -#define R200_VPI_OUT_REG_INDEX_MASK (31 << 13) /* GUESS based on fglrx native limits */ - -#define R200_VPI_OUT_WRITE_X (1 << 20) -#define R200_VPI_OUT_WRITE_Y (1 << 21) -#define R200_VPI_OUT_WRITE_Z (1 << 22) -#define R200_VPI_OUT_WRITE_W (1 << 23) - -#define R200_VPI_IN_REG_CLASS_TEMPORARY (0 << 0) -#define R200_VPI_IN_REG_CLASS_ATTRIBUTE (1 << 0) -#define R200_VPI_IN_REG_CLASS_PARAMETER (2 << 0) -#define R200_VPI_IN_REG_CLASS_NONE (9 << 0) -#define R200_VPI_IN_REG_CLASS_MASK (31 << 0) /* GUESS */ - -#define R200_VPI_IN_REG_INDEX_SHIFT 5 -#define R200_VPI_IN_REG_INDEX_MASK (255 << 5) /* GUESS based on fglrx native limits */ - -/* The R200 can select components from the input register arbitrarily. -// Use the following constants, shifted by the component shift you -// want to select */ -#define R200_VPI_IN_SELECT_X 0 -#define R200_VPI_IN_SELECT_Y 1 -#define R200_VPI_IN_SELECT_Z 2 -#define R200_VPI_IN_SELECT_W 3 -#define R200_VPI_IN_SELECT_ZERO 4 -#define R200_VPI_IN_SELECT_ONE 5 -#define R200_VPI_IN_SELECT_MASK 7 - -#define R200_VPI_IN_X_SHIFT 13 -#define R200_VPI_IN_Y_SHIFT 16 -#define R200_VPI_IN_Z_SHIFT 19 -#define R200_VPI_IN_W_SHIFT 22 - -#define R200_VPI_IN_NEG_X (1 << 25) -#define R200_VPI_IN_NEG_Y (1 << 26) -#define R200_VPI_IN_NEG_Z (1 << 27) -#define R200_VPI_IN_NEG_W (1 << 28) - -#define R200_VSF_OUT_CLASS_TMP (0 << 8) -#define R200_VSF_OUT_CLASS_ADDR (3 << 8) -#define R200_VSF_OUT_CLASS_RESULT_POS (4 << 8) -#define R200_VSF_OUT_CLASS_RESULT_COLOR (5 << 8) -#define R200_VSF_OUT_CLASS_RESULT_TEXC (6 << 8) -#define R200_VSF_OUT_CLASS_RESULT_FOGC (7 << 8) -#define R200_VSF_OUT_CLASS_RESULT_POINTSIZE (8 << 8) -#define R200_VSF_OUT_CLASS_MASK (31 << 8) - -/* opcodes - they all are the same as on r300 it seems, however - LIT and POW require different setup */ -#define R200_VPI_OUT_OP_DOT (1 << 0) -#define R200_VPI_OUT_OP_MUL (2 << 0) -#define R200_VPI_OUT_OP_ADD (3 << 0) -#define R200_VPI_OUT_OP_MAD (4 << 0) -#define R200_VPI_OUT_OP_DST (5 << 0) -#define R200_VPI_OUT_OP_FRC (6 << 0) -#define R200_VPI_OUT_OP_MAX (7 << 0) -#define R200_VPI_OUT_OP_MIN (8 << 0) -#define R200_VPI_OUT_OP_SGE (9 << 0) -#define R200_VPI_OUT_OP_SLT (10 << 0) - -#define R200_VPI_OUT_OP_ARL (13 << 0) - -#define R200_VPI_OUT_OP_EXP (65 << 0) -#define R200_VPI_OUT_OP_LOG (66 << 0) -/* base e exp. Useful for fog. */ -#define R200_VPI_OUT_OP_EXP_E (67 << 0) - -#define R200_VPI_OUT_OP_LIT (68 << 0) -#define R200_VPI_OUT_OP_POW (69 << 0) -#define R200_VPI_OUT_OP_RCP (70 << 0) -#define R200_VPI_OUT_OP_RSQ (72 << 0) - -#define R200_VPI_OUT_OP_EX2 (75 << 0) -#define R200_VPI_OUT_OP_LG2 (76 << 0) - -#define R200_VPI_OUT_OP_MAD_2 (128 << 0) - -/* first CARD32 of an instruction */ - -/* possible operations: - DOT, MUL, ADD, MAD, FRC, MAX, MIN, SGE, SLT, EXP, LOG, LIT, POW, RCP, RSQ, EX2, - LG2, MAD_2, ARL */ - -#define MAKE_VSF_OP(op, out_reg, out_reg_fields) \ - ((op) | (out_reg) | ((out_reg_fields) << 20) ) - -#define VSF_IN_CLASS_TMP 0 -#define VSF_IN_CLASS_ATTR 1 -#define VSF_IN_CLASS_PARAM 2 -#define VSF_IN_CLASS_NONE 9 - -#define VSF_IN_COMPONENT_X 0 -#define VSF_IN_COMPONENT_Y 1 -#define VSF_IN_COMPONENT_Z 2 -#define VSF_IN_COMPONENT_W 3 -#define VSF_IN_COMPONENT_ZERO 4 -#define VSF_IN_COMPONENT_ONE 5 - -#define MAKE_VSF_SOURCE(in_reg_index, comp_x, comp_y, comp_z, comp_w, class, negate) \ - ( ((in_reg_index)<<R200_VPI_IN_REG_INDEX_SHIFT) \ - | ((comp_x)<<R200_VPI_IN_X_SHIFT) \ - | ((comp_y)<<R200_VPI_IN_Y_SHIFT) \ - | ((comp_z)<<R200_VPI_IN_Z_SHIFT) \ - | ((comp_w)<<R200_VPI_IN_W_SHIFT) \ - | ((negate)<<25) | ((class))) - -#define EASY_VSF_SOURCE(in_reg_index, comp_x, comp_y, comp_z, comp_w, class, negate) \ - MAKE_VSF_SOURCE(in_reg_index, \ - VSF_IN_COMPONENT_##comp_x, \ - VSF_IN_COMPONENT_##comp_y, \ - VSF_IN_COMPONENT_##comp_z, \ - VSF_IN_COMPONENT_##comp_w, \ - VSF_IN_CLASS_##class, VSF_FLAG_##negate) - -/* special sources: */ - -/* (1.0,1.0,1.0,1.0) vector (ATTR, plain ) */ -#define VSF_ATTR_UNITY(reg) EASY_VSF_SOURCE(reg, ONE, ONE, ONE, ONE, ATTR, NONE) -#define VSF_UNITY(reg) EASY_VSF_SOURCE(reg, ONE, ONE, ONE, ONE, NONE, NONE) - -/* contents of unmodified register */ -#define VSF_REG(reg) EASY_VSF_SOURCE(reg, X, Y, Z, W, ATTR, NONE) - -/* contents of unmodified parameter */ -#define VSF_PARAM(reg) EASY_VSF_SOURCE(reg, X, Y, Z, W, PARAM, NONE) - -/* contents of unmodified temporary register */ -#define VSF_TMP(reg) EASY_VSF_SOURCE(reg, X, Y, Z, W, TMP, NONE) - -/* components of ATTR register */ -#define VSF_ATTR_X(reg) EASY_VSF_SOURCE(reg, X, X, X, X, ATTR, NONE) -#define VSF_ATTR_Y(reg) EASY_VSF_SOURCE(reg, Y, Y, Y, Y, ATTR, NONE) -#define VSF_ATTR_Z(reg) EASY_VSF_SOURCE(reg, Z, Z, Z, Z, ATTR, NONE) -#define VSF_ATTR_W(reg) EASY_VSF_SOURCE(reg, W, W, W, W, ATTR, NONE) - -#endif diff --git a/src/mesa/drivers/dri/r200/radeon_buffer_objects.c b/src/mesa/drivers/dri/r200/radeon_buffer_objects.c deleted file mode 120000 index f6a5f664701..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_buffer_objects.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_buffer_objects.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_buffer_objects.h b/src/mesa/drivers/dri/r200/radeon_buffer_objects.h deleted file mode 120000 index 2f134fd17b8..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_buffer_objects.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_buffer_objects.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_chipset.h b/src/mesa/drivers/dri/r200/radeon_chipset.h deleted file mode 120000 index eba99001ff8..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_chipset.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_chipset.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_cmdbuf.h b/src/mesa/drivers/dri/r200/radeon_cmdbuf.h deleted file mode 120000 index a799e1dc6df..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_cmdbuf.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_cmdbuf.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_common.c b/src/mesa/drivers/dri/r200/radeon_common.c deleted file mode 120000 index 67b19ba940d..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_common.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_common.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_common.h b/src/mesa/drivers/dri/r200/radeon_common.h deleted file mode 120000 index 5bcb696a9f7..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_common.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_common.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_common_context.c b/src/mesa/drivers/dri/r200/radeon_common_context.c deleted file mode 120000 index 86800f3819c..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_common_context.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_common_context.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_common_context.h b/src/mesa/drivers/dri/r200/radeon_common_context.h deleted file mode 120000 index 4d663125500..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_common_context.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_common_context.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_debug.c b/src/mesa/drivers/dri/r200/radeon_debug.c deleted file mode 120000 index c98c2e074c5..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_debug.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_debug.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_debug.h b/src/mesa/drivers/dri/r200/radeon_debug.h deleted file mode 120000 index bd8aa28e89e..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_debug.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_debug.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_dma.c b/src/mesa/drivers/dri/r200/radeon_dma.c deleted file mode 120000 index 43be0006255..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_dma.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_dma.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_dma.h b/src/mesa/drivers/dri/r200/radeon_dma.h deleted file mode 120000 index 82e50634e3c..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_dma.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_dma.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_fbo.c b/src/mesa/drivers/dri/r200/radeon_fbo.c deleted file mode 120000 index 0d738d8d780..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_fbo.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_fbo.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_fog.c b/src/mesa/drivers/dri/r200/radeon_fog.c deleted file mode 120000 index 231aa4ffcb3..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_fog.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_fog.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_fog.h b/src/mesa/drivers/dri/r200/radeon_fog.h deleted file mode 120000 index 76c40f621f3..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_fog.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_fog.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_mipmap_tree.c b/src/mesa/drivers/dri/r200/radeon_mipmap_tree.c deleted file mode 120000 index 31c0cfbe942..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_mipmap_tree.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_mipmap_tree.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_mipmap_tree.h b/src/mesa/drivers/dri/r200/radeon_mipmap_tree.h deleted file mode 120000 index 254d50cf8c5..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_mipmap_tree.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_mipmap_tree.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_pixel_read.c b/src/mesa/drivers/dri/r200/radeon_pixel_read.c deleted file mode 120000 index 3b03803126f..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_pixel_read.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_pixel_read.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_queryobj.c b/src/mesa/drivers/dri/r200/radeon_queryobj.c deleted file mode 120000 index 1d6ebc1c48b..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_queryobj.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_queryobj.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_queryobj.h b/src/mesa/drivers/dri/r200/radeon_queryobj.h deleted file mode 120000 index 8f6f842b0a6..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_queryobj.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_queryobj.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_screen.c b/src/mesa/drivers/dri/r200/radeon_screen.c deleted file mode 120000 index 86161118dd3..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_screen.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_screen.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_screen.h b/src/mesa/drivers/dri/r200/radeon_screen.h deleted file mode 120000 index 23bb6bd4598..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_screen.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_screen.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_span.c b/src/mesa/drivers/dri/r200/radeon_span.c deleted file mode 120000 index 232868c4c9e..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_span.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_span.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_span.h b/src/mesa/drivers/dri/r200/radeon_span.h deleted file mode 120000 index f9d634508c2..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_span.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_span.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_tex_copy.c b/src/mesa/drivers/dri/r200/radeon_tex_copy.c deleted file mode 120000 index dfa5ba34e65..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_tex_copy.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_tex_copy.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_texture.c b/src/mesa/drivers/dri/r200/radeon_texture.c deleted file mode 120000 index a822710915f..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_texture.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_texture.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_texture.h b/src/mesa/drivers/dri/r200/radeon_texture.h deleted file mode 120000 index 17fac3d5ea5..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_texture.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_texture.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_tile.c b/src/mesa/drivers/dri/r200/radeon_tile.c deleted file mode 120000 index d4bfe27da64..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_tile.c +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_tile.c
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/radeon_tile.h b/src/mesa/drivers/dri/r200/radeon_tile.h deleted file mode 120000 index 31074c581ea..00000000000 --- a/src/mesa/drivers/dri/r200/radeon_tile.h +++ /dev/null @@ -1 +0,0 @@ -../radeon/radeon_tile.h
\ No newline at end of file diff --git a/src/mesa/drivers/dri/r200/server/radeon_reg.h b/src/mesa/drivers/dri/r200/server/radeon_reg.h deleted file mode 120000 index e2349dcb685..00000000000 --- a/src/mesa/drivers/dri/r200/server/radeon_reg.h +++ /dev/null @@ -1 +0,0 @@ -../../radeon/server/radeon_reg.h
\ No newline at end of file |