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authorPaulo Zanoni <paulo.r.zanoni@intel.com>2012-08-10 12:06:37 -0300
committerKenneth Graunke <kenneth@whitecape.org>2013-05-09 15:11:53 -0700
commitf1d2b373177dbbb582cefb0d6c88994073fab652 (patch)
treea42aa7b9370704654fcc4271b7a5198f602f8f56 /src/mesa/drivers/dri
parentd0b82b1add5d1d1419d4390a3f7c584b6ee7d92c (diff)
i965: make GT3 machines work as GT3 instead of GT2
We were not allowed to say the "GT3" name, but we really needed to have the PCI IDs because too many people had such machines, so we had to make the GT3 machines work as GT2. Let's just say that GT2_PLUS was a short for GT2_PLUS_1 :) NOTE: This is a candidate for stable branches. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri')
-rw-r--r--src/mesa/drivers/dri/intel/intel_chipset.h52
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.c26
2 files changed, 41 insertions, 37 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h
index 04753ddb631..df025ac2695 100644
--- a/src/mesa/drivers/dri/intel/intel_chipset.h
+++ b/src/mesa/drivers/dri/intel/intel_chipset.h
@@ -95,40 +95,40 @@
#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
#define PCI_CHIP_HASWELL_GT2 0x0412
-#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422
+#define PCI_CHIP_HASWELL_GT3 0x0422
#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
#define PCI_CHIP_HASWELL_M_GT2 0x0416
-#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
+#define PCI_CHIP_HASWELL_M_GT3 0x0426
#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
#define PCI_CHIP_HASWELL_S_GT2 0x041A
-#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A
+#define PCI_CHIP_HASWELL_S_GT3 0x042A
#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
-#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22
+#define PCI_CHIP_HASWELL_SDV_GT3 0x0C22
#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
-#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
+#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26
#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
-#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
+#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A
#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
-#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22
+#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
-#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
+#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26
#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
-#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
+#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
-#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D22
+#define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
-#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26
+#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26
#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
-#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A
+#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
#define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \
devid == PCI_CHIP_I915_GM || \
@@ -229,21 +229,23 @@
devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \
devid == PCI_CHIP_HASWELL_CRW_GT2 || \
devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \
- devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \
- devid == PCI_CHIP_HASWELL_M_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_S_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \
- devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
+ devid == PCI_CHIP_HASWELL_CRW_S_GT2)
+
+#define IS_HSW_GT3(devid) (devid == PCI_CHIP_HASWELL_M_GT3 || \
+ devid == PCI_CHIP_HASWELL_S_GT3 || \
+ devid == PCI_CHIP_HASWELL_SDV_GT3 || \
+ devid == PCI_CHIP_HASWELL_SDV_M_GT3 || \
+ devid == PCI_CHIP_HASWELL_SDV_S_GT3 || \
+ devid == PCI_CHIP_HASWELL_ULT_GT3 || \
+ devid == PCI_CHIP_HASWELL_ULT_M_GT3 || \
+ devid == PCI_CHIP_HASWELL_ULT_S_GT3 || \
+ devid == PCI_CHIP_HASWELL_CRW_GT3 || \
+ devid == PCI_CHIP_HASWELL_CRW_M_GT3 || \
+ devid == PCI_CHIP_HASWELL_CRW_S_GT3)
#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
- IS_HSW_GT2(devid))
+ IS_HSW_GT2(devid) || \
+ IS_HSW_GT3(devid))
#define IS_965(devid) (IS_GEN4(devid) || \
IS_G4X(devid) || \
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 0a1dd7501de..88cc2478f52 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -195,44 +195,44 @@ intelGetString(struct gl_context * ctx, GLenum name)
break;
case PCI_CHIP_HASWELL_GT1:
case PCI_CHIP_HASWELL_GT2:
- case PCI_CHIP_HASWELL_GT2_PLUS:
+ case PCI_CHIP_HASWELL_GT3:
case PCI_CHIP_HASWELL_SDV_GT1:
case PCI_CHIP_HASWELL_SDV_GT2:
- case PCI_CHIP_HASWELL_SDV_GT2_PLUS:
+ case PCI_CHIP_HASWELL_SDV_GT3:
case PCI_CHIP_HASWELL_ULT_GT1:
case PCI_CHIP_HASWELL_ULT_GT2:
- case PCI_CHIP_HASWELL_ULT_GT2_PLUS:
+ case PCI_CHIP_HASWELL_ULT_GT3:
case PCI_CHIP_HASWELL_CRW_GT1:
case PCI_CHIP_HASWELL_CRW_GT2:
- case PCI_CHIP_HASWELL_CRW_GT2_PLUS:
+ case PCI_CHIP_HASWELL_CRW_GT3:
chipset = "Intel(R) Haswell Desktop";
break;
case PCI_CHIP_HASWELL_M_GT1:
case PCI_CHIP_HASWELL_M_GT2:
- case PCI_CHIP_HASWELL_M_GT2_PLUS:
+ case PCI_CHIP_HASWELL_M_GT3:
case PCI_CHIP_HASWELL_SDV_M_GT1:
case PCI_CHIP_HASWELL_SDV_M_GT2:
- case PCI_CHIP_HASWELL_SDV_M_GT2_PLUS:
+ case PCI_CHIP_HASWELL_SDV_M_GT3:
case PCI_CHIP_HASWELL_ULT_M_GT1:
case PCI_CHIP_HASWELL_ULT_M_GT2:
- case PCI_CHIP_HASWELL_ULT_M_GT2_PLUS:
+ case PCI_CHIP_HASWELL_ULT_M_GT3:
case PCI_CHIP_HASWELL_CRW_M_GT1:
case PCI_CHIP_HASWELL_CRW_M_GT2:
- case PCI_CHIP_HASWELL_CRW_M_GT2_PLUS:
+ case PCI_CHIP_HASWELL_CRW_M_GT3:
chipset = "Intel(R) Haswell Mobile";
break;
case PCI_CHIP_HASWELL_S_GT1:
case PCI_CHIP_HASWELL_S_GT2:
- case PCI_CHIP_HASWELL_S_GT2_PLUS:
+ case PCI_CHIP_HASWELL_S_GT3:
case PCI_CHIP_HASWELL_SDV_S_GT1:
case PCI_CHIP_HASWELL_SDV_S_GT2:
- case PCI_CHIP_HASWELL_SDV_S_GT2_PLUS:
+ case PCI_CHIP_HASWELL_SDV_S_GT3:
case PCI_CHIP_HASWELL_ULT_S_GT1:
case PCI_CHIP_HASWELL_ULT_S_GT2:
- case PCI_CHIP_HASWELL_ULT_S_GT2_PLUS:
+ case PCI_CHIP_HASWELL_ULT_S_GT3:
case PCI_CHIP_HASWELL_CRW_S_GT1:
case PCI_CHIP_HASWELL_CRW_S_GT2:
- case PCI_CHIP_HASWELL_CRW_S_GT2_PLUS:
+ case PCI_CHIP_HASWELL_CRW_S_GT3:
chipset = "Intel(R) Haswell Server";
break;
default:
@@ -684,6 +684,8 @@ intelInitContext(struct intel_context *intel,
intel->gt = 1;
else if (IS_SNB_GT2(devID) || IS_IVB_GT2(devID) || IS_HSW_GT2(devID))
intel->gt = 2;
+ else if (IS_HSW_GT3(devID))
+ intel->gt = 3;
else
intel->gt = 0;