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authorMarcin Ślusarz <marcin.slusarz@intel.com>2021-10-13 11:21:41 +0200
committerMarge Bot <eric+marge@anholt.net>2021-10-15 19:55:14 +0000
commitd05f7b4a2ca68cc11825239273f6d8558b5ffde8 (patch)
treec7c314bd16f2a10ffe37955827d7312dd89d213f /src/mesa/drivers/dri/i965
parent182237e1e89122b6a09f2a5607e9fc2b138fb11b (diff)
intel: fix INTEL_DEBUG environment variable on 32-bit systems
INTEL_DEBUG is defined (since 4015e1876a77162e3444eeaa29a0dfbc47efe90e) as: #define INTEL_DEBUG __builtin_expect(intel_debug, 0) which unfortunately chops off upper 32 bits from intel_debug on platforms where sizeof(long) != sizeof(uint64_t) because __builtin_expect is defined only for the long type. Fix this by changing the definition of INTEL_DEBUG to be function-like macro with "flags" argument. New definition returns 0 or 1 when any of the flags match. Most of the changes in this commit were generated using: for c in `git grep INTEL_DEBUG | grep "&" | grep -v i915 | awk -F: '{print $1}' | sort | uniq`; do perl -pi -e "s/INTEL_DEBUG & ([A-Z0-9a-z_]+)/INTEL_DBG(\1)/" $c perl -pi -e "s/INTEL_DEBUG & (\([A-Z0-9_ |]+\))/INTEL_DBG\1/" $c done but it didn't handle all cases and required minor cleanups (like removal of round brackets which were not needed anymore). Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13334>
Diffstat (limited to 'src/mesa/drivers/dri/i965')
-rw-r--r--src/mesa/drivers/dri/i965/brw_batch.c16
-rw-r--r--src/mesa/drivers/dri/i965/brw_binding_tables.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_blorp.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_clear.c4
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.c14
-rw-r--r--src/mesa/drivers/dri/i965/brw_context.h2
-rw-r--r--src/mesa/drivers/dri/i965/brw_cs.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_disk_cache.c4
-rw-r--r--src/mesa/drivers/dri/i965/brw_draw_upload.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_gs.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_link.cpp2
-rw-r--r--src/mesa/drivers/dri/i965/brw_mipmap_tree.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_performance_query.c4
-rw-r--r--src/mesa/drivers/dri/i965/brw_pixel_bitmap.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_program.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_screen.c8
-rw-r--r--src/mesa/drivers/dri/i965/brw_state_upload.c6
-rw-r--r--src/mesa/drivers/dri/i965/brw_tcs.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_tes.c2
-rw-r--r--src/mesa/drivers/dri/i965/brw_urb.c4
-rw-r--r--src/mesa/drivers/dri/i965/brw_vs.c4
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm.c6
-rw-r--r--src/mesa/drivers/dri/i965/genX_state_upload.c2
-rw-r--r--src/mesa/drivers/dri/i965/gfx7_l3_state.c2
24 files changed, 49 insertions, 49 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_batch.c b/src/mesa/drivers/dri/i965/brw_batch.c
index b51704f54e8..1d7da7abed3 100644
--- a/src/mesa/drivers/dri/i965/brw_batch.c
+++ b/src/mesa/drivers/dri/i965/brw_batch.c
@@ -138,7 +138,7 @@ brw_batch_init(struct brw_context *brw)
struct brw_batch *batch = &brw->batch;
const struct intel_device_info *devinfo = &screen->devinfo;
- if (INTEL_DEBUG & DEBUG_BATCH) {
+ if (INTEL_DEBUG(DEBUG_BATCH)) {
/* The shadow doesn't get relocs written so state decode fails. */
batch->use_shadow_copy = false;
} else
@@ -157,13 +157,13 @@ brw_batch_init(struct brw_context *brw)
malloc(batch->exec_array_size * sizeof(batch->validation_list[0]));
batch->contains_fence_signal = false;
- if (INTEL_DEBUG & DEBUG_BATCH) {
+ if (INTEL_DEBUG(DEBUG_BATCH)) {
batch->state_batch_sizes =
_mesa_hash_table_u64_create(NULL);
const unsigned decode_flags =
INTEL_BATCH_DECODE_FULL |
- ((INTEL_DEBUG & DEBUG_COLOR) ? INTEL_BATCH_DECODE_IN_COLOR : 0) |
+ (INTEL_DEBUG(DEBUG_COLOR) ? INTEL_BATCH_DECODE_IN_COLOR : 0) |
INTEL_BATCH_DECODE_OFFSETS |
INTEL_BATCH_DECODE_FLOATS;
@@ -600,7 +600,7 @@ brw_new_batch(struct brw_context *brw)
* while, because many programs won't cleanly destroy our context, so the
* end-of-run printout may not happen.
*/
- if (INTEL_DEBUG & DEBUG_SHADER_TIME)
+ if (INTEL_DEBUG(DEBUG_SHADER_TIME))
brw_collect_and_report_shader_time(brw);
brw_batch_maybe_noop(brw);
@@ -850,7 +850,7 @@ submit_batch(struct brw_context *brw, int in_fence_fd, int *out_fence_fd)
throttle(brw);
}
- if (INTEL_DEBUG & DEBUG_BATCH) {
+ if (INTEL_DEBUG(DEBUG_BATCH)) {
intel_print_batch(&batch->decoder, batch->batch.map,
4 * USED_BATCH(*batch),
batch->batch.bo->gtt_offset, false);
@@ -899,7 +899,7 @@ _brw_batch_flush_fence(struct brw_context *brw,
brw_bo_reference(brw->throttle_batch[0]);
}
- if (INTEL_DEBUG & (DEBUG_BATCH | DEBUG_SUBMIT)) {
+ if (INTEL_DEBUG(DEBUG_BATCH | DEBUG_SUBMIT)) {
int bytes_for_commands = 4 * USED_BATCH(brw->batch);
int bytes_for_state = brw->batch.state_used;
fprintf(stderr, "%19s:%-3d: Batchbuffer flush with %5db (%0.1f%%) (pkt),"
@@ -917,7 +917,7 @@ _brw_batch_flush_fence(struct brw_context *brw,
ret = submit_batch(brw, in_fence_fd, out_fence_fd);
- if (INTEL_DEBUG & DEBUG_SYNC) {
+ if (INTEL_DEBUG(DEBUG_SYNC)) {
fprintf(stderr, "waiting for idle\n");
brw_bo_wait_rendering(brw->batch.batch.bo);
}
@@ -1087,7 +1087,7 @@ brw_state_batch(struct brw_context *brw,
assert(offset + size < batch->state.bo->size);
}
- if (INTEL_DEBUG & DEBUG_BATCH) {
+ if (INTEL_DEBUG(DEBUG_BATCH)) {
_mesa_hash_table_u64_insert(batch->state_batch_sizes,
offset, (void *) (uintptr_t) size);
}
diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c b/src/mesa/drivers/dri/i965/brw_binding_tables.c
index 8ed56228a31..8ecdcc54147 100644
--- a/src/mesa/drivers/dri/i965/brw_binding_tables.c
+++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c
@@ -66,7 +66,7 @@ brw_upload_binding_table(struct brw_context *brw,
stage_state->bind_bo_offset = 0;
} else {
/* Upload a new binding table. */
- if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
+ if (INTEL_DEBUG(DEBUG_SHADER_TIME)) {
brw_emit_buffer_surface_state(
brw, &stage_state->surf_offset[
prog_data->binding_table.shader_time_start],
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 64876b6a8e1..200cd1175ec 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1209,7 +1209,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
bool can_fast_clear = !partial_clear;
- if (INTEL_DEBUG & DEBUG_NO_FAST_CLEAR)
+ if (INTEL_DEBUG(DEBUG_NO_FAST_CLEAR))
can_fast_clear = false;
uint8_t color_write_disable = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index bef2d86c08f..3fcc31a31c8 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -62,7 +62,7 @@ debug_mask(const char *name, GLbitfield mask)
{
GLuint i;
- if (INTEL_DEBUG & DEBUG_BLIT) {
+ if (INTEL_DEBUG(DEBUG_BLIT)) {
DBG("%s clear:", name);
for (i = 0; i < BUFFER_COUNT; i++) {
if (mask & (1 << i))
@@ -107,7 +107,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
struct gl_renderbuffer_attachment *depth_att = &fb->Attachment[BUFFER_DEPTH];
const struct intel_device_info *devinfo = &brw->screen->devinfo;
- if (INTEL_DEBUG & DEBUG_NO_FAST_CLEAR)
+ if (INTEL_DEBUG(DEBUG_NO_FAST_CLEAR))
return false;
if (devinfo->ver < 6)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 097dd9cb1dc..24c60af711c 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -885,7 +885,7 @@ brw_process_driconf_options(struct brw_context *brw)
struct gl_context *ctx = &brw->ctx;
const driOptionCache *const options = &brw->screen->optionCache;
- if (INTEL_DEBUG & DEBUG_NO_HIZ) {
+ if (INTEL_DEBUG(DEBUG_NO_HIZ)) {
brw->has_hiz = false;
/* On gfx6, you can only do separate stencil with HIZ. */
if (devinfo->ver == 6)
@@ -1074,7 +1074,7 @@ brw_create_context(gl_api api,
_mesa_meta_init(ctx);
- if (INTEL_DEBUG & DEBUG_PERF)
+ if (INTEL_DEBUG(DEBUG_PERF))
brw->perf_debug = true;
brw_initialize_cs_context_constants(brw);
@@ -1172,7 +1172,7 @@ brw_create_context(gl_api api,
ctx->Const.RobustAccess = GL_TRUE;
}
- if (INTEL_DEBUG & DEBUG_SHADER_TIME)
+ if (INTEL_DEBUG(DEBUG_SHADER_TIME))
brw_init_shader_time(brw);
_mesa_override_extensions(ctx);
@@ -1251,7 +1251,7 @@ brw_destroy_context(__DRIcontext *driContextPriv)
_mesa_meta_free(&brw->ctx);
- if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
+ if (INTEL_DEBUG(DEBUG_SHADER_TIME)) {
/* Force a report. */
brw->shader_time.report_time = 0;
@@ -1510,7 +1510,7 @@ brw_update_dri2_buffers(struct brw_context *brw, __DRIdrawable *drawable)
* thus ignore the invalidate. */
drawable->lastStamp = drawable->dri2.stamp;
- if (INTEL_DEBUG & DEBUG_DRI)
+ if (INTEL_DEBUG(DEBUG_DRI))
fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable);
brw_query_dri2_buffers(brw, drawable, &buffers, &count);
@@ -1563,7 +1563,7 @@ brw_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
* thus ignore the invalidate. */
drawable->lastStamp = drawable->dri2.stamp;
- if (INTEL_DEBUG & DEBUG_DRI)
+ if (INTEL_DEBUG(DEBUG_DRI))
fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable);
if (dri_screen->image.loader)
@@ -1742,7 +1742,7 @@ brw_process_dri2_buffer(struct brw_context *brw,
if (old_name == buffer->name)
return;
- if (INTEL_DEBUG & DEBUG_DRI) {
+ if (INTEL_DEBUG(DEBUG_DRI)) {
fprintf(stderr,
"attaching buffer %d, at %d, cpp %d, pitch %d\n",
buffer->name, buffer->attachment,
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 17791286328..bf00fe01607 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -376,7 +376,7 @@ struct brw_cache {
#define perf_debug(...) do { \
static GLuint msg_id = 0; \
- if (INTEL_DEBUG & DEBUG_PERF) \
+ if (INTEL_DEBUG(DEBUG_PERF)) \
dbg_printf(__VA_ARGS__); \
if (brw->perf_debug) \
_mesa_gl_debugf(&brw->ctx, &msg_id, \
diff --git a/src/mesa/drivers/dri/i965/brw_cs.c b/src/mesa/drivers/dri/i965/brw_cs.c
index 0723a686e0b..786dda4b450 100644
--- a/src/mesa/drivers/dri/i965/brw_cs.c
+++ b/src/mesa/drivers/dri/i965/brw_cs.c
@@ -94,7 +94,7 @@ brw_codegen_cs_prog(struct brw_context *brw,
.log_data = brw,
};
- if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
+ if (INTEL_DEBUG(DEBUG_SHADER_TIME)) {
params.shader_time = true;
params.shader_time_index =
brw_get_shader_time_index(brw, &cp->program, ST_CS, true);
diff --git a/src/mesa/drivers/dri/i965/brw_disk_cache.c b/src/mesa/drivers/dri/i965/brw_disk_cache.c
index e94cf3220a6..b3fcb5eb3e2 100644
--- a/src/mesa/drivers/dri/i965/brw_disk_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_disk_cache.c
@@ -49,7 +49,7 @@ debug_enabled_for_stage(gl_shader_stage stage)
DEBUG_VS, DEBUG_TCS, DEBUG_TES, DEBUG_GS, DEBUG_WM, DEBUG_CS,
};
assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_debug_flags));
- return (INTEL_DEBUG & stage_debug_flags[stage]) != 0;
+ return INTEL_DEBUG(stage_debug_flags[stage]);
}
static void
@@ -391,7 +391,7 @@ void
brw_disk_cache_init(struct brw_screen *screen)
{
#ifdef ENABLE_SHADER_CACHE
- if (INTEL_DEBUG & DEBUG_DISK_CACHE_DISABLE_MASK)
+ if (INTEL_DEBUG(DEBUG_DISK_CACHE_DISABLE_MASK))
return;
/* array length: print length + null char + 1 extra to verify it is unused */
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index fb3ebc5e3b3..eb181f088a3 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -256,7 +256,7 @@ brw_get_vertex_surface_type(struct brw_context *brw,
const bool is_ivybridge_or_older =
devinfo->verx10 <= 70 && !devinfo->is_baytrail;
- if (INTEL_DEBUG & DEBUG_VERTS)
+ if (INTEL_DEBUG(DEBUG_VERTS))
fprintf(stderr, "type %s size %d normalized %d\n",
_mesa_enum_to_string(glformat->Type),
glformat->Size, glformat->Normalized);
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index ea6aa3ee94c..b3acdec64a5 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -120,7 +120,7 @@ brw_codegen_gs_prog(struct brw_context *brw,
&prog_data);
int st_index = -1;
- if (INTEL_DEBUG & DEBUG_SHADER_TIME)
+ if (INTEL_DEBUG(DEBUG_SHADER_TIME))
st_index = brw_get_shader_time_index(brw, &gp->program, ST_GS, true);
if (unlikely(brw->perf_debug)) {
diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp
index 396ee4d3c0d..974543ec806 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -248,7 +248,7 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
prog->ShadowSamplers = shader->shadow_samplers;
bool debug_enabled =
- (INTEL_DEBUG & intel_debug_flag_for_shader_stage(shader->Stage));
+ INTEL_DEBUG(intel_debug_flag_for_shader_stage(shader->Stage));
if (debug_enabled && shader->ir) {
fprintf(stderr, "GLSL IR for native %s shader %d:\n",
diff --git a/src/mesa/drivers/dri/i965/brw_mipmap_tree.c b/src/mesa/drivers/dri/i965/brw_mipmap_tree.c
index 9165efc55e7..2c85f9b3900 100644
--- a/src/mesa/drivers/dri/i965/brw_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/brw_mipmap_tree.c
@@ -170,7 +170,7 @@ brw_miptree_choose_aux_usage(struct brw_context *brw,
if (_mesa_is_format_color_format(mt->format)) {
if (mt->surf.samples > 1) {
mt->aux_usage = ISL_AUX_USAGE_MCS;
- } else if (!(INTEL_DEBUG & DEBUG_NO_RBC) &&
+ } else if (!INTEL_DEBUG(DEBUG_NO_RBC) &&
format_supports_ccs_e(brw, mt->format)) {
mt->aux_usage = ISL_AUX_USAGE_CCS_E;
} else if (brw->mesa_format_supports_render[mt->format]) {
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 655dd7ccc18..43bd4d6711e 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -249,7 +249,7 @@ brw_begin_perf_query(struct gl_context *ctx,
bool ret = intel_perf_begin_query(perf_ctx, obj);
- if (INTEL_DEBUG & DEBUG_PERFMON)
+ if (INTEL_DEBUG(DEBUG_PERFMON))
dump_perf_queries(brw);
return ret;
@@ -315,7 +315,7 @@ brw_get_perf_query_data(struct gl_context *ctx,
DBG("GetData(%d)\n", o->Id);
- if (INTEL_DEBUG & DEBUG_PERFMON)
+ if (INTEL_DEBUG(DEBUG_PERFMON))
dump_perf_queries(brw);
/* We expect that the frontend only calls this hook when it knows
diff --git a/src/mesa/drivers/dri/i965/brw_pixel_bitmap.c b/src/mesa/drivers/dri/i965/brw_pixel_bitmap.c
index d62fac8ab51..aa8c2fc5a2b 100644
--- a/src/mesa/drivers/dri/i965/brw_pixel_bitmap.c
+++ b/src/mesa/drivers/dri/i965/brw_pixel_bitmap.c
@@ -311,7 +311,7 @@ do_blit_bitmap(struct gl_context *ctx,
}
out:
- if (INTEL_DEBUG & DEBUG_SYNC)
+ if (INTEL_DEBUG(DEBUG_SYNC))
brw_batch_flush(brw);
if (unpack->BufferObj) {
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index ffa06980f7a..cbce06c2d5b 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -791,7 +791,7 @@ brw_assign_common_binding_table_offsets(const struct intel_device_info *devinfo,
stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
}
- if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
+ if (INTEL_DEBUG(DEBUG_SHADER_TIME)) {
stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
next_binding_table_offset++;
} else {
diff --git a/src/mesa/drivers/dri/i965/brw_screen.c b/src/mesa/drivers/dri/i965/brw_screen.c
index b8e44f4b412..fbf81e6b60c 100644
--- a/src/mesa/drivers/dri/i965/brw_screen.c
+++ b/src/mesa/drivers/dri/i965/brw_screen.c
@@ -374,7 +374,7 @@ modifier_is_supported(const struct intel_device_info *devinfo,
if (modinfo->aux_usage == ISL_AUX_USAGE_CCS_E) {
/* If INTEL_DEBUG=norbc is set, don't support any CCS_E modifiers */
- if (INTEL_DEBUG & DEBUG_NO_RBC)
+ if (INTEL_DEBUG(DEBUG_NO_RBC))
return false;
/* CCS_E is not supported for planar images */
@@ -2489,7 +2489,7 @@ shader_perf_log_mesa(void *data, unsigned *msg_id, const char *fmt, ...)
va_list args;
va_start(args, fmt);
- if (INTEL_DEBUG & DEBUG_PERF) {
+ if (INTEL_DEBUG(DEBUG_PERF)) {
va_list args_copy;
va_copy(args_copy, args);
vfprintf(stderr, fmt, args_copy);
@@ -2561,7 +2561,7 @@ __DRIconfig **brw_init_screen(__DRIscreen *dri_screen)
brw_process_intel_debug_variable();
- if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && devinfo->ver < 7) {
+ if (INTEL_DEBUG(DEBUG_SHADER_TIME) && devinfo->ver < 7) {
fprintf(stderr,
"shader_time debugging requires gfx7 (Ivybridge) or better.\n");
intel_debug &= ~DEBUG_SHADER_TIME;
@@ -2812,7 +2812,7 @@ __DRIconfig **brw_init_screen(__DRIscreen *dri_screen)
brw_screen_init_surface_formats(screen);
- if (INTEL_DEBUG & (DEBUG_BATCH | DEBUG_SUBMIT)) {
+ if (INTEL_DEBUG(DEBUG_BATCH | DEBUG_SUBMIT)) {
unsigned int caps = brw_get_integer(screen, I915_PARAM_HAS_SCHEDULER);
if (caps) {
fprintf(stderr, "Kernel scheduler detected: %08x\n", caps);
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 94fda31d692..8b2c1dedaf5 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -619,7 +619,7 @@ brw_upload_pipeline_state(struct brw_context *brw,
if (pipeline == BRW_RENDER_PIPELINE && brw->current_hash_scale != 1)
brw_emit_hashing_mode(brw, UINT_MAX, UINT_MAX, 1);
- if (INTEL_DEBUG & DEBUG_REEMIT) {
+ if (INTEL_DEBUG(DEBUG_REEMIT)) {
/* Always re-emit all state. */
brw->NewGLState = ~0;
ctx->NewDriverState = ~0ull;
@@ -689,7 +689,7 @@ brw_upload_pipeline_state(struct brw_context *brw,
brw_get_pipeline_atoms(brw, pipeline);
const int num_atoms = brw->num_atoms[pipeline];
- if (INTEL_DEBUG) {
+ if (INTEL_DEBUG(DEBUG_ANY)) {
/* Debug version which enforces various sanity checks on the
* state flags which are generated and checked to help ensure
* state atoms are ordered correctly in the list.
@@ -723,7 +723,7 @@ brw_upload_pipeline_state(struct brw_context *brw,
}
}
- if (INTEL_DEBUG & DEBUG_STATE) {
+ if (INTEL_DEBUG(DEBUG_STATE)) {
STATIC_ASSERT(ARRAY_SIZE(brw_bits) == BRW_NUM_STATE_BITS + 1);
brw_update_dirty_count(mesa_bits, state.mesa);
diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c b/src/mesa/drivers/dri/i965/brw_tcs.c
index faf6ad57b0c..5eaa3ed2ff8 100644
--- a/src/mesa/drivers/dri/i965/brw_tcs.c
+++ b/src/mesa/drivers/dri/i965/brw_tcs.c
@@ -100,7 +100,7 @@ brw_codegen_tcs_prog(struct brw_context *brw, struct brw_program *tcp,
}
int st_index = -1;
- if (((INTEL_DEBUG & DEBUG_SHADER_TIME) && tep))
+ if (INTEL_DEBUG(DEBUG_SHADER_TIME) && tep)
st_index = brw_get_shader_time_index(brw, &tep->program, ST_TCS, true);
if (unlikely(brw->perf_debug)) {
diff --git a/src/mesa/drivers/dri/i965/brw_tes.c b/src/mesa/drivers/dri/i965/brw_tes.c
index 9cafd2dd848..19114c5b0c4 100644
--- a/src/mesa/drivers/dri/i965/brw_tes.c
+++ b/src/mesa/drivers/dri/i965/brw_tes.c
@@ -63,7 +63,7 @@ brw_codegen_tes_prog(struct brw_context *brw,
}
int st_index = -1;
- if (INTEL_DEBUG & DEBUG_SHADER_TIME)
+ if (INTEL_DEBUG(DEBUG_SHADER_TIME))
st_index = brw_get_shader_time_index(brw, &tep->program, ST_TES, true);
if (unlikely(brw->perf_debug)) {
diff --git a/src/mesa/drivers/dri/i965/brw_urb.c b/src/mesa/drivers/dri/i965/brw_urb.c
index a6bd447c5f1..81175467321 100644
--- a/src/mesa/drivers/dri/i965/brw_urb.c
+++ b/src/mesa/drivers/dri/i965/brw_urb.c
@@ -189,12 +189,12 @@ brw_calculate_urb_fence(struct brw_context *brw, unsigned csize,
exit(1);
}
- if (INTEL_DEBUG & (DEBUG_URB|DEBUG_PERF))
+ if (INTEL_DEBUG(DEBUG_URB|DEBUG_PERF))
fprintf(stderr, "URB CONSTRAINED\n");
}
done:
- if (INTEL_DEBUG & DEBUG_URB)
+ if (INTEL_DEBUG(DEBUG_URB))
fprintf(stderr,
"URB fence: %d ..VS.. %d ..GS.. %d ..CLP.. %d ..SF.. %d ..CS.. %d\n",
brw->urb.vs_start,
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index e41bdcdd7ec..1d22c0d56d5 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -172,7 +172,7 @@ brw_codegen_vs_prog(struct brw_context *brw,
start_time = get_time();
}
- if (INTEL_DEBUG & DEBUG_VS) {
+ if (INTEL_DEBUG(DEBUG_VS)) {
if (vp->program.info.is_arb_asm)
brw_dump_arb_asm("vertex", &vp->program);
}
@@ -187,7 +187,7 @@ brw_codegen_vs_prog(struct brw_context *brw,
.log_data = brw,
};
- if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
+ if (INTEL_DEBUG(DEBUG_SHADER_TIME)) {
params.shader_time = true;
params.shader_time_index =
brw_get_shader_time_index(brw, &vp->program, ST_VS,
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index 7912f6ab034..36dbad1a1ba 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -101,7 +101,7 @@ brw_codegen_wm_prog(struct brw_context *brw,
} else {
brw_nir_setup_arb_uniforms(mem_ctx, nir, &fp->program, &prog_data.base);
- if (INTEL_DEBUG & DEBUG_WM)
+ if (INTEL_DEBUG(DEBUG_WM))
brw_dump_arb_asm("fragment", &fp->program);
}
@@ -122,7 +122,7 @@ brw_codegen_wm_prog(struct brw_context *brw,
.log_data = brw,
};
- if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
+ if (INTEL_DEBUG(DEBUG_SHADER_TIME)) {
params.shader_time = true;
params.shader_time_index8 =
brw_get_shader_time_index(brw, &fp->program, ST_FS8,
@@ -164,7 +164,7 @@ brw_codegen_wm_prog(struct brw_context *brw,
brw_alloc_stage_scratch(brw, &brw->wm.base, prog_data.base.total_scratch);
- if (((INTEL_DEBUG & DEBUG_WM) && fp->program.info.is_arb_asm))
+ if (INTEL_DEBUG(DEBUG_WM) && fp->program.info.is_arb_asm)
fprintf(stderr, "\n");
/* The param and pull_param arrays will be freed by the shader cache. */
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c
index f34b5823289..efe9abc5867 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -4273,7 +4273,7 @@ genX(upload_cs_state)(struct brw_context *brw)
const struct brw_cs_dispatch_info dispatch =
brw_cs_get_dispatch_info(devinfo, cs_prog_data, brw->compute.group_size);
- if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
+ if (INTEL_DEBUG(DEBUG_SHADER_TIME)) {
brw_emit_buffer_surface_state(
brw, &stage_state->surf_offset[
prog_data->binding_table.shader_time_start],
diff --git a/src/mesa/drivers/dri/i965/gfx7_l3_state.c b/src/mesa/drivers/dri/i965/gfx7_l3_state.c
index 9d36be5e1f1..f7ef5c1d3e1 100644
--- a/src/mesa/drivers/dri/i965/gfx7_l3_state.c
+++ b/src/mesa/drivers/dri/i965/gfx7_l3_state.c
@@ -242,7 +242,7 @@ brw_emit_l3_state(struct brw_context *brw)
update_urb_size(brw, cfg);
brw->l3.config = cfg;
- if (INTEL_DEBUG & DEBUG_L3) {
+ if (INTEL_DEBUG(DEBUG_L3)) {
fprintf(stderr, "L3 config transition (%f > %f): ", dw, dw_threshold);
intel_dump_l3_config(cfg, stderr);
}