diff options
| author | Kenneth Graunke <kenneth@whitecape.org> | 2013-08-13 15:03:12 -0700 |
|---|---|---|
| committer | Ian Romanick <ian.d.romanick@intel.com> | 2013-08-16 12:36:31 -0700 |
| commit | e2185778e2e6d2d1c6bd7846e94f5ebfd3cdd160 (patch) | |
| tree | 50a6e6b52abc441e52ba9029d6b34cf441c60df3 /src/mesa/drivers/dri/i965 | |
| parent | a98d5f2663dc8488b4232449369df45f2dfaa42f (diff) | |
i965: Force X-tiling for 128 bpp formats on Sandybridge.
128 bpp formats are not allowed to be Y-tiled on any architectures
except Gen7.
+11 Piglits on Sandybridge (mostly regression fixes since the
switch to Y-tiling).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63867
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64261
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "9.2" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit c189840b21e176d87cbb382e64e848061b8c7b06)
Diffstat (limited to 'src/mesa/drivers/dri/i965')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 36a080f8f74..6775909d036 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -468,6 +468,15 @@ intel_miptree_choose_tiling(struct brw_context *brw, if (brw->gen < 6) return I915_TILING_X; + /* From the Sandybridge PRM, Volume 1, Part 2, page 32: + * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX + * or Linear." + * 128 bits per pixel translates to 16 bytes per pixel. This is necessary + * all the way back to 965, but is explicitly permitted on Gen7. + */ + if (brw->gen != 7 && mt->cpp >= 16) + return I915_TILING_X; + return I915_TILING_Y | I915_TILING_X; } |