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authorNanley Chery <nanley.g.chery@intel.com>2020-02-21 11:49:55 -0800
committerMarge Bot <eric+marge@anholt.net>2020-02-24 18:00:05 +0000
commitb62379ac6f699933da52d032e2b3c06ab73f9549 (patch)
treec990663a818a18584af5f7aa9bfcd7b138d6a161 /src/mesa/drivers/dri/i965/intel_mipmap_tree.c
parentb9856fbf3b7ddbe0b77bf984fe7ec4a64ad858bf (diff)
i965: Use isl_aux_state_transition_write()
v2. Dirty shadow miptrees independent of aux. (Jason) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_mipmap_tree.c')
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.c199
1 files changed, 16 insertions, 183 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 0f67b6c9a85..63ca925e775 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1813,151 +1813,6 @@ intel_miptree_check_color_resolve(const struct brw_context *brw,
(void)layer;
}
-static void
-intel_miptree_finish_ccs_write(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- uint32_t level, uint32_t layer,
- enum isl_aux_usage aux_usage)
-{
- assert(aux_usage == ISL_AUX_USAGE_NONE ||
- aux_usage == ISL_AUX_USAGE_CCS_D ||
- aux_usage == ISL_AUX_USAGE_CCS_E);
-
- enum isl_aux_state aux_state = intel_miptree_get_aux_state(mt, level, layer);
-
- if (mt->aux_usage == ISL_AUX_USAGE_CCS_E) {
- switch (aux_state) {
- case ISL_AUX_STATE_CLEAR:
- case ISL_AUX_STATE_PARTIAL_CLEAR:
- assert(aux_usage == ISL_AUX_USAGE_CCS_E ||
- aux_usage == ISL_AUX_USAGE_CCS_D);
-
- if (aux_usage == ISL_AUX_USAGE_CCS_E) {
- intel_miptree_set_aux_state(brw, mt, level, layer, 1,
- ISL_AUX_STATE_COMPRESSED_CLEAR);
- } else if (aux_state != ISL_AUX_STATE_PARTIAL_CLEAR) {
- intel_miptree_set_aux_state(brw, mt, level, layer, 1,
- ISL_AUX_STATE_PARTIAL_CLEAR);
- }
- break;
-
- case ISL_AUX_STATE_COMPRESSED_CLEAR:
- case ISL_AUX_STATE_COMPRESSED_NO_CLEAR:
- assert(aux_usage == ISL_AUX_USAGE_CCS_E);
- break; /* Nothing to do */
-
- case ISL_AUX_STATE_PASS_THROUGH:
- if (aux_usage == ISL_AUX_USAGE_CCS_E) {
- intel_miptree_set_aux_state(brw, mt, level, layer, 1,
- ISL_AUX_STATE_COMPRESSED_NO_CLEAR);
- } else {
- /* Nothing to do */
- }
- break;
-
- case ISL_AUX_STATE_RESOLVED:
- case ISL_AUX_STATE_AUX_INVALID:
- unreachable("Invalid aux state for CCS_E");
- }
- } else {
- assert(mt->aux_usage == ISL_AUX_USAGE_CCS_D);
- /* CCS_D is a bit simpler */
- switch (aux_state) {
- case ISL_AUX_STATE_CLEAR:
- assert(aux_usage == ISL_AUX_USAGE_CCS_D);
- intel_miptree_set_aux_state(brw, mt, level, layer, 1,
- ISL_AUX_STATE_PARTIAL_CLEAR);
- break;
-
- case ISL_AUX_STATE_PARTIAL_CLEAR:
- assert(aux_usage == ISL_AUX_USAGE_CCS_D);
- break; /* Nothing to do */
-
- case ISL_AUX_STATE_PASS_THROUGH:
- /* Nothing to do */
- break;
-
- case ISL_AUX_STATE_COMPRESSED_CLEAR:
- case ISL_AUX_STATE_COMPRESSED_NO_CLEAR:
- case ISL_AUX_STATE_RESOLVED:
- case ISL_AUX_STATE_AUX_INVALID:
- unreachable("Invalid aux state for CCS_D");
- }
- }
-}
-
-static void
-intel_miptree_finish_mcs_write(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- uint32_t layer,
- enum isl_aux_usage aux_usage)
-{
- assert(aux_usage == ISL_AUX_USAGE_MCS);
-
- switch (intel_miptree_get_aux_state(mt, 0, layer)) {
- case ISL_AUX_STATE_CLEAR:
- intel_miptree_set_aux_state(brw, mt, 0, layer, 1,
- ISL_AUX_STATE_COMPRESSED_CLEAR);
- break;
-
- case ISL_AUX_STATE_COMPRESSED_CLEAR:
- case ISL_AUX_STATE_COMPRESSED_NO_CLEAR:
- break; /* Nothing to do */
-
- case ISL_AUX_STATE_RESOLVED:
- case ISL_AUX_STATE_PASS_THROUGH:
- case ISL_AUX_STATE_AUX_INVALID:
- case ISL_AUX_STATE_PARTIAL_CLEAR:
- unreachable("Invalid aux state for MCS");
- }
-}
-
-static void
-intel_miptree_finish_hiz_write(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- uint32_t level, uint32_t layer,
- enum isl_aux_usage aux_usage)
-{
- assert(aux_usage == ISL_AUX_USAGE_NONE || aux_usage == ISL_AUX_USAGE_HIZ);
-
- switch (intel_miptree_get_aux_state(mt, level, layer)) {
- case ISL_AUX_STATE_CLEAR:
- assert(aux_usage == ISL_AUX_USAGE_HIZ);
- intel_miptree_set_aux_state(brw, mt, level, layer, 1,
- ISL_AUX_STATE_COMPRESSED_CLEAR);
- break;
-
- case ISL_AUX_STATE_COMPRESSED_NO_CLEAR:
- case ISL_AUX_STATE_COMPRESSED_CLEAR:
- assert(aux_usage == ISL_AUX_USAGE_HIZ);
- break; /* Nothing to do */
-
- case ISL_AUX_STATE_RESOLVED:
- if (aux_usage == ISL_AUX_USAGE_HIZ) {
- intel_miptree_set_aux_state(brw, mt, level, layer, 1,
- ISL_AUX_STATE_COMPRESSED_NO_CLEAR);
- } else {
- intel_miptree_set_aux_state(brw, mt, level, layer, 1,
- ISL_AUX_STATE_AUX_INVALID);
- }
- break;
-
- case ISL_AUX_STATE_PASS_THROUGH:
- if (aux_usage == ISL_AUX_USAGE_HIZ) {
- intel_miptree_set_aux_state(brw, mt, level, layer, 1,
- ISL_AUX_STATE_COMPRESSED_NO_CLEAR);
- }
- break;
-
- case ISL_AUX_STATE_AUX_INVALID:
- assert(aux_usage != ISL_AUX_USAGE_HIZ);
- break;
-
- case ISL_AUX_STATE_PARTIAL_CLEAR:
- unreachable("Invalid HiZ state");
- }
-}
-
void
intel_miptree_prepare_access(struct brw_context *brw,
struct intel_mipmap_tree *mt,
@@ -2009,48 +1864,26 @@ intel_miptree_finish_write(struct brw_context *brw,
enum isl_aux_usage aux_usage)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
- num_layers = miptree_layer_range_length(mt, level, start_layer, num_layers);
-
- switch (mt->aux_usage) {
- case ISL_AUX_USAGE_NONE:
- if (mt->format == MESA_FORMAT_S_UINT8 && devinfo->gen <= 7) {
- mt->shadow_needs_update = true;
- } else if (intel_miptree_has_etc_shadow(brw, mt)) {
- mt->shadow_needs_update = true;
- }
- break;
- case ISL_AUX_USAGE_MCS:
- assert(mt->aux_buf);
- for (uint32_t a = 0; a < num_layers; a++) {
- intel_miptree_finish_mcs_write(brw, mt, start_layer + a,
- aux_usage);
- }
- break;
-
- case ISL_AUX_USAGE_CCS_D:
- case ISL_AUX_USAGE_CCS_E:
- if (!mt->aux_buf)
- return;
-
- for (uint32_t a = 0; a < num_layers; a++) {
- intel_miptree_finish_ccs_write(brw, mt, level, start_layer + a,
- aux_usage);
- }
- break;
+ if (mt->format == MESA_FORMAT_S_UINT8 && devinfo->gen <= 7) {
+ mt->shadow_needs_update = true;
+ } else if (intel_miptree_has_etc_shadow(brw, mt)) {
+ mt->shadow_needs_update = true;
+ }
- case ISL_AUX_USAGE_HIZ:
- if (!intel_miptree_level_has_hiz(mt, level))
- return;
+ if (!level_has_aux(mt, level))
+ return;
- for (uint32_t a = 0; a < num_layers; a++) {
- intel_miptree_finish_hiz_write(brw, mt, level, start_layer + a,
- aux_usage);
- }
- break;
+ const uint32_t level_layers =
+ miptree_layer_range_length(mt, level, start_layer, num_layers);
- default:
- unreachable("Invavlid aux usage");
+ for (uint32_t a = 0; a < level_layers; a++) {
+ const uint32_t layer = start_layer + a;
+ const enum isl_aux_state aux_state =
+ intel_miptree_get_aux_state(mt, level, layer);
+ const enum isl_aux_state new_aux_state =
+ isl_aux_state_transition_write(aux_state, aux_usage, false);
+ intel_miptree_set_aux_state(brw, mt, level, layer, 1, new_aux_state);
}
}