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authorChad Versace <chad.versace@intel.com>2015-10-08 12:21:19 -0700
committerChad Versace <chad.versace@intel.com>2015-10-09 14:24:12 -0700
commit82b324c24bc28ae99a6110706c85460b71d26077 (patch)
tree52094b9bce9300d21c17f24c3d0c1c4324a01264 /src/mesa/drivers/dri/i965/gen8_surface_state.c
parent8a0c85b25853decb4a110b6d36d79c4f095d437b (diff)
i965/gen8: Remove gen<8 checks in gen8 codeskl-fast-clear-v12.00skl-fast-clear-v11.00
Some assertions in gen8_surface_state.c checked for gen < 8. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen8_surface_state.c')
-rw-r--r--src/mesa/drivers/dri/i965/gen8_surface_state.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index e1e7704655d..18b86652fd2 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -221,8 +221,8 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
* "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
* 16 must be used."
*/
- assert(brw->gen < 9 || mt->halign == 16);
- assert(brw->gen < 8 || mt->num_samples > 1 || mt->halign == 16);
+ if (brw->gen >= 9 || mt->num_samples == 1)
+ assert(mt->halign == 16);
}
const uint32_t surf_type = translate_tex_target(target);
@@ -470,8 +470,8 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
* "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
* 16 must be used."
*/
- assert(brw->gen < 9 || mt->halign == 16);
- assert(brw->gen < 8 || mt->num_samples > 1 || mt->halign == 16);
+ if (brw->gen >= 9 || mt->num_samples == 1)
+ assert(mt->halign == 16);
}
uint32_t *surf = allocate_surface_state(brw, &offset, surf_index);