diff options
| author | Eric Anholt <eric@anholt.net> | 2014-04-06 12:08:37 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2014-04-11 13:38:53 -0700 |
| commit | 99442bc7b20e4d76a5bdff72821e86a7ff5942ab (patch) | |
| tree | 55c4999b2ab61a3b4bc3628283aaf48dd7a66dce /src/mesa/drivers/dri/i965/brw_draw_upload.c | |
| parent | 9a5d19d680323dfb9705c6c5ac10ac30d9ccc842 (diff) | |
i965: Stop setting up a 1:1 "attrib" member in our vertex inputs.
It's just the array index, so we can just go look at the array and see
which element we are.
No significant performance difference (n=140)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_draw_upload.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_draw_upload.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 2b56cdedd1c..45e9d3f93d2 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -713,7 +713,7 @@ static void brw_emit_vertices(struct brw_context *brw) uint32_t comp2 = BRW_VE1_COMPONENT_STORE_SRC; uint32_t comp3 = BRW_VE1_COMPONENT_STORE_SRC; - if (input->attrib == VERT_ATTRIB_EDGEFLAG) { + if (input == &brw->vb.inputs[VERT_ATTRIB_EDGEFLAG]) { /* Gen6+ passes edgeflag as sideband along with the vertex, instead * of in the VUE. We have to upload it sideband as the last vertex * element according to the B-Spec. |