diff options
| author | Jason Ekstrand <jason.ekstrand@collabora.com> | 2022-11-29 14:05:19 -0600 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2022-12-01 04:56:48 +0000 |
| commit | b4dd3df22797afe3c4b8aa5313edc4a2db7a2b58 (patch) | |
| tree | e20a9099161fef7657f7cbca2da0f95cfb69c30b /src/intel | |
| parent | 19ad2629d067bb38b47dcb03733bd6609a774f44 (diff) | |
intel/nir: Set has_base_workgroup_id for lower_compute_system_values
This option didn't exist half a decade ago when I first implemented base
workgroup support in ANV. It's cleaner to just have split system values
like all the other zero_base+base things do.
We currently only do this for COMPUTE and not KERNEL because it lets us
avoid changing intel_clc for now. We can add KERNEL later if needed.
We also don't do this lowering for task/mesh.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>
Diffstat (limited to 'src/intel')
| -rw-r--r-- | src/intel/compiler/brw_nir.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index d4b0e8c8d3f..b89d7db4ddb 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -974,7 +974,10 @@ brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir, } OPT(nir_lower_system_values); - OPT(nir_lower_compute_system_values, NULL); + nir_lower_compute_system_values_options lower_csv_options = { + .has_base_workgroup_id = nir->info.stage == MESA_SHADER_COMPUTE, + }; + OPT(nir_lower_compute_system_values, &lower_csv_options); const nir_lower_subgroups_options subgroups_options = { .ballot_bit_size = 32, |