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authorAnuj Phogat <anuj.phogat@gmail.com>2017-06-13 17:01:16 -0700
committerAnuj Phogat <anuj.phogat@gmail.com>2017-06-23 11:16:00 -0700
commit7896dee349bf747f5c03a9f5206a548b7482e72c (patch)
tree280a0fa15bac050299f3fe3ee94d4cf73576a911 /src/intel
parentb98055330932a19997e68f2c935b0c7dfd90d9c1 (diff)
anv/cnl: Don't write to Cache Mode Register 1 on gen10+
For PartialResolveDisableInVC field recommendation is to always set this to 0 and that's the default value of the bit. So, we have nothing left to write to CACHE_MODE_1. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/vulkan/genX_state.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index 7a16ec06f71..3e6583289b6 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -52,13 +52,11 @@ genX(init_device_state)(struct anv_device *device)
ps.PipelineSelection = _3D;
}
-#if GEN_GEN >= 9
+#if GEN_GEN == 9
uint32_t cache_mode_1;
anv_pack_struct(&cache_mode_1, GENX(CACHE_MODE_1),
-#if GEN_GEN == 9
.FloatBlendOptimizationEnable = true,
.FloatBlendOptimizationEnableMask = true,
-#endif
.PartialResolveDisableInVC = true,
.PartialResolveDisableInVCMask = true);