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authorLionel Landwerlin <lionel.g.landwerlin@intel.com>2017-06-20 11:06:24 +0100
committerLionel Landwerlin <lionel.g.landwerlin@intel.com>2017-06-20 23:26:42 +0100
commit030abc61091a38596427aa04022066719be9add5 (patch)
tree31bcc61d00bf788ffa04a03aacd8a2451427c50e /src/intel
parentb3b61211157ab934f1898d3519e7288c1fd89d80 (diff)
intel: compiler/i965: fix is_broxton checks
In 5f2fe9302c is_geminilake was introduced for the differenciate broxton from geminilake. Unfortunately I failed as verifying that is_broxton is throughout the code base to mean Gen9lp. Fixes: 5f2fe9302c ("intel: common: add flag to identify platforms by name") Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/intel')
-rw-r--r--src/intel/common/gen_device_info.h3
-rw-r--r--src/intel/compiler/brw_fs.cpp2
-rw-r--r--src/intel/compiler/brw_fs_nir.cpp4
-rw-r--r--src/intel/compiler/brw_vec4.cpp2
-rw-r--r--src/intel/isl/isl_format.c4
5 files changed, 9 insertions, 6 deletions
diff --git a/src/intel/common/gen_device_info.h b/src/intel/common/gen_device_info.h
index 920a3365025..cc83857b759 100644
--- a/src/intel/common/gen_device_info.h
+++ b/src/intel/common/gen_device_info.h
@@ -186,6 +186,9 @@ struct gen_device_info
/** @} */
};
+#define gen_device_info_is_9lp(devinfo) \
+ (devinfo->is_broxton || devinfo->is_geminilake)
+
bool gen_get_device_info(int devid, struct gen_device_info *devinfo);
const char *gen_get_device_name(int devid);
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 90a650add07..43b6e342043 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -3348,7 +3348,7 @@ fs_visitor::lower_integer_multiplication()
* operation directly, but CHV/BXT cannot.
*/
if (devinfo->gen >= 8 &&
- !devinfo->is_cherryview && !devinfo->is_broxton)
+ !devinfo->is_cherryview && !gen_device_info_is_9lp(devinfo))
continue;
if (inst->src[1].file == IMM &&
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 876b1030ec0..a9dce42c38d 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -639,7 +639,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
*/
if (nir_dest_bit_size(instr->dest.dest) == 64 &&
nir_src_bit_size(instr->src[0].src) == 32 &&
- (devinfo->is_cherryview || devinfo->is_broxton)) {
+ (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
fs_reg tmp = bld.vgrf(result.type, 1);
tmp = subscript(tmp, op[0].type, 0);
inst = bld.MOV(tmp, op[0]);
@@ -3748,7 +3748,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
(instr->num_components - 1) * type_sz(dest.type);
bool supports_64bit_indirects =
- !devinfo->is_cherryview && !devinfo->is_broxton;
+ !devinfo->is_cherryview && !gen_device_info_is_9lp(devinfo);
if (type_sz(dest.type) != 8 || supports_64bit_indirects) {
for (unsigned j = 0; j < instr->num_components; j++) {
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index b443effca9a..3de7d931dde 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -985,7 +985,7 @@ vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction *inst)
* affected, at least by the 64b restriction, since DepCtrl with double
* precision instructions seems to produce GPU hangs in some cases.
*/
- if (devinfo->gen == 8 || devinfo->is_broxton) {
+ if (devinfo->gen == 8 || gen_device_info_is_9lp(devinfo)) {
if (inst->opcode == BRW_OPCODE_MUL &&
IS_DWORD(inst->src[0]) &&
IS_DWORD(inst->src[1]))
diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
index 31c74bd5f0f..a9f9c6be73a 100644
--- a/src/intel/isl/isl_format.c
+++ b/src/intel/isl/isl_format.c
@@ -406,7 +406,7 @@ isl_format_supports_sampling(const struct gen_device_info *devinfo,
*/
if (fmtl->txc == ISL_TXC_ASTC)
return format < ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16;
- } else if (devinfo->is_broxton) {
+ } else if (gen_device_info_is_9lp(devinfo)) {
const struct isl_format_layout *fmtl = isl_format_get_layout(format);
/* Support for ASTC HDR exists on Broxton even though big-core
* GPUs didn't get it until Cannonlake.
@@ -439,7 +439,7 @@ isl_format_supports_filtering(const struct gen_device_info *devinfo,
*/
if (fmtl->txc == ISL_TXC_ASTC)
return format < ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16;
- } else if (devinfo->is_broxton) {
+ } else if (gen_device_info_is_9lp(devinfo)) {
const struct isl_format_layout *fmtl = isl_format_get_layout(format);
/* Support for ASTC HDR exists on Broxton even though big-core
* GPUs didn't get it until Cannonlake.