diff options
| author | Jason Ekstrand <jason.ekstrand@intel.com> | 2019-02-27 16:08:20 -0600 |
|---|---|---|
| committer | Jason Ekstrand <jason@jlekstrand.net> | 2019-04-19 19:56:42 +0000 |
| commit | 6e230d7607f9b3e082d00859bd7725c4dc87e5cf (patch) | |
| tree | b16be9b8611f6700676a6637c7544991d8e884e3 /src/intel/vulkan/anv_pipeline.c | |
| parent | d6c9bd6e01b4d593f362a3b5518a71acf2e83ca1 (diff) | |
anv: Implement VK_EXT_descriptor_indexing
Now that everything is in place to do bindless for all resource types
except input attachments and UBOs, VK_EXT_descriptor_indexing is
"trivial".
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Diffstat (limited to 'src/intel/vulkan/anv_pipeline.c')
| -rw-r--r-- | src/intel/vulkan/anv_pipeline.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 09abf4e85fd..64d4d93803c 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -138,6 +138,7 @@ anv_shader_compile_to_nir(struct anv_device *device, .lower_workgroup_access_to_offsets = true, .caps = { .derivative_group = true, + .descriptor_array_dynamic_indexing = true, .device_group = true, .draw_parameters = true, .float16 = pdevice->info.gen >= 8, @@ -152,6 +153,7 @@ anv_shader_compile_to_nir(struct anv_device *device, .multiview = true, .physical_storage_buffer_address = pdevice->has_a64_buffer_access, .post_depth_coverage = pdevice->info.gen >= 9, + .runtime_descriptor_array = true, .shader_viewport_index_layer = true, .stencil_export = pdevice->info.gen >= 9, .storage_8bit = pdevice->info.gen >= 8, @@ -638,6 +640,13 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline, ssbo_address_format); NIR_PASS_V(nir, nir_opt_constant_folding); + + /* We don't support non-uniform UBOs and non-uniform SSBO access is + * handled naturally by falling back to A64 messages. + */ + NIR_PASS_V(nir, nir_lower_non_uniform_access, + nir_lower_non_uniform_texture_access | + nir_lower_non_uniform_image_access); } if (nir->info.stage != MESA_SHADER_COMPUTE) |