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authorNanley Chery <nanley.g.chery@intel.com>2017-05-16 16:20:59 -0700
committerNanley Chery <nanley.g.chery@intel.com>2017-05-22 11:13:53 -0700
commit52a6fd98713b8a4d438567684067beada618ed0e (patch)
tree81cd26b0d6d875c86928cd2cf3b246a686034975 /src/intel/isl/isl_format.c
parentb2c5e69942ee795af6de6e99d5f597ba4bd61859 (diff)
intel/isl: Add ASTC HDR to format lists and helpers
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Diffstat (limited to 'src/intel/isl/isl_format.c')
-rw-r--r--src/intel/isl/isl_format.c32
1 files changed, 30 insertions, 2 deletions
diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
index 165c7e5b6b2..e6d2a438d30 100644
--- a/src/intel/isl/isl_format.c
+++ b/src/intel/isl/isl_format.c
@@ -341,6 +341,20 @@ static const struct surface_format_info format_info[] = {
SF(90, 90, x, x, x, x, x, x, x, x, x, x, ASTC_LDR_2D_10X10_U8SRGB)
SF(90, 90, x, x, x, x, x, x, x, x, x, x, ASTC_LDR_2D_12X10_U8SRGB)
SF(90, 90, x, x, x, x, x, x, x, x, x, x, ASTC_LDR_2D_12X12_U8SRGB)
+ SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_4X4_FLT16)
+ SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_5X4_FLT16)
+ SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_5X5_FLT16)
+ SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_6X5_FLT16)
+ SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_6X6_FLT16)
+ SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_8X5_FLT16)
+ SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_8X6_FLT16)
+ SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_8X8_FLT16)
+ SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_10X5_FLT16)
+ SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_10X6_FLT16)
+ SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_10X8_FLT16)
+ SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_10X10_FLT16)
+ SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_12X10_FLT16)
+ SF(100, 100, x, x, x, x, x, x, x, x, x, x, ASTC_HDR_2D_12X12_FLT16)
};
#undef x
#undef Y
@@ -387,10 +401,17 @@ isl_format_supports_sampling(const struct gen_device_info *devinfo,
return true;
} else if (devinfo->is_cherryview) {
const struct isl_format_layout *fmtl = isl_format_get_layout(format);
- /* Support for ASTC exists on Cherry View even though big-core
+ /* Support for ASTC LDR exists on Cherry View even though big-core
* GPUs didn't get it until Skylake.
*/
if (fmtl->txc == ISL_TXC_ASTC)
+ return format < ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16;
+ } else if (devinfo->is_broxton) {
+ const struct isl_format_layout *fmtl = isl_format_get_layout(format);
+ /* Support for ASTC HDR exists on Broxton even though big-core
+ * GPUs didn't get it until Cannonlake.
+ */
+ if (fmtl->txc == ISL_TXC_ASTC)
return true;
}
@@ -413,10 +434,17 @@ isl_format_supports_filtering(const struct gen_device_info *devinfo,
return true;
} else if (devinfo->is_cherryview) {
const struct isl_format_layout *fmtl = isl_format_get_layout(format);
- /* Support for ASTC exists on Cherry View even though big-core
+ /* Support for ASTC LDR exists on Cherry View even though big-core
* GPUs didn't get it until Skylake.
*/
if (fmtl->txc == ISL_TXC_ASTC)
+ return format < ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16;
+ } else if (devinfo->is_broxton) {
+ const struct isl_format_layout *fmtl = isl_format_get_layout(format);
+ /* Support for ASTC HDR exists on Broxton even though big-core
+ * GPUs didn't get it until Cannonlake.
+ */
+ if (fmtl->txc == ISL_TXC_ASTC)
return true;
}