diff options
author | Sagar Ghuge <sagar.ghuge@intel.com> | 2021-08-26 10:13:34 -0700 |
---|---|---|
committer | Marge Bot <eric+marge@anholt.net> | 2021-09-09 23:34:33 +0000 |
commit | 527468f56f45de49971622052b172f7cffb38617 (patch) | |
tree | 9d475142531230efdf458d0e30fb898e8e59eadb /src/intel/compiler/brw_fs.cpp | |
parent | 7f2395046f5e0b09821a22d45bf22ce41f0b09cb (diff) |
intel/compiler: Add 64-bit A64 float logical opcode support
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12566>
Diffstat (limited to 'src/intel/compiler/brw_fs.cpp')
-rw-r--r-- | src/intel/compiler/brw_fs.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 07eb7324e45..fd0b09b7bdc 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -884,6 +884,7 @@ fs_inst::components_read(unsigned i) const case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL: case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL: + case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL: assert(src[2].file == IMM); if (i == 1) { /* Data source */ @@ -6298,6 +6299,7 @@ lower_lsc_a64_logical_send(const fs_builder &bld, fs_inst *inst) case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL: { case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL: case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL: + case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL: /* Bspec: Atomic instruction -> Cache section: * * Atomic messages are always forced to "un-cacheable" in the L1 @@ -6933,6 +6935,7 @@ fs_visitor::lower_logical_sends() case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL: case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL: case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL: + case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL: if (devinfo->has_lsc) { lower_lsc_a64_logical_send(ibld, inst); break; @@ -7560,6 +7563,7 @@ get_lowered_simd_width(const struct intel_device_info *devinfo, case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL: case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT16_LOGICAL: case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT32_LOGICAL: + case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT64_LOGICAL: return 8; case SHADER_OPCODE_URB_READ_SIMD8: |