summaryrefslogtreecommitdiff
path: root/src/gallium
diff options
context:
space:
mode:
authorSt├ęphane Marchesin <marcheu@chromium.org>2011-07-13 11:56:44 -0700
committerSt├ęphane Marchesin <marcheu@chromium.org>2011-07-13 11:56:44 -0700
commitf7a85f603b0da0770c27b200bff6e239e3aeae95 (patch)
tree95a0a3267b12826fb82c04a6e2763fb2bce88065 /src/gallium
parent9baad926602547e14d4fdc6a66ec629dfa6acbb2 (diff)
parent4f4855b249cbcb77900e9767041becf255afbba1 (diff)
Merge branch 'master' of ssh://git.freedesktop.org/git/mesa/mesa
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/auxiliary/gallivm/lp_bld_debug.cpp16
-rw-r--r--src/gallium/auxiliary/gallivm/lp_bld_type.c6
-rw-r--r--src/gallium/auxiliary/util/u_pack_color.h64
-rw-r--r--src/gallium/auxiliary/util/u_surface.c35
-rw-r--r--src/gallium/auxiliary/util/u_tile.c35
-rw-r--r--src/gallium/auxiliary/util/u_upload_mgr.c2
-rw-r--r--src/gallium/drivers/i915/i915_context.c4
-rw-r--r--src/gallium/drivers/nvfx/nvfx_screen.c3
-rw-r--r--src/gallium/drivers/r600/eg_asm.c2
-rw-r--r--src/gallium/drivers/r600/evergreen_state.c39
-rw-r--r--src/gallium/drivers/r600/evergreend.h7
-rw-r--r--src/gallium/drivers/r600/r600_asm.c180
-rw-r--r--src/gallium/drivers/r600/r600_asm.h5
-rw-r--r--src/gallium/drivers/r600/r600_opcodes.h10
-rw-r--r--src/gallium/drivers/r600/r600_pipe.c42
-rw-r--r--src/gallium/drivers/r600/r600_pipe.h3
-rw-r--r--src/gallium/drivers/r600/r600_shader.c125
-rw-r--r--src/gallium/drivers/r600/r600_shader.h1
-rw-r--r--src/gallium/drivers/r600/r600_state.c39
-rw-r--r--src/gallium/drivers/r600/r600_state_common.c26
-rw-r--r--src/gallium/drivers/r600/r600_texture.c15
-rw-r--r--src/gallium/state_trackers/dri/common/dri_context.c2
-rw-r--r--src/gallium/state_trackers/egl/x11/x11_screen.c18
-rw-r--r--src/gallium/state_trackers/glx/xlib/glx_api.c9
-rw-r--r--src/gallium/targets/egl-static/Makefile2
-rw-r--r--src/gallium/winsys/r600/drm/evergreen_hw_context.c1
-rw-r--r--src/gallium/winsys/r600/drm/r600_drm.c10
-rw-r--r--src/gallium/winsys/r600/drm/r600_hw_context.c2
28 files changed, 422 insertions, 281 deletions
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_debug.cpp b/src/gallium/auxiliary/gallivm/lp_bld_debug.cpp
index 01e660ef7d9..29dfb868d95 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_debug.cpp
+++ b/src/gallium/auxiliary/gallivm/lp_bld_debug.cpp
@@ -207,21 +207,13 @@ lp_disassemble(const void* func)
}
raw_debug_ostream Out;
-#if HAVE_LLVM >= 0x0300
- TargetMachine *TM = T->createTargetMachine(Triple, sys::getHostCPUName(), "");
-#else
- TargetMachine *TM = T->createTargetMachine(Triple, "");
-#endif
#if HAVE_LLVM >= 0x0300
unsigned int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
#else
int AsmPrinterVariant = AsmInfo->getAssemblerDialect();
#endif
-#if HAVE_LLVM >= 0x0300
- OwningPtr<MCInstPrinter> Printer(
- T->createMCInstPrinter(*TM, AsmPrinterVariant, *AsmInfo));
-#elif HAVE_LLVM >= 0x0208
+#if HAVE_LLVM >= 0x0208
OwningPtr<MCInstPrinter> Printer(
T->createMCInstPrinter(AsmPrinterVariant, *AsmInfo));
#else
@@ -233,6 +225,12 @@ lp_disassemble(const void* func)
return;
}
+#if HAVE_LLVM >= 0x0300
+ TargetMachine *TM = T->createTargetMachine(Triple, sys::getHostCPUName(), "");
+#else
+ TargetMachine *TM = T->createTargetMachine(Triple, "");
+#endif
+
const TargetInstrInfo *TII = TM->getInstrInfo();
/*
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_type.c b/src/gallium/auxiliary/gallivm/lp_bld_type.c
index c5cf6d4a6c4..efd159f8869 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_type.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_type.c
@@ -325,16 +325,18 @@ lp_typekind_name(LLVMTypeKind t)
return "LLVMArrayTypeKind";
case LLVMPointerTypeKind:
return "LLVMPointerTypeKind";
+#if HAVE_LLVM < 0x0300
case LLVMOpaqueTypeKind:
return "LLVMOpaqueTypeKind";
+#endif
case LLVMVectorTypeKind:
return "LLVMVectorTypeKind";
case LLVMMetadataTypeKind:
return "LLVMMetadataTypeKind";
- /* Only in LLVM 2.7 and later???
+#if HAVE_LLVM == 0x0207
case LLVMUnionTypeKind:
return "LLVMUnionTypeKind";
- */
+#endif
default:
return "unknown LLVMTypeKind";
}
diff --git a/src/gallium/auxiliary/util/u_pack_color.h b/src/gallium/auxiliary/util/u_pack_color.h
index 5378f2d782f..9391f1b80e0 100644
--- a/src/gallium/auxiliary/util/u_pack_color.h
+++ b/src/gallium/auxiliary/util/u_pack_color.h
@@ -458,6 +458,19 @@ util_pack_mask_z(enum pipe_format format, uint32_t z)
}
}
+
+static INLINE uint64_t
+util_pack64_mask_z(enum pipe_format format, uint32_t z)
+{
+ switch (format) {
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+ return z;
+ default:
+ return util_pack_mask_z(format, z);
+ }
+}
+
+
static INLINE uint32_t
util_pack_mask_z_stencil(enum pipe_format format, uint32_t z, uint8_t s)
{
@@ -481,6 +494,21 @@ util_pack_mask_z_stencil(enum pipe_format format, uint32_t z, uint8_t s)
}
+static INLINE uint64_t
+util_pack64_mask_z_stencil(enum pipe_format format, uint32_t z, uint8_t s)
+{
+ uint64_t packed;
+
+ switch (format) {
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+ packed = util_pack64_mask_z(format, z);
+ packed |= (uint64_t)s << 32ull;
+ return packed;
+ default:
+ return util_pack_mask_z_stencil(format, z, s);
+ }
+}
+
/**
* Note: it's assumed that z is in [0,1]
@@ -525,6 +553,24 @@ util_pack_z(enum pipe_format format, double z)
return 0;
}
}
+
+
+static INLINE uint64_t
+util_pack64_z(enum pipe_format format, double z)
+{
+ union fi fui;
+
+ if (z == 0)
+ return 0;
+
+ switch (format) {
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+ fui.f = (float)z;
+ return fui.ui;
+ default:
+ return util_pack_z(format, z);
+ }
+}
/**
@@ -554,6 +600,24 @@ util_pack_z_stencil(enum pipe_format format, double z, uint8_t s)
}
+static INLINE uint64_t
+util_pack64_z_stencil(enum pipe_format format, double z, uint8_t s)
+{
+ uint64_t packed;
+
+ switch (format) {
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+ packed = util_pack64_z(format, z);
+ packed |= (uint64_t)s << 32ull;
+ break;
+ default:
+ return util_pack_z_stencil(format, z, s);
+ }
+
+ return packed;
+}
+
+
/**
* Pack 4 ubytes into a 4-byte word
*/
diff --git a/src/gallium/auxiliary/util/u_surface.c b/src/gallium/auxiliary/util/u_surface.c
index 4c5cc4da182..8e123867da6 100644
--- a/src/gallium/auxiliary/util/u_surface.c
+++ b/src/gallium/auxiliary/util/u_surface.c
@@ -358,8 +358,41 @@ util_clear_depth_stencil(struct pipe_context *pipe,
dst_map += dst_stride;
}
}
- break;
+ break;
case 8:
+ {
+ uint64_t zstencil = util_pack64_z_stencil(dst->texture->format,
+ depth, stencil);
+
+ assert(dst->format == PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED);
+
+ if (!need_rmw) {
+ for (i = 0; i < height; i++) {
+ uint64_t *row = (uint64_t *)dst_map;
+ for (j = 0; j < width; j++)
+ *row++ = zstencil;
+ dst_map += dst_stride;
+ }
+ }
+ else {
+ uint64_t src_mask;
+
+ if (clear_flags & PIPE_CLEAR_DEPTH)
+ src_mask = 0x00000000ffffffffull;
+ else
+ src_mask = 0x000000ff00000000ull;
+
+ for (i = 0; i < height; i++) {
+ uint64_t *row = (uint64_t *)dst_map;
+ for (j = 0; j < width; j++) {
+ uint64_t tmp = *row & ~src_mask;
+ *row++ = tmp | (zstencil & src_mask);
+ }
+ dst_map += dst_stride;
+ }
+ }
+ break;
+ }
default:
assert(0);
break;
diff --git a/src/gallium/auxiliary/util/u_tile.c b/src/gallium/auxiliary/util/u_tile.c
index e3c7085ba92..23f12e5f464 100644
--- a/src/gallium/auxiliary/util/u_tile.c
+++ b/src/gallium/auxiliary/util/u_tile.c
@@ -318,6 +318,32 @@ z32f_get_tile_rgba(const float *src,
}
}
+/*** PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED ***/
+
+/**
+ * Return each Z value as four floats in [0,1].
+ */
+static void
+z32f_x24s8_get_tile_rgba(const float *src,
+ unsigned w, unsigned h,
+ float *p,
+ unsigned dst_stride)
+{
+ unsigned i, j;
+
+ for (i = 0; i < h; i++) {
+ float *pRow = p;
+ for (j = 0; j < w; j++, pRow += 4) {
+ pRow[0] =
+ pRow[1] =
+ pRow[2] =
+ pRow[3] = *src;
+ src += 2;
+ }
+ p += dst_stride;
+ }
+}
+
void
pipe_tile_raw_to_rgba(enum pipe_format format,
@@ -352,6 +378,9 @@ pipe_tile_raw_to_rgba(enum pipe_format format,
case PIPE_FORMAT_Z32_FLOAT:
z32f_get_tile_rgba((float *) src, w, h, dst, dst_stride);
break;
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+ z32f_x24s8_get_tile_rgba((float *) src, w, h, dst, dst_stride);
+ break;
default:
util_format_read_4f(format,
dst, dst_stride * sizeof(float),
@@ -445,6 +474,12 @@ pipe_put_tile_rgba_format(struct pipe_context *pipe,
case PIPE_FORMAT_X8Z24_UNORM:
/*z24s8_put_tile_rgba((unsigned *) packed, w, h, p, src_stride);*/
break;
+ case PIPE_FORMAT_Z32_FLOAT:
+ /*z32f_put_tile_rgba((unsigned *) packed, w, h, p, src_stride);*/
+ break;
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+ /*z32f_s8x24_put_tile_rgba((unsigned *) packed, w, h, p, src_stride);*/
+ break;
default:
util_format_write_4f(format,
p, src_stride * sizeof(float),
diff --git a/src/gallium/auxiliary/util/u_upload_mgr.c b/src/gallium/auxiliary/util/u_upload_mgr.c
index e50db6d67fe..71fe53e3a27 100644
--- a/src/gallium/auxiliary/util/u_upload_mgr.c
+++ b/src/gallium/auxiliary/util/u_upload_mgr.c
@@ -257,7 +257,7 @@ enum pipe_error u_upload_buffer( struct u_upload_mgr *upload,
ret = u_upload_data( upload,
min_out_offset,
size,
- map,
+ map + offset,
out_offset,
outbuf, flushed );
diff --git a/src/gallium/drivers/i915/i915_context.c b/src/gallium/drivers/i915/i915_context.c
index 28ff40a2328..1b30309bb58 100644
--- a/src/gallium/drivers/i915/i915_context.c
+++ b/src/gallium/drivers/i915/i915_context.c
@@ -99,11 +99,11 @@ static void i915_destroy(struct pipe_context *pipe)
struct i915_context *i915 = i915_context(pipe);
int i;
- draw_destroy(i915->draw);
-
if (i915->blitter)
util_blitter_destroy(i915->blitter);
+ draw_destroy(i915->draw);
+
if(i915->batch)
i915->iws->batchbuffer_destroy(i915->batch);
diff --git a/src/gallium/drivers/nvfx/nvfx_screen.c b/src/gallium/drivers/nvfx/nvfx_screen.c
index 7a013a916b9..8569b5a190b 100644
--- a/src/gallium/drivers/nvfx/nvfx_screen.c
+++ b/src/gallium/drivers/nvfx/nvfx_screen.c
@@ -33,6 +33,9 @@ nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return 1;
case PIPE_CAP_GLSL:
return 1;
+ case PIPE_CAP_SM3:
+ /* TODO: >= nv4x support Shader Model 3.0 */
+ return 0;
case PIPE_CAP_ANISOTROPIC_FILTER:
return 1;
case PIPE_CAP_POINT_SPRITE:
diff --git a/src/gallium/drivers/r600/eg_asm.c b/src/gallium/drivers/r600/eg_asm.c
index fb0b0f104bf..c95872b0809 100644
--- a/src/gallium/drivers/r600/eg_asm.c
+++ b/src/gallium/drivers/r600/eg_asm.c
@@ -69,7 +69,7 @@ int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
S_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(cf->output.swizzle_w) |
S_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(cf->output.barrier) |
S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(cf->output.inst);
- if (bc->chiprev == CHIPREV_EVERGREEN) /* no EOP on cayman */
+ if (bc->chip_class == EVERGREEN) /* no EOP on cayman */
bc->bytecode[id] |= S_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(cf->output.end_of_program);
id++;
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 887f52e67db..4605c833dea 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -510,11 +510,11 @@ static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
if (R600_BIG_ENDIAN) {
switch(colorformat) {
case V_028C70_COLOR_4_4:
- return(ENDIAN_NONE);
+ return ENDIAN_NONE;
/* 8-bit buffers. */
case V_028C70_COLOR_8:
- return(ENDIAN_NONE);
+ return ENDIAN_NONE;
/* 16-bit buffers. */
case V_028C70_COLOR_5_6_5:
@@ -522,7 +522,7 @@ static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
case V_028C70_COLOR_4_4_4_4:
case V_028C70_COLOR_16:
case V_028C70_COLOR_8_8:
- return(ENDIAN_8IN16);
+ return ENDIAN_8IN16;
/* 32-bit buffers. */
case V_028C70_COLOR_8_8_8_8:
@@ -532,23 +532,23 @@ static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
case V_028C70_COLOR_32_FLOAT:
case V_028C70_COLOR_16_16_FLOAT:
case V_028C70_COLOR_16_16:
- return(ENDIAN_8IN32);
+ return ENDIAN_8IN32;
/* 64-bit buffers. */
case V_028C70_COLOR_16_16_16_16:
case V_028C70_COLOR_16_16_16_16_FLOAT:
- return(ENDIAN_8IN16);
+ return ENDIAN_8IN16;
case V_028C70_COLOR_32_32_FLOAT:
case V_028C70_COLOR_32_32:
- return(ENDIAN_8IN32);
+ return ENDIAN_8IN32;
/* 96-bit buffers. */
case V_028C70_COLOR_32_32_32_FLOAT:
/* 128-bit buffers. */
case V_028C70_COLOR_32_32_32_32_FLOAT:
case V_028C70_COLOR_32_32_32_32:
- return(ENDIAN_8IN32);
+ return ENDIAN_8IN32;
default:
return ENDIAN_NONE; /* Unsupported. */
}
@@ -657,13 +657,11 @@ static void *evergreen_create_blend_state(struct pipe_context *ctx,
u32 color_control, target_mask;
/* FIXME there is more then 8 framebuffer */
unsigned blend_cntl[8];
- enum radeon_family family;
if (blend == NULL) {
return NULL;
}
- family = r600_get_family(rctx->radeon);
rstate = &blend->rstate;
rstate->id = R600_PIPE_STATE_BLEND;
@@ -690,7 +688,7 @@ static void *evergreen_create_blend_state(struct pipe_context *ctx,
r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
color_control, 0xFFFFFFFD, NULL);
- if (family != CHIP_CAYMAN)
+ if (rctx->chip_class != CAYMAN)
r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
else {
r600_pipe_state_add_reg(rstate, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 0xFFFFFFFF, 0xFFFFFFFF, NULL);
@@ -827,9 +825,6 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx,
unsigned tmp;
unsigned prov_vtx = 1, polygon_dual_mode;
unsigned clip_rule;
- enum radeon_family family;
-
- family = r600_get_family(rctx->radeon);
if (rs == NULL) {
return NULL;
@@ -888,7 +883,7 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx,
tmp = (unsigned)state->line_width * 8;
r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
- if (family == CHIP_CAYMAN) {
+ if (rctx->chip_class == CAYMAN) {
r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
@@ -1447,14 +1442,11 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
u32 shader_mask, tl, br, target_mask;
- enum radeon_family family;
int tl_x, tl_y, br_x, br_y;
if (rstate == NULL)
return;
- family = r600_get_family(rctx->radeon);
-
evergreen_context_flush_dest_caches(&rctx->ctx);
rctx->ctx.num_dest_buffers = state->nr_cbufs;
@@ -1491,7 +1483,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
if (br_y == 0)
tl_y = 1;
/* cayman hw workaround */
- if (family == CHIP_CAYMAN) {
+ if (rctx->chip_class == CAYMAN) {
if (br_x == 1 && br_y == 1)
br_x = 2;
}
@@ -1535,7 +1527,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
shader_mask, 0xFFFFFFFF, NULL);
- if (family == CHIP_CAYMAN) {
+ if (rctx->chip_class == CAYMAN) {
r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
0x00000000, 0xFFFFFFFF, NULL);
} else {
@@ -1722,9 +1714,9 @@ void evergreen_init_config(struct r600_pipe_context *rctx)
enum radeon_family family;
unsigned tmp;
- family = r600_get_family(rctx->radeon);
+ family = rctx->family;
- if (family == CHIP_CAYMAN) {
+ if (rctx->chip_class == CAYMAN) {
cayman_init_config(rctx);
return;
}
@@ -2034,6 +2026,11 @@ void evergreen_init_config(struct r600_pipe_context *rctx)
tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL);
+ tmp = 0;
+ tmp |= S_008E2C_NUM_PS_LDS(0x1000);
+ tmp |= S_008E2C_NUM_LS_LDS(0x1000);
+ r600_pipe_state_add_reg(rstate, R_008E2C_SQ_LDS_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
+
r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL);
diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h
index d795f5757ed..96dbd4da91b 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -216,6 +216,13 @@
#define S_008C28_NUM_LS_STACK_ENTRIES(x) (((x) & 0xFFF) << 16)
#define G_008C28_NUM_LS_STACK_ENTRIES(x) (((x) >> 16) & 0xFFF)
#define C_008C28_NUM_LS_STACK_ENTRIES(x) 0xF000FFFF
+#define R_008E2C_SQ_LDS_RESOURCE_MGMT 0x00008E2C
+#define S_008E2C_NUM_PS_LDS(x) (((x) & 0xFFFF) << 0)
+#define G_008E2C_NUM_PS_LDS(x) (((x) >> 0) & 0xFFFF)
+#define C_008E2C_NUM_PS_LDS(x) 0x0000FFFF
+#define S_008E2C_NUM_LS_LDS(x) (((x) & 0xFFFF) << 16)
+#define G_008E2C_NUM_LS_LDS(x) (((x) >> 16) & 0xFFFF)
+#define C_008E2C_NUM_LS_LDS(x) 0xFFFF0000
#define R_008CF0_SQ_MS_FIFO_SIZES 0x00008CF0
#define S_008CF0_CACHE_FIFO_SIZE(x) (((x) & 0xFF) << 0)
diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
index 065f955ebcb..5fae2b00c8b 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -41,9 +41,9 @@ static inline unsigned int r600_bc_get_num_operands(struct r600_bc *bc, struct r
if(alu->is_op3)
return 3;
- switch (bc->chiprev) {
- case CHIPREV_R600:
- case CHIPREV_R700:
+ switch (bc->chip_class) {
+ case R600:
+ case R700:
switch (alu->inst) {
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
return 0;
@@ -93,8 +93,8 @@ static inline unsigned int r600_bc_get_num_operands(struct r600_bc *bc, struct r
"Need instruction operand number for 0x%x.\n", alu->inst);
}
break;
- case CHIPREV_EVERGREEN:
- case CHIPREV_CAYMAN:
+ case EVERGREEN:
+ case CAYMAN:
switch (alu->inst) {
case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP:
return 0;
@@ -195,48 +195,10 @@ static struct r600_bc_tex *r600_bc_tex(void)
return tex;
}
-int r600_bc_init(struct r600_bc *bc, enum radeon_family family)
+void r600_bc_init(struct r600_bc *bc, enum chip_class chip_class)
{
LIST_INITHEAD(&bc->cf);
- bc->family = family;
- switch (bc->family) {
- case CHIP_R600:
- case CHIP_RV610:
- case CHIP_RV630:
- case CHIP_RV670:
- case CHIP_RV620:
- case CHIP_RV635:
- case CHIP_RS780:
- case CHIP_RS880:
- bc->chiprev = CHIPREV_R600;
- break;
- case CHIP_RV770:
- case CHIP_RV730:
- case CHIP_RV710:
- case CHIP_RV740:
- bc->chiprev = CHIPREV_R700;
- break;
- case CHIP_CEDAR:
- case CHIP_REDWOOD:
- case CHIP_JUNIPER:
- case CHIP_CYPRESS:
- case CHIP_HEMLOCK:
- case CHIP_PALM:
- case CHIP_SUMO:
- case CHIP_SUMO2:
- case CHIP_BARTS:
- case CHIP_TURKS:
- case CHIP_CAICOS:
- bc->chiprev = CHIPREV_EVERGREEN;
- break;
- case CHIP_CAYMAN:
- bc->chiprev = CHIPREV_CAYMAN;
- break;
- default:
- R600_ERR("unknown family %d\n", bc->family);
- return -EINVAL;
- }
- return 0;
+ bc->chip_class = chip_class;
}
static int r600_bc_add_cf(struct r600_bc *bc)
@@ -301,9 +263,9 @@ int r600_bc_add_output(struct r600_bc *bc, const struct r600_bc_output *output)
/* alu instructions that can ony exits once per group */
static int is_alu_once_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
{
- switch (bc->chiprev) {
- case CHIPREV_R600:
- case CHIPREV_R700:
+ switch (bc->chip_class) {
+ case R600:
+ case R700:
return !alu->is_op3 && (
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGT ||
@@ -339,8 +301,8 @@ static int is_alu_once_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_PUSH_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLT_PUSH_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETLE_PUSH_INT);
- case CHIPREV_EVERGREEN:
- case CHIPREV_CAYMAN:
+ case EVERGREEN:
+ case CAYMAN:
default:
return !alu->is_op3 && (
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLE ||
@@ -382,16 +344,16 @@ static int is_alu_once_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
static int is_alu_reduction_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
{
- switch (bc->chiprev) {
- case CHIPREV_R600:
- case CHIPREV_R700:
+ switch (bc->chip_class) {
+ case R600:
+ case R700:
return !alu->is_op3 && (
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4 ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX4);
- case CHIPREV_EVERGREEN:
- case CHIPREV_CAYMAN:
+ case EVERGREEN:
+ case CAYMAN:
default:
return !alu->is_op3 && (
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE ||
@@ -403,13 +365,13 @@ static int is_alu_reduction_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
static int is_alu_cube_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
{
- switch (bc->chiprev) {
- case CHIPREV_R600:
- case CHIPREV_R700:
+ switch (bc->chip_class) {
+ case R600:
+ case R700:
return !alu->is_op3 &&
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
- case CHIPREV_EVERGREEN:
- case CHIPREV_CAYMAN:
+ case EVERGREEN:
+ case CAYMAN:
default:
return !alu->is_op3 &&
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE;
@@ -418,15 +380,15 @@ static int is_alu_cube_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
static int is_alu_mova_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
{
- switch (bc->chiprev) {
- case CHIPREV_R600:
- case CHIPREV_R700:
+ switch (bc->chip_class) {
+ case R600:
+ case R700:
return !alu->is_op3 && (
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
- case CHIPREV_EVERGREEN:
- case CHIPREV_CAYMAN:
+ case EVERGREEN:
+ case CAYMAN:
default:
return !alu->is_op3 && (
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
@@ -438,16 +400,16 @@ static int is_alu_vec_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
{
return is_alu_reduction_inst(bc, alu) ||
is_alu_mova_inst(bc, alu) ||
- (bc->chiprev == CHIPREV_EVERGREEN &&
+ (bc->chip_class == EVERGREEN &&
alu->inst == EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT_FLOOR);
}
/* alu instructions that can only execute on the trans unit */
static int is_alu_trans_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
{
- switch (bc->chiprev) {
- case CHIPREV_R600:
- case CHIPREV_R700:
+ switch (bc->chip_class) {
+ case R600:
+ case R700:
if (!alu->is_op3)
return alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_ASHR_INT ||
alu->inst == V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLT_TO_INT ||
@@ -478,8 +440,8 @@ static int is_alu_trans_unit_inst(struct r600_bc *bc, struct r600_bc_alu *alu)
alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_D2 ||
alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M2 ||
alu->inst == V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT_M4;
- case CHIPREV_EVERGREEN:
- case CHIPREV_CAYMAN:
+ case EVERGREEN:
+ case CAYMAN:
default:
if (!alu->is_op3)
/* Note that FLT_TO_INT_* instructions are vector-only instructions
@@ -525,7 +487,7 @@ static int assign_alu_units(struct r600_bc *bc, struct r600_bc_alu *alu_first,
{
struct r600_bc_alu *alu;
unsigned i, chan, trans;
- int max_slots = bc->chiprev == CHIPREV_CAYMAN ? 4 : 5;
+ int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
for (i = 0; i < max_slots; i++)
assignment[i] = NULL;
@@ -612,7 +574,7 @@ static int reserve_gpr(struct alu_bank_swizzle *bs, unsigned sel, unsigned chan,
static int reserve_cfile(struct r600_bc *bc, struct alu_bank_swizzle *bs, unsigned sel, unsigned chan)
{
int res, num_res = 4;
- if (bc->chiprev >= CHIPREV_R700) {
+ if (bc->chip_class >= R700) {
num_res = 2;
chan /= 2;
}
@@ -733,8 +695,8 @@ static int check_and_set_bank_swizzle(struct r600_bc *bc,
struct alu_bank_swizzle bs;
int bank_swizzle[5];
int i, r = 0, forced = 0;
- boolean scalar_only = bc->chiprev == CHIPREV_CAYMAN ? false : true;
- int max_slots = bc->chiprev == CHIPREV_CAYMAN ? 4 : 5;
+ boolean scalar_only = bc->chip_class == CAYMAN ? false : true;
+ int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
for (i = 0; i < max_slots; i++) {
if (slots[i] && slots[i]->bank_swizzle_force) {
@@ -806,7 +768,7 @@ static int replace_gpr_with_pv_ps(struct r600_bc *bc,
struct r600_bc_alu *prev[5];
int gpr[5], chan[5];
int i, j, r, src, num_src;
- int max_slots = bc->chiprev == CHIPREV_CAYMAN ? 4 : 5;
+ int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
r = assign_alu_units(bc, alu_prev, prev);
if (r)
@@ -834,7 +796,7 @@ static int replace_gpr_with_pv_ps(struct r600_bc *bc,
if (!is_gpr(alu->src[src].sel) || alu->src[src].rel)
continue;
- if (bc->chiprev < CHIPREV_CAYMAN) {
+ if (bc->chip_class < CAYMAN) {
if (alu->src[src].sel == gpr[4] &&
alu->src[src].chan == chan[4]) {
alu->src[src].sel = V_SQ_ALU_SRC_PS;
@@ -948,7 +910,7 @@ static int merge_inst_groups(struct r600_bc *bc, struct r600_bc_alu *slots[5],
int i, j, r, src, num_src;
int num_once_inst = 0;
int have_mova = 0, have_rel = 0;
- int max_slots = bc->chiprev == CHIPREV_CAYMAN ? 4 : 5;
+ int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
r = assign_alu_units(bc, alu_prev, prev);
if (r)
@@ -1252,7 +1214,7 @@ int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu, int
uint32_t literal[4];
unsigned nliteral;
struct r600_bc_alu *slots[5];
- int max_slots = bc->chiprev == CHIPREV_CAYMAN ? 4 : 5;
+ int max_slots = bc->chip_class == CAYMAN ? 4 : 5;
r = assign_alu_units(bc, bc->cf_last->curr_bs_head, slots);
if (r)
return r;
@@ -1302,26 +1264,26 @@ int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu)
static unsigned r600_bc_num_tex_and_vtx_instructions(const struct r600_bc *bc)
{
- switch (bc->chiprev) {
- case CHIPREV_R600:
+ switch (bc->chip_class) {
+ case R600:
return 8;
- case CHIPREV_R700:
+ case R700:
return 16;
- case CHIPREV_EVERGREEN:
- case CHIPREV_CAYMAN:
+ case EVERGREEN:
+ case CAYMAN:
return 64;
default:
- R600_ERR("Unknown chiprev %d.\n", bc->chiprev);
+ R600_ERR("Unknown chip class %d.\n", bc->chip_class);
return 8;
}
}
static inline boolean last_inst_was_vtx_fetch(struct r600_bc *bc)
{
- if (bc->chiprev == CHIPREV_CAYMAN) {
+ if (bc->chip_class == CAYMAN) {
if (bc->cf_last->inst != CM_V_SQ_CF_WORD1_SQ_CF_INST_TC)
return TRUE;
} else {
@@ -1350,7 +1312,7 @@ int r600_bc_add_vtx(struct r600_bc *bc, const struct r600_bc_vtx *vtx)
free(nvtx);
return r;
}
- if (bc->chiprev == CHIPREV_CAYMAN)
+ if (bc->chip_class == CAYMAN)
bc->cf_last->inst = CM_V_SQ_CF_WORD1_SQ_CF_INST_TC;
else
bc->cf_last->inst = V_SQ_CF_WORD1_SQ_CF_INST_VTX;
@@ -1438,7 +1400,7 @@ static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsign
S_SQ_VTX_WORD0_FETCH_TYPE(vtx->fetch_type) |
S_SQ_VTX_WORD0_SRC_GPR(vtx->src_gpr) |
S_SQ_VTX_WORD0_SRC_SEL_X(vtx->src_sel_x);
- if (bc->chiprev < CHIPREV_CAYMAN)
+ if (bc->chip_class < CAYMAN)
bc->bytecode[id] |= S_SQ_VTX_WORD0_MEGA_FETCH_COUNT(vtx->mega_fetch_count);
id++;
bc->bytecode[id++] = S_SQ_VTX_WORD1_DST_SEL_X(vtx->dst_sel_x) |
@@ -1453,7 +1415,7 @@ static int r600_bc_vtx_build(struct r600_bc *bc, struct r600_bc_vtx *vtx, unsign
S_SQ_VTX_WORD1_GPR_DST_GPR(vtx->dst_gpr);
bc->bytecode[id] = S_SQ_VTX_WORD2_OFFSET(vtx->offset)|
S_SQ_VTX_WORD2_ENDIAN_SWAP(vtx->endian);
- if (bc->chiprev < CHIPREV_CAYMAN)
+ if (bc->chip_class < CAYMAN)
bc->bytecode[id] |= S_SQ_VTX_WORD2_MEGA_FETCH(1);
id++;
bc->bytecode[id++] = 0;
@@ -1560,13 +1522,13 @@ static int r600_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
S_SQ_CF_ALU_WORD1_KCACHE_ADDR0(cf->kcache[0].addr) |
S_SQ_CF_ALU_WORD1_KCACHE_ADDR1(cf->kcache[1].addr) |
S_SQ_CF_ALU_WORD1_BARRIER(1) |
- S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chiprev == CHIPREV_R600 ? cf->r6xx_uses_waterfall : 0) |
+ S_SQ_CF_ALU_WORD1_USES_WATERFALL(bc->chip_class == R600 ? cf->r6xx_uses_waterfall : 0) |
S_SQ_CF_ALU_WORD1_COUNT((cf->ndw / 2) - 1);
break;
case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
- if (bc->chiprev == CHIPREV_R700)
+ if (bc->chip_class == R700)
r700_bc_cf_vtx_build(&bc->bytecode[id], cf);
else
r600_bc_cf_vtx_build(&bc->bytecode[id], cf);
@@ -1673,7 +1635,7 @@ int r600_bc_build(struct r600_bc *bc)
return -ENOMEM;
LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
addr = cf->addr;
- if (bc->chiprev >= CHIPREV_EVERGREEN)
+ if (bc->chip_class >= EVERGREEN)
r = eg_bc_cf_build(bc, cf);
else
r = r600_bc_cf_build(bc, cf);
@@ -1691,17 +1653,17 @@ int r600_bc_build(struct r600_bc *bc)
if (r)
return r;
r600_bc_alu_adjust_literals(bc, alu, literal, nliteral);
- switch(bc->chiprev) {
- case CHIPREV_R600:
+ switch(bc->chip_class) {
+ case R600:
r = r600_bc_alu_build(bc, alu, addr);
break;
- case CHIPREV_R700:
- case CHIPREV_EVERGREEN: /* eg alu is same encoding as r700 */
- case CHIPREV_CAYMAN: /* eg alu is same encoding as r700 */
+ case R700:
+ case EVERGREEN: /* eg alu is same encoding as r700 */
+ case CAYMAN: /* eg alu is same encoding as r700 */
r = r700_bc_alu_build(bc, alu, addr);
break;
default:
- R600_ERR("unknown family %d\n", bc->family);
+ R600_ERR("unknown chip class %d.\n", bc->chip_class);
return -EINVAL;
}
if (r)
@@ -1726,7 +1688,7 @@ int r600_bc_build(struct r600_bc *bc)
}
break;
case V_SQ_CF_WORD1_SQ_CF_INST_TEX:
- if (bc->chiprev == CHIPREV_CAYMAN) {
+ if (bc->chip_class == CAYMAN) {
LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
r = r600_bc_vtx_build(bc, vtx, addr);
if (r)
@@ -1812,17 +1774,17 @@ void r600_bc_dump(struct r600_bc *bc)
unsigned nliteral;
char chip = '6';
- switch (bc->chiprev) {
- case 1:
+ switch (bc->chip_class) {
+ case R700:
chip = '7';
break;
- case 2:
+ case EVERGREEN:
chip = 'E';
break;
- case 3:
+ case CAYMAN:
chip = 'C';
break;
- case 0:
+ case R600:
default:
chip = '6';
break;
@@ -1993,7 +1955,7 @@ void r600_bc_dump(struct r600_bc *bc)
fprintf(stderr, "%04d %08X ", id, bc->bytecode[id]);
fprintf(stderr, "SRC(GPR:%d ", vtx->src_gpr);
fprintf(stderr, "SEL_X:%d) ", vtx->src_sel_x);
- if (bc->chiprev < CHIPREV_CAYMAN)
+ if (bc->chip_class < CAYMAN)
fprintf(stderr, "MEGA_FETCH_COUNT:%d ", vtx->mega_fetch_count);
else
fprintf(stderr, "SEL_Y:%d) ", 0);
@@ -2162,7 +2124,7 @@ int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, stru
struct r600_bc_vtx vtx;
struct pipe_vertex_element *elements = ve->elements;
const struct util_format_description *desc;
- unsigned fetch_resource_start = rctx->family >= CHIP_CEDAR ? 0 : 160;
+ unsigned fetch_resource_start = rctx->chip_class >= EVERGREEN ? 0 : 160;
unsigned format, num_format, format_comp, endian;
u32 *bytecode;
int i, r;
@@ -2180,9 +2142,7 @@ int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, stru
}
memset(&bc, 0, sizeof(bc));
- r = r600_bc_init(&bc, r600_get_family(rctx->radeon));
- if (r)
- return r;
+ r600_bc_init(&bc, rctx->chip_class);
for (i = 0; i < ve->count; i++) {
if (elements[i].instance_divisor > 1) {
@@ -2287,7 +2247,7 @@ int r600_vertex_elements_build_fetch_shader(struct r600_pipe_context *rctx, stru
r600_bo_unmap(rctx->radeon, ve->fetch_shader);
r600_bc_clear(&bc);
- if (rctx->family >= CHIP_CEDAR)
+ if (rctx->chip_class >= EVERGREEN)
evergreen_fetch_shader(&rctx->context, ve);
else
r600_fetch_shader(&rctx->context, ve);
diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h
index 540f45bbd06..cbdaacf7178 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -171,8 +171,7 @@ struct r600_cf_callstack {
};
struct r600_bc {
- enum radeon_family family;
- int chiprev; /* 0 - r600, 1 - r700, 2 - evergreen */
+ enum chip_class chip_class;
int type;
struct list_head cf;
struct r600_bc_cf *cf_last;
@@ -193,7 +192,7 @@ struct r600_bc {
int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf);
/* r600_asm.c */
-int r600_bc_init(struct r600_bc *bc, enum radeon_family family);
+void r600_bc_init(struct r600_bc *bc, enum chip_class chip_class);
void r600_bc_clear(struct r600_bc *bc);
int r600_bc_add_alu(struct r600_bc *bc, const struct r600_bc_alu *alu);
int r600_bc_add_vtx(struct r600_bc *bc, const struct r600_bc_vtx *vtx);
diff --git a/src/gallium/drivers/r600/r600_opcodes.h b/src/gallium/drivers/r600/r600_opcodes.h
index 184f32c9960..7ae091ea5cd 100644
--- a/src/gallium/drivers/r600/r600_opcodes.h
+++ b/src/gallium/drivers/r600/r600_opcodes.h
@@ -409,14 +409,8 @@
#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_EXPORT_COMBINED 0x0000005B
#define EG_V_SQ_CF_ALLOC_EXPORT_WORD1_SQ_CF_INST_MEM_RAT_COMBINED_CACHELESS 0x0000005C
+#define BC_INST(bc, x) ((bc)->chip_class >= EVERGREEN ? EG_##x : x)
-#define CHIPREV_R600 0
-#define CHIPREV_R700 1
-#define CHIPREV_EVERGREEN 2
-#define CHIPREV_CAYMAN 3
-
-#define BC_INST(bc, x) ((bc)->chiprev >= CHIPREV_EVERGREEN ? EG_##x : x)
-
-#define CTX_INST(x) (ctx->bc->chiprev >= CHIPREV_EVERGREEN ? EG_##x : x)
+#define CTX_INST(x) (ctx->bc->chip_class >= EVERGREEN ? EG_##x : x)
#endif
diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index d512268f63f..a3df4f571a0 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -194,7 +194,6 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
{
struct r600_pipe_context *rctx = CALLOC_STRUCT(r600_pipe_context);
struct r600_screen* rscreen = (struct r600_screen *)screen;
- enum chip_class class;
if (rctx == NULL)
return NULL;
@@ -211,6 +210,7 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
rctx->screen = rscreen;
rctx->radeon = rscreen->radeon;
rctx->family = r600_get_family(rctx->radeon);
+ rctx->chip_class = r600_get_family_class(rctx->radeon);
rctx->fences.bo = NULL;
rctx->fences.data = NULL;
@@ -224,47 +224,29 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
r600_init_surface_functions(rctx);
rctx->context.draw_vbo = r600_draw_vbo;
- switch (r600_get_family(rctx->radeon)) {
- case CHIP_R600:
- case CHIP_RV610:
- case CHIP_RV630:
- case CHIP_RV670:
- case CHIP_RV620:
- case CHIP_RV635:
- case CHIP_RS780:
- case CHIP_RS880:
- case CHIP_RV770:
- case CHIP_RV730:
- case CHIP_RV710:
- case CHIP_RV740:
+ switch (rctx->chip_class) {
+ case R600:
+ case R700:
r600_init_state_functions(rctx);
if (r600_context_init(&rctx->ctx, rctx->radeon)) {
r600_destroy_context(&rctx->context);
return NULL;
}
r600_init_config(rctx);
+ rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
break;
- case CHIP_CEDAR:
- case CHIP_REDWOOD:
- case CHIP_JUNIPER:
- case CHIP_CYPRESS:
- case CHIP_HEMLOCK:
- case CHIP_PALM:
- case CHIP_SUMO:
- case CHIP_SUMO2:
- case CHIP_BARTS:
- case CHIP_TURKS:
- case CHIP_CAICOS:
- case CHIP_CAYMAN:
+ case EVERGREEN:
+ case CAYMAN:
evergreen_init_state_functions(rctx);
if (evergreen_context_init(&rctx->ctx, rctx->radeon)) {
r600_destroy_context(&rctx->context);
return NULL;
}
evergreen_init_config(rctx);
+ rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
break;
default:
- R600_ERR("unsupported family %d\n", r600_get_family(rctx->radeon));
+ R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
r600_destroy_context(&rctx->context);
return NULL;
}
@@ -289,12 +271,6 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
return NULL;
}
- class = r600_get_family_class(rctx->radeon);
- if (class == R600 || class == R700)
- rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
- else
- rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
-
return &rctx->context;
}
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index c58c2f77743..6f399ed43b0 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -175,7 +175,8 @@ struct r600_pipe_fences {
struct r600_pipe_context {
struct pipe_context context;
struct blitter_context *blitter;
- unsigned family;
+ enum radeon_family family;
+ enum chip_class chip_class;
void *custom_dsa_flush;
struct r600_screen *screen;
struct radeon *radeon;
diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index f83d7079b29..3e21ad1fdc6 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -99,14 +99,14 @@ static int r600_pipe_shader(struct pipe_context *ctx, struct r600_pipe_shader *s
/* build state */
switch (rshader->processor_type) {
case TGSI_PROCESSOR_VERTEX:
- if (rshader->family >= CHIP_CEDAR) {
+ if (rctx->chip_class >= EVERGREEN) {
evergreen_pipe_shader_vs(ctx, shader);
} else {
r600_pipe_shader_vs(ctx, shader);
}
break;
case TGSI_PROCESSOR_FRAGMENT:
- if (rshader->family >= CHIP_CEDAR) {
+ if (rctx->chip_class >= EVERGREEN) {
evergreen_pipe_shader_ps(ctx, shader);
} else {
r600_pipe_shader_ps(ctx, shader);
@@ -135,7 +135,6 @@ int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *s
fprintf(stderr, "--------------------------------------------------------------\n");
tgsi_dump(shader->tokens, 0);
}
- shader->shader.family = r600_get_family(rctx->radeon);
r = r600_shader_from_tgsi(rctx, shader);
if (r) {
R600_ERR("translation from TGSI failed !\n");
@@ -317,7 +316,7 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
ctx->shader->input[i].interpolate = d->Declaration.Interpolate;
ctx->shader->input[i].centroid = d->Declaration.Centroid;
ctx->shader->input[i].gpr = ctx->file_offset[TGSI_FILE_INPUT] + i;
- if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chiprev >= CHIPREV_EVERGREEN) {
+ if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->bc->chip_class >= EVERGREEN) {
/* turn input into interpolate on EG */
if (ctx->shader->input[i].name != TGSI_SEMANTIC_POSITION) {
if (ctx->shader->input[i].interpolate > 0) {
@@ -610,9 +609,7 @@ static int r600_shader_from_tgsi(struct r600_pipe_context * rctx, struct r600_pi
ctx.bc = &shader->bc;
ctx.shader = shader;
- r = r600_bc_init(ctx.bc, shader->family);
- if (r)
- return r;
+ r600_bc_init(ctx.bc, rctx->chip_class);
ctx.tokens = tokens;
tgsi_scan_shader(tokens, &ctx.info);
tgsi_parse_init(&ctx.parse, tokens);
@@ -651,13 +648,13 @@ static int r600_shader_from_tgsi(struct r600_pipe_context * rctx, struct r600_pi
}
if (ctx.type == TGSI_PROCESSOR_VERTEX) {
ctx.file_offset[TGSI_FILE_INPUT] = 1;
- if (ctx.bc->chiprev >= CHIPREV_EVERGREEN) {
+ if (ctx.bc->chip_class >= EVERGREEN) {
r600_bc_add_cfinst(ctx.bc, EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
} else {
r600_bc_add_cfinst(ctx.bc, V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS);
}
}
- if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chiprev >= CHIPREV_EVERGREEN) {
+ if (ctx.type == TGSI_PROCESSOR_FRAGMENT && ctx.bc->chip_class >= EVERGREEN) {
ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
}
ctx.file_offset[TGSI_FILE_OUTPUT] = ctx.file_offset[TGSI_FILE_INPUT] +
@@ -711,9 +708,9 @@ static int r600_shader_from_tgsi(struct r600_pipe_context * rctx, struct r600_pi
goto out_err;
if ((r = tgsi_split_literal_constant(&ctx)))
goto out_err;
- if (ctx.bc->chiprev == CHIPREV_CAYMAN)
+ if (ctx.bc->chip_class == CAYMAN)
ctx.inst_info = &cm_shader_tgsi_instruction[opcode];
- else if (ctx.bc->chiprev >= CHIPREV_EVERGREEN)
+ else if (ctx.bc->chip_class >= EVERGREEN)
ctx.inst_info = &eg_shader_tgsi_instruction[opcode];
else
ctx.inst_info = &r600_shader_tgsi_instruction[opcode];
@@ -802,7 +799,7 @@ static int r600_shader_from_tgsi(struct r600_pipe_context * rctx, struct r600_pi
if (shader->output[i].name == TGSI_SEMANTIC_COLOR) {
output[i + j].array_base = shader->output[i].sid;
output[i + j].type = V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;
- if (shader->fs_write_all && (shader->family >= CHIP_CEDAR)) {
+ if (shader->fs_write_all && (rctx->chip_class >= EVERGREEN)) {
for (j = 1; j < shader->nr_cbufs; j++) {
memset(&output[i + j], 0, sizeof(struct r600_bc_output));
output[i + j].gpr = shader->output[i].gpr;
@@ -886,7 +883,7 @@ static int r600_shader_from_tgsi(struct r600_pipe_context * rctx, struct r600_pi
}
/* set export done on last export of each type */
for (i = noutput - 1, output_done = 0; i >= 0; i--) {
- if (ctx.bc->chiprev < CHIPREV_CAYMAN) {
+ if (ctx.bc->chip_class < CAYMAN) {
if (i == (noutput - 1)) {
output[i].end_of_program = 1;
}
@@ -903,7 +900,7 @@ static int r600_shader_from_tgsi(struct r600_pipe_context * rctx, struct r600_pi
goto out_err;
}
/* add program end */
- if (ctx.bc->chiprev == CHIPREV_CAYMAN)
+ if (ctx.bc->chip_class == CAYMAN)
cm_bc_add_cf_end(ctx.bc);
free(ctx.literals);
@@ -939,6 +936,17 @@ static void r600_bc_src(struct r600_bc_alu_src *bc_src,
bc_src->value = shader_src->value[bc_src->chan];
}
+static void r600_bc_src_set_abs(struct r600_bc_alu_src *bc_src)
+{
+ bc_src->abs = 1;
+ bc_src->neg = 0;
+}
+
+static void r600_bc_src_toggle_neg(struct r600_bc_alu_src *bc_src)
+{
+ bc_src->neg = !bc_src->neg;
+}
+
static void tgsi_dst(struct r600_shader_ctx *ctx,
const struct tgsi_full_dst_register *tgsi_dst,
unsigned swizzle,
@@ -995,12 +1003,10 @@ static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
/* handle some special cases */
switch (ctx->inst_info->tgsi_opcode) {
case TGSI_OPCODE_SUB:
- alu.src[1].neg = 1;
+ r600_bc_src_toggle_neg(&alu.src[1]);
break;
case TGSI_OPCODE_ABS:
- alu.src[0].abs = 1;
- if (alu.src[0].neg)
- alu.src[0].neg = 0;
+ r600_bc_src_set_abs(&alu.src[0]);
break;
default:
break;
@@ -1114,7 +1120,7 @@ static int tgsi_setup_trig(struct r600_shader_ctx *ctx)
alu.src[2].sel = V_SQ_ALU_SRC_LITERAL;
alu.src[2].chan = 0;
- if (ctx->bc->chiprev == CHIPREV_R600) {
+ if (ctx->bc->chip_class == R600) {
alu.src[1].value = *(uint32_t *)&double_pi;
alu.src[2].value = *(uint32_t *)&neg_pi;
} else {
@@ -1221,7 +1227,7 @@ static int tgsi_scs(struct r600_shader_ctx *ctx)
/* dst.x = COS */
if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
- if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+ if (ctx->bc->chip_class == CAYMAN) {
for (i = 0 ; i < 3; i++) {
memset(&alu, 0, sizeof(struct r600_bc_alu));
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS);
@@ -1255,7 +1261,7 @@ static int tgsi_scs(struct r600_shader_ctx *ctx)
/* dst.y = SIN */
if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
- if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+ if (ctx->bc->chip_class == CAYMAN) {
for (i = 0 ; i < 3; i++) {
memset(&alu, 0, sizeof(struct r600_bc_alu));
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN);
@@ -1364,19 +1370,37 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
struct r600_bc_alu alu;
int r;
+ /* tmp.x = max(src.y, 0.0) */
+ memset(&alu, 0, sizeof(struct r600_bc_alu));
+ alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX);
+ r600_bc_src(&alu.src[0], &ctx->src[0], 1);
+ alu.src[1].sel = V_SQ_ALU_SRC_0; /*0.0*/
+ alu.src[1].chan = 1;
+
+ alu.dst.sel = ctx->temp_reg;
+ alu.dst.chan = 0;
+ alu.dst.write = 1;
+
+ alu.last = 1;
+ r = r600_bc_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+
if (inst->Dst[0].Register.WriteMask & (1 << 2))
{
int chan;
int sel;
int i;
- if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+ if (ctx->bc->chip_class == CAYMAN) {
for (i = 0; i < 3; i++) {
- /* dst.z = log(src.y) */
+ /* tmp.z = log(tmp.x) */
memset(&alu, 0, sizeof(struct r600_bc_alu));
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
- r600_bc_src(&alu.src[0], &ctx->src[0], 1);
- tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
+ alu.src[0].sel = ctx->temp_reg;
+ alu.src[0].chan = 0;
+ alu.dst.sel = ctx->temp_reg;
+ alu.dst.chan = i;
if (i == 2) {
alu.dst.write = 1;
alu.last = 1;
@@ -1388,10 +1412,11 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
return r;
}
} else {
- /* dst.z = log(src.y) */
+ /* tmp.z = log(tmp.x) */
memset(&alu, 0, sizeof(struct r600_bc_alu));
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_CLAMPED);
- r600_bc_src(&alu.src[0], &ctx->src[0], 1);
+ alu.src[0].sel = ctx->temp_reg;
+ alu.src[0].chan = 0;
alu.dst.sel = ctx->temp_reg;
alu.dst.chan = 2;
alu.dst.write = 1;
@@ -1404,13 +1429,12 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
chan = alu.dst.chan;
sel = alu.dst.sel;
- /* tmp.x = amd MUL_LIT(src.w, dst.z, src.x ) */
+ /* tmp.x = amd MUL_LIT(tmp.z, src.w, src.x ) */
memset(&alu, 0, sizeof(struct r600_bc_alu));
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP3_SQ_OP3_INST_MUL_LIT);
- r600_bc_src(&alu.src[0], &ctx->src[0], 3);
- alu.src[1].sel = sel;
- alu.src[1].chan = chan;
-
+ alu.src[0].sel = sel;
+ alu.src[0].chan = chan;
+ r600_bc_src(&alu.src[1], &ctx->src[0], 3);
r600_bc_src(&alu.src[2], &ctx->src[0], 0);
alu.dst.sel = ctx->temp_reg;
alu.dst.chan = 0;
@@ -1421,7 +1445,7 @@ static int tgsi_lit(struct r600_shader_ctx *ctx)
if (r)
return r;
- if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+ if (ctx->bc->chip_class == CAYMAN) {
for (i = 0; i < 3; i++) {
/* dst.z = exp(tmp.x) */
memset(&alu, 0, sizeof(struct r600_bc_alu));
@@ -1506,7 +1530,7 @@ static int tgsi_rsq(struct r600_shader_ctx *ctx)
for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
r600_bc_src(&alu.src[i], &ctx->src[i], 0);
- alu.src[i].abs = 1;
+ r600_bc_src_set_abs(&alu.src[i]);
}
alu.dst.sel = ctx->temp_reg;
alu.dst.write = 1;
@@ -1898,7 +1922,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
} else if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
int out_chan;
/* Add perspective divide */
- if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+ if (ctx->bc->chip_class == CAYMAN) {
out_chan = 2;
for (i = 0; i < 3; i++) {
memset(&alu, 0, sizeof(struct r600_bc_alu));
@@ -1980,7 +2004,7 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
}
/* tmp1.z = RCP_e(|tmp1.z|) */
- if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+ if (ctx->bc->chip_class == CAYMAN) {
for (i = 0; i < 3; i++) {
memset(&alu, 0, sizeof(struct r600_bc_alu));
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
@@ -2192,7 +2216,7 @@ static int tgsi_lrp(struct r600_shader_ctx *ctx)
alu.src[0].sel = V_SQ_ALU_SRC_1;
alu.src[0].chan = 0;
r600_bc_src(&alu.src[1], &ctx->src[0], i);
- alu.src[1].neg = 1;
+ r600_bc_src_toggle_neg(&alu.src[1]);
alu.dst.sel = ctx->temp_reg;
alu.dst.chan = i;
if (i == lasti) {
@@ -2373,7 +2397,7 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)
if (r)
return r;
- if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+ if (ctx->bc->chip_class == CAYMAN) {
for (i = 0; i < 3; i++) {
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
alu.src[0].sel = ctx->temp_reg;
@@ -2429,7 +2453,7 @@ static int tgsi_exp(struct r600_shader_ctx *ctx)
/* result.z = RoughApprox2ToX(tmp);*/
if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
- if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+ if (ctx->bc->chip_class == CAYMAN) {
for (i = 0; i < 3; i++) {
memset(&alu, 0, sizeof(struct r600_bc_alu));
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
@@ -2489,14 +2513,15 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
int r;
int i;
- /* result.x = floor(log2(src)); */
+ /* result.x = floor(log2(|src|)); */
if (inst->Dst[0].Register.WriteMask & 1) {
- if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+ if (ctx->bc->chip_class == CAYMAN) {
for (i = 0; i < 3; i++) {
memset(&alu, 0, sizeof(struct r600_bc_alu));
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
r600_bc_src(&alu.src[0], &ctx->src[0], 0);
+ r600_bc_src_set_abs(&alu.src[0]);
alu.dst.sel = ctx->temp_reg;
alu.dst.chan = i;
@@ -2514,6 +2539,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
r600_bc_src(&alu.src[0], &ctx->src[0], 0);
+ r600_bc_src_set_abs(&alu.src[0]);
alu.dst.sel = ctx->temp_reg;
alu.dst.chan = 0;
@@ -2538,15 +2564,16 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
return r;
}
- /* result.y = src.x / (2 ^ floor(log2(src.x))); */
+ /* result.y = |src.x| / (2 ^ floor(log2(|src.x|))); */
if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
- if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+ if (ctx->bc->chip_class == CAYMAN) {
for (i = 0; i < 3; i++) {
memset(&alu, 0, sizeof(struct r600_bc_alu));
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
r600_bc_src(&alu.src[0], &ctx->src[0], 0);
+ r600_bc_src_set_abs(&alu.src[0]);
alu.dst.sel = ctx->temp_reg;
alu.dst.chan = i;
@@ -2564,6 +2591,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
r600_bc_src(&alu.src[0], &ctx->src[0], 0);
+ r600_bc_src_set_abs(&alu.src[0]);
alu.dst.sel = ctx->temp_reg;
alu.dst.chan = 1;
@@ -2590,7 +2618,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
if (r)
return r;
- if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+ if (ctx->bc->chip_class == CAYMAN) {
for (i = 0; i < 3; i++) {
memset(&alu, 0, sizeof(struct r600_bc_alu));
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE);
@@ -2624,7 +2652,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
return r;
}
- if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+ if (ctx->bc->chip_class == CAYMAN) {
for (i = 0; i < 3; i++) {
memset(&alu, 0, sizeof(struct r600_bc_alu));
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RECIP_IEEE);
@@ -2663,6 +2691,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
r600_bc_src(&alu.src[0], &ctx->src[0], 0);
+ r600_bc_src_set_abs(&alu.src[0]);
alu.src[1].sel = ctx->temp_reg;
alu.src[1].chan = 1;
@@ -2677,14 +2706,15 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
return r;
}
- /* result.z = log2(src);*/
+ /* result.z = log2(|src|);*/
if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
- if (ctx->bc->chiprev == CHIPREV_CAYMAN) {
+ if (ctx->bc->chip_class == CAYMAN) {
for (i = 0; i < 3; i++) {
memset(&alu, 0, sizeof(struct r600_bc_alu));
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
r600_bc_src(&alu.src[0], &ctx->src[0], 0);
+ r600_bc_src_set_abs(&alu.src[0]);
alu.dst.sel = ctx->temp_reg;
if (i == 2)
@@ -2702,6 +2732,7 @@ static int tgsi_log(struct r600_shader_ctx *ctx)
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE);
r600_bc_src(&alu.src[0], &ctx->src[0], 0);
+ r600_bc_src_set_abs(&alu.src[0]);
alu.dst.sel = ctx->temp_reg;
alu.dst.write = 1;
diff --git a/src/gallium/drivers/r600/r600_shader.h b/src/gallium/drivers/r600/r600_shader.h
index 76aebf2b1ea..3ba84bd8907 100644
--- a/src/gallium/drivers/r600/r600_shader.h
+++ b/src/gallium/drivers/r600/r600_shader.h
@@ -43,7 +43,6 @@ struct r600_shader {
unsigned nlds;
struct r600_shader_io input[32];
struct r600_shader_io output[32];
- enum radeon_family family;
boolean uses_kill;
boolean fs_write_all;
boolean clamp_color;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 3085cd9a87a..01406f2bad6 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -263,6 +263,10 @@ static uint32_t r600_translate_dbformat(enum pipe_format format)
return V_028010_DEPTH_X8_24;
case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
return V_028010_DEPTH_8_24;
+ case PIPE_FORMAT_Z32_FLOAT:
+ return V_028010_DEPTH_32_FLOAT;
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+ return V_028010_DEPTH_X24_8_32_FLOAT;
default:
return ~0U;
}
@@ -353,6 +357,7 @@ static uint32_t r600_translate_colorswap(enum pipe_format format)
case PIPE_FORMAT_R16G16_UNORM:
case PIPE_FORMAT_R16G16_FLOAT:
case PIPE_FORMAT_R32_FLOAT:
+ case PIPE_FORMAT_Z32_FLOAT:
return V_0280A0_SWAP_STD;
/* 64-bit buffers. */
@@ -360,6 +365,7 @@ static uint32_t r600_translate_colorswap(enum pipe_format format)
case PIPE_FORMAT_R16G16B16A16_UNORM:
case PIPE_FORMAT_R16G16B16A16_SNORM:
case PIPE_FORMAT_R16G16B16A16_FLOAT:
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
/* 128-bit buffers. */
case PIPE_FORMAT_R32G32B32A32_FLOAT:
@@ -444,7 +450,11 @@ static uint32_t r600_translate_colorformat(enum pipe_format format)
case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
return V_0280A0_COLOR_24_8;
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+ return V_0280A0_COLOR_X24_8_32_FLOAT;
+
case PIPE_FORMAT_R32_FLOAT:
+ case PIPE_FORMAT_Z32_FLOAT:
return V_0280A0_COLOR_32_FLOAT;
case PIPE_FORMAT_R16G16_FLOAT:
@@ -501,11 +511,11 @@ static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
if (R600_BIG_ENDIAN) {
switch(colorformat) {
case V_0280A0_COLOR_4_4:
- return(ENDIAN_NONE);
+ return ENDIAN_NONE;
/* 8-bit buffers. */
case V_0280A0_COLOR_8:
- return(ENDIAN_NONE);
+ return ENDIAN_NONE;
/* 16-bit buffers. */
case V_0280A0_COLOR_5_6_5:
@@ -513,7 +523,7 @@ static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
case V_0280A0_COLOR_4_4_4_4:
case V_0280A0_COLOR_16:
case V_0280A0_COLOR_8_8:
- return(ENDIAN_8IN16);
+ return ENDIAN_8IN16;
/* 32-bit buffers. */
case V_0280A0_COLOR_8_8_8_8:
@@ -523,22 +533,23 @@ static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
case V_0280A0_COLOR_32_FLOAT:
case V_0280A0_COLOR_16_16_FLOAT:
case V_0280A0_COLOR_16_16:
- return(ENDIAN_8IN32);
+ return ENDIAN_8IN32;
/* 64-bit buffers. */
case V_0280A0_COLOR_16_16_16_16:
case V_0280A0_COLOR_16_16_16_16_FLOAT:
- return(ENDIAN_8IN16);
+ return ENDIAN_8IN16;
case V_0280A0_COLOR_32_32_FLOAT:
case V_0280A0_COLOR_32_32:
- return(ENDIAN_8IN32);
+ case V_0280A0_COLOR_X24_8_32_FLOAT:
+ return ENDIAN_8IN32;
/* 128-bit buffers. */
case V_0280A0_COLOR_32_32_32_FLOAT:
case V_0280A0_COLOR_32_32_32_32_FLOAT:
case V_0280A0_COLOR_32_32_32_32:
- return(ENDIAN_8IN32);
+ return ENDIAN_8IN32;
default:
return ENDIAN_NONE; /* Unsupported. */
}
@@ -635,6 +646,7 @@ void r600_polygon_offset_update(struct r600_pipe_context *rctx)
offset_units *= 2.0f;
break;
case PIPE_FORMAT_Z32_FLOAT:
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
depth = -23;
offset_units *= 1.0f;
offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
@@ -1399,7 +1411,7 @@ static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rsta
/* EXPORT_NORM is an optimzation that can be enabled for better
* performance in certain cases
*/
- if (rctx->family < CHIP_RV770) {
+ if (rctx->chip_class == R600) {
/* EXPORT_NORM can be enabled if:
* - 11-bit or smaller UNORM/SNORM/SRGB
* - BLEND_CLAMP is enabled
@@ -1559,7 +1571,7 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx,
r600_pipe_state_add_reg(rstate,
R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
0xFFFFFFFF, NULL);
- if (rctx->family >= CHIP_RV770) {
+ if (rctx->chip_class >= R700) {
r600_pipe_state_add_reg(rstate,
R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
0xFFFFFFFF, NULL);
@@ -1653,16 +1665,13 @@ void r600_init_state_functions(struct r600_pipe_context *rctx)
void r600_adjust_gprs(struct r600_pipe_context *rctx)
{
- enum radeon_family family;
struct r600_pipe_state rstate;
unsigned num_ps_gprs = rctx->default_ps_gprs;
unsigned num_vs_gprs = rctx->default_vs_gprs;
unsigned tmp;
int diff;
- family = r600_get_family(rctx->radeon);
-
- if (family >= CHIP_CEDAR)
+ if (rctx->chip_class >= EVERGREEN)
return;
if (!rctx->ps_shader && !rctx->vs_shader)
@@ -1714,7 +1723,7 @@ void r600_init_config(struct r600_pipe_context *rctx)
struct r600_pipe_state *rstate = &rctx->config;
u32 tmp;
- family = r600_get_family(rctx->radeon);
+ family = rctx->family;
ps_prio = 0;
vs_prio = 1;
gs_prio = 2;
@@ -1895,7 +1904,7 @@ void r600_init_config(struct r600_pipe_context *rctx)
r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
- if (family >= CHIP_RV770) {
+ if (rctx->chip_class >= R700) {
r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
S_009508_DISABLE_CUBE_ANISO(1) |
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index d9140403e5a..408eaed491b 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -109,7 +109,7 @@ void r600_bind_rs_state(struct pipe_context *ctx, void *state)
rctx->states[rs->rstate.id] = &rs->rstate;
r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
- if (rctx->family >= CHIP_CEDAR) {
+ if (rctx->chip_class >= EVERGREEN) {
evergreen_polygon_offset_update(rctx);
} else {
r600_polygon_offset_update(rctx);
@@ -212,7 +212,7 @@ void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
/* Zero states. */
for (i = 0; i < count; i++) {
if (!buffers[i].buffer) {
- if (rctx->family >= CHIP_CEDAR) {
+ if (rctx->chip_class >= EVERGREEN) {
evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
} else {
r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
@@ -220,7 +220,7 @@ void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
}
}
for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
- if (rctx->family >= CHIP_CEDAR) {
+ if (rctx->chip_class >= EVERGREEN) {
evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
} else {
r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
@@ -367,7 +367,7 @@ static void r600_spi_update(struct r600_pipe_context *rctx)
for (i = 0; i < rshader->ninput; i++) {
if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
rshader->input[i].name == TGSI_SEMANTIC_FACE)
- if (rctx->family >= CHIP_CEDAR)
+ if (rctx->chip_class >= EVERGREEN)
continue;
else
sid=0;
@@ -387,7 +387,7 @@ static void r600_spi_update(struct r600_pipe_context *rctx)
tmp |= S_028644_PT_SPRITE_TEX(1);
}
- if (rctx->family < CHIP_CEDAR) {
+ if (rctx->chip_class < EVERGREEN) {
if (rshader->input[i].centroid)
tmp |= S_028644_SEL_CENTROID(1);
@@ -434,14 +434,14 @@ void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
rstate = &rctx->vs_const_buffer_resource[index];
if (!rstate->id) {
- if (rctx->family >= CHIP_CEDAR) {
+ if (rctx->chip_class >= EVERGREEN) {
evergreen_pipe_init_buffer_resource(rctx, rstate);
} else {
r600_pipe_init_buffer_resource(rctx, rstate);
}
}
- if (rctx->family >= CHIP_CEDAR) {
+ if (rctx->chip_class >= EVERGREEN) {
evergreen_pipe_mod_buffer_resource(rstate, &rbuffer->r, offset, 16);
evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
} else {
@@ -462,13 +462,13 @@ void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
rstate = &rctx->ps_const_buffer_resource[index];
if (!rstate->id) {
- if (rctx->family >= CHIP_CEDAR) {
+ if (rctx->chip_class >= EVERGREEN) {
evergreen_pipe_init_buffer_resource(rctx, rstate);
} else {
r600_pipe_init_buffer_resource(rctx, rstate);
}
}
- if (rctx->family >= CHIP_CEDAR) {
+ if (rctx->chip_class >= EVERGREEN) {
evergreen_pipe_mod_buffer_resource(rstate, &rbuffer->r, offset, 16);
evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
} else {
@@ -521,14 +521,14 @@ static void r600_vertex_buffer_update(struct r600_pipe_context *rctx)
offset += vertex_buffer->buffer_offset + r600_bo_offset(rbuffer->bo);
if (!rstate->id) {
- if (rctx->family >= CHIP_CEDAR) {
+ if (rctx->chip_class >= EVERGREEN) {
evergreen_pipe_init_buffer_resource(rctx, rstate);
} else {
r600_pipe_init_buffer_resource(rctx, rstate);
}
}
- if (rctx->family >= CHIP_CEDAR) {
+ if (rctx->chip_class >= EVERGREEN) {
evergreen_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride);
evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
} else {
@@ -600,7 +600,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
r600_shader_rebuild(ctx, rctx->vs_shader);
if ((rctx->ps_shader->shader.clamp_color != rctx->clamp_fragment_color) ||
- ((rctx->family >= CHIP_CEDAR) && rctx->ps_shader->shader.fs_write_all &&
+ ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
(rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs)))
r600_shader_rebuild(ctx, rctx->ps_shader);
@@ -655,7 +655,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
rdraw.indices_bo_offset = draw.index_buffer_offset;
}
- if (rctx->family >= CHIP_CEDAR) {
+ if (rctx->chip_class >= EVERGREEN) {
evergreen_context_draw(&rctx->ctx, &rdraw);
} else {
r600_context_draw(&rctx->ctx, &rdraw);
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index 18460419f85..10c32c53a6d 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -313,7 +313,14 @@ static boolean permit_hardware_blit(struct pipe_screen *screen,
PIPE_BIND_SAMPLER_VIEW))
return FALSE;
- return TRUE;
+ switch (res->usage) {
+ case PIPE_USAGE_STREAM:
+ case PIPE_USAGE_STAGING:
+ return FALSE;
+
+ default:
+ return TRUE;
+ }
}
static boolean r600_texture_get_handle(struct pipe_screen* screen,
@@ -851,6 +858,12 @@ uint32_t r600_translate_texformat(struct pipe_screen *screen,
result = FMT_8;
word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
goto out_word4;
+ case PIPE_FORMAT_Z32_FLOAT:
+ result = FMT_32_FLOAT;
+ goto out_word4;
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
+ result = FMT_X24_8_32_FLOAT;
+ goto out_word4;
default:
goto out_unknown;
}
diff --git a/src/gallium/state_trackers/dri/common/dri_context.c b/src/gallium/state_trackers/dri/common/dri_context.c
index 08bbdf96e34..e6612b1911d 100644
--- a/src/gallium/state_trackers/dri/common/dri_context.c
+++ b/src/gallium/state_trackers/dri/common/dri_context.c
@@ -143,8 +143,6 @@ dri_unbind_context(__DRIcontext * cPriv)
/* dri_util.c ensures cPriv is not null */
struct dri_screen *screen = dri_screen(cPriv->driScreenPriv);
struct dri_context *ctx = dri_context(cPriv);
- struct dri_drawable *draw = dri_drawable(ctx->dPriv);
- struct dri_drawable *read = dri_drawable(ctx->rPriv);
struct st_api *stapi = screen->st_api;
if (--ctx->bind_count == 0) {
diff --git a/src/gallium/state_trackers/egl/x11/x11_screen.c b/src/gallium/state_trackers/egl/x11/x11_screen.c
index f1cc4400ba5..6155b4d03c0 100644
--- a/src/gallium/state_trackers/egl/x11/x11_screen.c
+++ b/src/gallium/state_trackers/egl/x11/x11_screen.c
@@ -452,6 +452,12 @@ dri2InvalidateBuffers(Display *dpy, XID drawable)
extern unsigned
dri2GetSwapEventType(Display *dpy, XID drawable);
+extern void *
+dri2GetGlxDrawableFromXDrawableId(Display *dpy, XID id);
+
+extern void *
+GetGLXDrawable(Display *dpy, XID drawable);
+
/**
* This is also called from src/glx/dri2.c.
*/
@@ -460,4 +466,16 @@ unsigned dri2GetSwapEventType(Display *dpy, XID drawable)
return 0;
}
+void *
+dri2GetGlxDrawableFromXDrawableId(Display *dpy, XID id)
+{
+ return NULL;
+}
+
+void *
+GetGLXDrawable(Display *dpy, XID drawable)
+{
+ return NULL;
+}
+
#endif /* GLX_DIRECT_RENDERING */
diff --git a/src/gallium/state_trackers/glx/xlib/glx_api.c b/src/gallium/state_trackers/glx/xlib/glx_api.c
index 6233fb81781..a7aafd846cd 100644
--- a/src/gallium/state_trackers/glx/xlib/glx_api.c
+++ b/src/gallium/state_trackers/glx/xlib/glx_api.c
@@ -864,16 +864,19 @@ choose_visual( Display *dpy, int screen, const int *list, GLboolean fbConfig )
parselist++;
break;
case GLX_FBCONFIG_ID:
+ case GLX_VISUAL_ID:
if (!fbConfig)
return NULL;
parselist++;
desiredVisualID = *parselist++;
break;
case GLX_X_RENDERABLE:
+ case GLX_MAX_PBUFFER_WIDTH:
+ case GLX_MAX_PBUFFER_HEIGHT:
+ case GLX_MAX_PBUFFER_PIXELS:
if (!fbConfig)
- return NULL;
- parselist += 2;
- /* ignore */
+ return NULL; /* invalid config option */
+ parselist += 2; /* ignore the parameter */
break;
#ifdef GLX_EXT_texture_from_pixmap
diff --git a/src/gallium/targets/egl-static/Makefile b/src/gallium/targets/egl-static/Makefile
index 832d7ba438f..69e7eecdf0c 100644
--- a/src/gallium/targets/egl-static/Makefile
+++ b/src/gallium/targets/egl-static/Makefile
@@ -42,7 +42,7 @@ egl_CPPFLAGS += \
-I$(TOP)/src/egl/main \
-D_EGL_MAIN=_eglMain
egl_LIBS += $(TOP)/src/gallium/state_trackers/egl/libegl.a
-egl_SYS += $(LIBUDEV_LIBS) $(DLOPEN_LIBS) -lEGL -lm
+egl_SYS += $(LIBUDEV_LIBS) $(DLOPEN_LIBS) -lEGL -lm -lpthread
# EGL platforms
ifneq ($(findstring x11, $(EGL_PLATFORMS)),)
diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index 4d9dd505c41..60d2e289396 100644
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -55,6 +55,7 @@ static const struct r600_reg evergreen_config_reg_list[] = {
{R_008C24_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
{R_008C28_SQ_STACK_RESOURCE_MGMT_3, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
{R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
+ {R_008E2C_SQ_LDS_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
{R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
{R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0},
};
diff --git a/src/gallium/winsys/r600/drm/r600_drm.c b/src/gallium/winsys/r600/drm/r600_drm.c
index 4602f7f2a4b..b5a4d928bf5 100644
--- a/src/gallium/winsys/r600/drm/r600_drm.c
+++ b/src/gallium/winsys/r600/drm/r600_drm.c
@@ -186,7 +186,7 @@ static int eg_interpret_tiling(struct radeon *radeon, uint32_t tiling_config)
static int radeon_drm_get_tiling(struct radeon *radeon)
{
- struct drm_radeon_info info;
+ struct drm_radeon_info info = {};
int r;
uint32_t tiling_config = 0;
@@ -208,8 +208,8 @@ static int radeon_drm_get_tiling(struct radeon *radeon)
static int radeon_get_clock_crystal_freq(struct radeon *radeon)
{
- struct drm_radeon_info info;
- uint32_t clock_crystal_freq;
+ struct drm_radeon_info info = {};
+ uint32_t clock_crystal_freq = 0;
int r;
info.request = RADEON_INFO_CLOCK_CRYSTAL_FREQ;
@@ -226,8 +226,8 @@ static int radeon_get_clock_crystal_freq(struct radeon *radeon)
static int radeon_get_num_backends(struct radeon *radeon)
{
- struct drm_radeon_info info;
- uint32_t num_backends;
+ struct drm_radeon_info info = {};
+ uint32_t num_backends = 0;
int r;
info.request = RADEON_INFO_NUM_BACKENDS;
diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c
index 633cd35f7a7..a2f13ff0863 100644
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -1504,7 +1504,7 @@ void r600_context_flush(struct r600_context *ctx)
/* suspend queries */
r600_context_queries_suspend(ctx);
- if (ctx->radeon->family >= CHIP_CEDAR)
+ if (ctx->radeon->chip_class >= EVERGREEN)
evergreen_context_flush_dest_caches(ctx);
else
r600_context_flush_dest_caches(ctx);