summaryrefslogtreecommitdiff
path: root/src/gallium
diff options
context:
space:
mode:
authorMarek Olšák <marek.olsak@amd.com>2015-10-18 15:09:24 +0200
committerMarek Olšák <marek.olsak@amd.com>2015-10-20 12:56:46 +0200
commit8339585b1206232c1df165108ef6adadb0829ab0 (patch)
tree48a11070c714d69fb167785474b594d3249508a3 /src/gallium
parent38391835b5cbdd52e7a3221ff98f402aefa1639b (diff)
radeonsi: enable BC_OPTIMIZE if centroid isn't used
This solution was recommended by a Catalyst developer. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/radeonsi/si_state_shaders.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 8b26b943e00..eea00e0fafc 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -404,6 +404,7 @@ static void si_shader_ps(struct si_shader *shader)
unsigned num_sgprs, num_user_sgprs;
unsigned spi_baryc_cntl = 0;
uint64_t va;
+ bool has_centroid;
pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
@@ -435,8 +436,11 @@ static void si_shader_ps(struct si_shader *shader)
}
}
+ has_centroid = G_0286CC_PERSP_CENTROID_ENA(shader->spi_ps_input_ena) ||
+ G_0286CC_LINEAR_CENTROID_ENA(shader->spi_ps_input_ena);
+
spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
- S_0286D8_BC_OPTIMIZE_DISABLE(1);
+ S_0286D8_BC_OPTIMIZE_DISABLE(has_centroid);
si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);