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authorIlia Mirkin <imirkin@alum.mit.edu>2013-12-01 23:13:56 -0500
committerIan Romanick <ian.d.romanick@intel.com>2013-12-06 10:51:18 -0800
commitde517d2bb38c62a6814c3c624cbcca942f8f13af (patch)
treecf1c4e7d7999ec56dd1552ca14c3fbf00c51dcc4 /src/gallium
parent8991193f70c9879162e3822589a6c17afdae433c (diff)
nv50: Fix GPU_READING/WRITING bit removal
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> CC: "9.1, 9.2, 10.0" <mesa-stable@lists.freedesktop.org> (cherry picked from commit c45cf6199fc493538cef33125c8a97a892e2ca83)
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/nouveau/nv50/nv50_state_validate.c4
-rw-r--r--src/gallium/drivers/nouveau/nv50/nv50_tex.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
index 866829ca22d..86b9a236fb6 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
@@ -61,7 +61,7 @@ nv50_validate_fb(struct nv50_context *nv50)
if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING)
nv50->state.rt_serialize = TRUE;
mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
- mt->base.status &= NOUVEAU_BUFFER_STATUS_GPU_READING;
+ mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
/* only register for writing, otherwise we'd always serialize here */
BCTX_REFN(nv50->bufctx_3d, FB, &mt->base, WR);
@@ -91,7 +91,7 @@ nv50_validate_fb(struct nv50_context *nv50)
if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING)
nv50->state.rt_serialize = TRUE;
mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
- mt->base.status &= NOUVEAU_BUFFER_STATUS_GPU_READING;
+ mt->base.status &= ~NOUVEAU_BUFFER_STATUS_GPU_READING;
BCTX_REFN(nv50->bufctx_3d, FB, &mt->base, WR);
} else {
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_tex.c b/src/gallium/drivers/nouveau/nv50/nv50_tex.c
index 9e512928381..f7284fa50ce 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_tex.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_tex.c
@@ -271,7 +271,7 @@ nv50_validate_tic(struct nv50_context *nv50, int s)
nv50->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
- res->status &= NOUVEAU_BUFFER_STATUS_GPU_WRITING;
+ res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
BCTX_REFN(nv50->bufctx_3d, TEXTURES, res, RD);