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authorPierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>2022-08-11 15:05:18 +0200
committerMarge Bot <emma+marge@anholt.net>2022-08-31 13:29:48 +0000
commitd05a2243d46cb3c34e154a609dc0ceb6a5c92dac (patch)
tree6ea9633dd8152c19bb12926f60a7ae7c9bd8a5d1 /src/gallium/winsys
parent33426a328b783dedb86f9c024225c2635579eda7 (diff)
radeonsi/sqtt: set stable pstate if possible
This avoids the need to manually change the power profile. Reviewed-by: Mihai Preda <mhpreda@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18009>
Diffstat (limited to 'src/gallium/winsys')
-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c29
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_drm_winsys.c6
2 files changed, 35 insertions, 0 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index 1aa1985227c..318197b1ae2 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -363,6 +363,34 @@ static bool amdgpu_cs_is_secure(struct radeon_cmdbuf *rcs)
return cs->csc->secure;
}
+static uint32_t
+radeon_to_amdgpu_pstate(enum radeon_ctx_pstate pstate)
+{
+ switch (pstate) {
+ case RADEON_CTX_PSTATE_NONE:
+ return AMDGPU_CTX_STABLE_PSTATE_NONE;
+ case RADEON_CTX_PSTATE_STANDARD:
+ return AMDGPU_CTX_STABLE_PSTATE_STANDARD;
+ case RADEON_CTX_PSTATE_MIN_SCLK:
+ return AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK;
+ case RADEON_CTX_PSTATE_MIN_MCLK:
+ return AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK;
+ case RADEON_CTX_PSTATE_PEAK:
+ return AMDGPU_CTX_STABLE_PSTATE_PEAK;
+ default:
+ unreachable("Invalid pstate");
+ }
+}
+
+static bool
+amdgpu_cs_set_pstate(struct radeon_cmdbuf *rcs, enum radeon_ctx_pstate pstate)
+{
+ struct amdgpu_cs *cs = amdgpu_cs(rcs);
+ uint32_t amdgpu_pstate = radeon_to_amdgpu_pstate(pstate);
+ return amdgpu_cs_ctx_stable_pstate(cs->ctx->ctx,
+ AMDGPU_CTX_OP_SET_STABLE_PSTATE, amdgpu_pstate, NULL) == 0;
+}
+
PUBLIC struct radeon_winsys *
amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
radeon_screen_create_t screen_create)
@@ -532,6 +560,7 @@ amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
ws->base.read_registers = amdgpu_read_registers;
ws->base.pin_threads_to_L3_cache = amdgpu_pin_threads_to_L3_cache;
ws->base.cs_is_secure = amdgpu_cs_is_secure;
+ ws->base.cs_set_pstate = amdgpu_cs_set_pstate;
amdgpu_bo_init_functions(ws);
amdgpu_cs_init_functions(ws);
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 9135380012e..0c94f9f769b 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -787,6 +787,11 @@ static bool radeon_cs_is_secure(struct radeon_cmdbuf* cs)
return false;
}
+static bool radeon_cs_set_pstate(struct radeon_cmdbuf* cs, enum radeon_ctx_pstate state)
+{
+ return false;
+}
+
PUBLIC struct radeon_winsys *
radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config,
radeon_screen_create_t screen_create)
@@ -859,6 +864,7 @@ radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config,
ws->base.query_value = radeon_query_value;
ws->base.read_registers = radeon_read_registers;
ws->base.cs_is_secure = radeon_cs_is_secure;
+ ws->base.cs_set_pstate = radeon_cs_set_pstate;
radeon_drm_bo_init_functions(ws);
radeon_drm_cs_init_functions(ws);