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authorPierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>2021-05-26 15:19:16 +0200
committerMarge Bot <eric+marge@anholt.net>2021-06-07 07:38:35 +0000
commita57e90bfea4c538ad2e0f70d693ea092201ede68 (patch)
tree68336a5f53ada46bf2f4493ae56f710461060e31 /src/gallium/winsys
parenta981105d906e08b00fd70a81ada575efa4f43b05 (diff)
winsys/amdgpu: use int16 for buffer_indices_hashlist
int16 allows to correctly store the indices of 32k buffers; this seems sufficient and is twice smaller than regular int. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11010>
Diffstat (limited to 'src/gallium/winsys')
-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_cs.c8
-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_cs.h11
2 files changed, 12 insertions, 7 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 22f5671dfa4..4898cb31e1c 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -444,7 +444,7 @@ static int amdgpu_lookup_buffer(struct amdgpu_cs_context *cs, struct amdgpu_wins
* AAAAAAAAAAABBBBBBBBBBBBBBCCCCCCCC
* will collide here: ^ and here: ^,
* meaning that we should get very few collisions in the end. */
- cs->buffer_indices_hashlist[hash] = i;
+ cs->buffer_indices_hashlist[hash] = i & 0x7fff;
return i;
}
}
@@ -523,7 +523,7 @@ amdgpu_lookup_or_add_real_buffer(struct radeon_cmdbuf *rcs, struct amdgpu_cs *ac
idx = amdgpu_do_add_real_buffer(acs->ws, cs, bo);
hash = bo->unique_id & (BUFFER_HASHLIST_SIZE-1);
- cs->buffer_indices_hashlist[hash] = idx;
+ cs->buffer_indices_hashlist[hash] = idx & 0x7fff;
if (bo->base.placement & RADEON_DOMAIN_VRAM)
rcs->used_vram_kb += bo->base.size / 1024;
@@ -578,7 +578,7 @@ static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_winsys *ws,
cs->num_slab_buffers++;
hash = bo->unique_id & (BUFFER_HASHLIST_SIZE-1);
- cs->buffer_indices_hashlist[hash] = idx;
+ cs->buffer_indices_hashlist[hash] = idx & 0x7fff;
return idx;
}
@@ -622,7 +622,7 @@ static int amdgpu_lookup_or_add_sparse_buffer(struct amdgpu_winsys *ws,
cs->num_sparse_buffers++;
hash = bo->unique_id & (BUFFER_HASHLIST_SIZE-1);
- cs->buffer_indices_hashlist[hash] = idx;
+ cs->buffer_indices_hashlist[hash] = idx & 0x7fff;
/* We delay adding the backing buffers until we really have to. However,
* we cannot delay accounting for memory use.
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
index 4683ed9b210..77bde4a070b 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
@@ -104,7 +104,7 @@ struct amdgpu_cs_context {
unsigned max_sparse_buffers;
struct amdgpu_cs_buffer *sparse_buffers;
- int *buffer_indices_hashlist;
+ int16_t *buffer_indices_hashlist;
struct amdgpu_winsys_bo *last_added_bo;
unsigned last_added_bo_index;
@@ -147,8 +147,13 @@ struct amdgpu_cs {
struct amdgpu_cs_context *csc;
/* The CS being currently-owned by the other thread. */
struct amdgpu_cs_context *cst;
- /* This is only used by csc, not cst */
- int buffer_indices_hashlist[BUFFER_HASHLIST_SIZE];
+ /* buffer_indices_hashlist[hash(bo)] returns -1 if the bo
+ * isn't part of any buffer lists or the index where the bo could be found.
+ * Since 1) hash collisions of 2 different bo can happen and 2) we use a
+ * single hashlist for the 3 buffer list, this is only a hint.
+ * amdgpu_lookup_buffer uses this hint to speed up buffers look up.
+ */
+ int16_t buffer_indices_hashlist[BUFFER_HASHLIST_SIZE];
/* Flush CS. */
void (*flush_cs)(void *ctx, unsigned flags, struct pipe_fence_handle **fence);