r300,r600,radeonsi: inline struct radeon_cmdbuf to remove dereferences

It's straightforward except that the amdgpu winsys had to be cleaned up
to allow this.

radeon_cmdbuf is inlined and optionally the winsys can save the pointer
to it. radeon_cmdbuf::priv points to the winsys cs structure.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7907>

3 files changed, 101 insertions, 113 deletions

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 46e560a6dca..90c598316f0 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -276,7 +276,7 @@ void *amdgpu_bo_map(struct pb_buffer *buf,
 {
    struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
    struct amdgpu_winsys_bo *real;
-   struct amdgpu_cs *cs = (struct amdgpu_cs*)rcs;
+   struct amdgpu_cs *cs = rcs ? amdgpu_cs(rcs) : NULL;
 
    assert(!(bo->base.usage & RADEON_FLAG_SPARSE));
 
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 25be8a1695c..632138fde01 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -489,7 +489,8 @@ amdgpu_do_add_real_buffer(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo
 }
 
 static int
-amdgpu_lookup_or_add_real_buffer(struct amdgpu_cs *acs, struct amdgpu_winsys_bo *bo)
+amdgpu_lookup_or_add_real_buffer(struct radeon_cmdbuf *rcs, struct amdgpu_cs *acs,
+                                 struct amdgpu_winsys_bo *bo)
 {
    struct amdgpu_cs_context *cs = acs->csc;
    unsigned hash;
@@ -504,14 +505,15 @@ amdgpu_lookup_or_add_real_buffer(struct amdgpu_cs *acs, struct amdgpu_winsys_bo
    cs->buffer_indices_hashlist[hash] = idx;
 
    if (bo->base.placement & RADEON_DOMAIN_VRAM)
-      acs->main.base.used_vram += bo->base.size;
+      rcs->used_vram += bo->base.size;
    else if (bo->base.placement & RADEON_DOMAIN_GTT)
-      acs->main.base.used_gart += bo->base.size;
+      rcs->used_gart += bo->base.size;
 
    return idx;
 }
 
-static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_cs *acs,
+static int amdgpu_lookup_or_add_slab_buffer(struct radeon_cmdbuf *rcs,
+                                            struct amdgpu_cs *acs,
                                             struct amdgpu_winsys_bo *bo)
 {
    struct amdgpu_cs_context *cs = acs->csc;
@@ -523,7 +525,7 @@ static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_cs *acs,
    if (idx >= 0)
       return idx;
 
-   real_idx = amdgpu_lookup_or_add_real_buffer(acs, bo->u.slab.real);
+   real_idx = amdgpu_lookup_or_add_real_buffer(rcs, acs, bo->u.slab.real);
    if (real_idx < 0)
       return -1;
 
@@ -560,7 +562,8 @@ static int amdgpu_lookup_or_add_slab_buffer(struct amdgpu_cs *acs,
    return idx;
 }
 
-static int amdgpu_lookup_or_add_sparse_buffer(struct amdgpu_cs *acs,
+static int amdgpu_lookup_or_add_sparse_buffer(struct radeon_cmdbuf *rcs,
+                                              struct amdgpu_cs *acs,
                                               struct amdgpu_winsys_bo *bo)
 {
    struct amdgpu_cs_context *cs = acs->csc;
@@ -607,9 +610,9 @@ static int amdgpu_lookup_or_add_sparse_buffer(struct amdgpu_cs *acs,
 
    list_for_each_entry(struct amdgpu_sparse_backing, backing, &bo->u.sparse.backing, list) {
       if (bo->base.placement & RADEON_DOMAIN_VRAM)
-         acs->main.base.used_vram += backing->bo->base.size;
+         rcs->used_vram += backing->bo->base.size;
       else if (bo->base.placement & RADEON_DOMAIN_GTT)
-         acs->main.base.used_gart += backing->bo->base.size;
+         rcs->used_gart += backing->bo->base.size;
    }
 
    simple_mtx_unlock(&bo->lock);
@@ -643,7 +646,7 @@ static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf *rcs,
 
    if (!(bo->base.usage & RADEON_FLAG_SPARSE)) {
       if (!bo->bo) {
-         index = amdgpu_lookup_or_add_slab_buffer(acs, bo);
+         index = amdgpu_lookup_or_add_slab_buffer(rcs, acs, bo);
          if (index < 0)
             return 0;
 
@@ -653,14 +656,14 @@ static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf *rcs,
          usage &= ~RADEON_USAGE_SYNCHRONIZED;
          index = buffer->u.slab.real_idx;
       } else {
-         index = amdgpu_lookup_or_add_real_buffer(acs, bo);
+         index = amdgpu_lookup_or_add_real_buffer(rcs, acs, bo);
          if (index < 0)
             return 0;
       }
 
       buffer = &cs->real_buffers[index];
    } else {
-      index = amdgpu_lookup_or_add_sparse_buffer(acs, bo);
+      index = amdgpu_lookup_or_add_sparse_buffer(rcs, acs, bo);
       if (index < 0)
          return 0;
 
@@ -679,7 +682,7 @@ static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf *rcs,
 
 static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws,
                                  struct amdgpu_ib *ib,
-                                 enum ring_type ring_type)
+                                 struct amdgpu_cs *cs)
 {
    struct pb_buffer *pb;
    uint8_t *mapped;
@@ -691,7 +694,7 @@ static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws,
     * is the largest power of two that fits into the size field of the
     * INDIRECT_BUFFER packet.
     */
-   if (amdgpu_cs_has_chaining(amdgpu_cs_from_ib(ib)))
+   if (amdgpu_cs_has_chaining(cs))
       buffer_size = 4 *util_next_power_of_two(ib->max_ib_size);
    else
       buffer_size = 4 *util_next_power_of_two(4 * ib->max_ib_size);
@@ -706,9 +709,9 @@ static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws,
                          ws->info.gart_page_size,
                          RADEON_DOMAIN_GTT,
                          RADEON_FLAG_NO_INTERPROCESS_SHARING |
-                         (ring_type == RING_GFX ||
-                          ring_type == RING_COMPUTE ||
-                          ring_type == RING_DMA ?
+                         (cs->ring_type == RING_GFX ||
+                          cs->ring_type == RING_COMPUTE ||
+                          cs->ring_type == RING_DMA ?
                           RADEON_FLAG_32BIT | RADEON_FLAG_GTT_WC : 0));
    if (!pb)
       return false;
@@ -746,29 +749,19 @@ static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type)
    }
 }
 
-static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws, struct amdgpu_cs *cs,
-                              enum ib_type ib_type)
+static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws,
+                              struct radeon_cmdbuf *rcs,
+                              struct amdgpu_ib *ib,
+                              struct amdgpu_cs *cs)
 {
    /* Small IBs are better than big IBs, because the GPU goes idle quicker
     * and there is less waiting for buffers and fences. Proof:
     *   http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
     */
-   struct amdgpu_ib *ib = NULL;
-   struct drm_amdgpu_cs_chunk_ib *info = &cs->csc->ib[ib_type];
+   struct drm_amdgpu_cs_chunk_ib *info = &cs->csc->ib[ib->ib_type];
    /* This is the minimum size of a contiguous IB. */
    unsigned ib_size = 4 * 1024 * 4;
 
-   switch (ib_type) {
-   case IB_PARALLEL_COMPUTE:
-      ib = &cs->compute_ib;
-      break;
-   case IB_MAIN:
-      ib = &cs->main;
-      break;
-   default:
-      unreachable("unhandled IB type");
-   }
-
    /* Always allocate at least the size of the biggest cs_check_space call,
     * because precisely the last call might have requested this size.
     */
@@ -777,20 +770,20 @@ static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws, struct amdgpu_cs *cs,
    if (!amdgpu_cs_has_chaining(cs)) {
       ib_size = MAX2(ib_size,
                      4 * MIN2(util_next_power_of_two(ib->max_ib_size),
-                              amdgpu_ib_max_submit_dwords(ib_type)));
+                              amdgpu_ib_max_submit_dwords(ib->ib_type)));
    }
 
    ib->max_ib_size = ib->max_ib_size - ib->max_ib_size / 32;
 
-   ib->base.prev_dw = 0;
-   ib->base.num_prev = 0;
-   ib->base.current.cdw = 0;
-   ib->base.current.buf = NULL;
+   rcs->prev_dw = 0;
+   rcs->num_prev = 0;
+   rcs->current.cdw = 0;
+   rcs->current.buf = NULL;
 
    /* Allocate a new buffer for IBs if the current buffer is all used. */
    if (!ib->big_ib_buffer ||
        ib->used_ib_space + ib_size > ib->big_ib_buffer->size) {
-      if (!amdgpu_ib_new_buffer(ws, ib, cs->ring_type))
+      if (!amdgpu_ib_new_buffer(ws, ib, cs))
          return false;
    }
 
@@ -801,33 +794,34 @@ static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws, struct amdgpu_cs *cs,
    ib->ptr_ib_size = &info->ib_bytes;
    ib->ptr_ib_size_inside_ib = false;
 
-   amdgpu_cs_add_buffer(&cs->main.base, ib->big_ib_buffer,
+   amdgpu_cs_add_buffer(cs->main.rcs, ib->big_ib_buffer,
                         RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 
-   ib->base.current.buf = (uint32_t*)(ib->ib_mapped + ib->used_ib_space);
+   rcs->current.buf = (uint32_t*)(ib->ib_mapped + ib->used_ib_space);
 
    ib_size = ib->big_ib_buffer->size - ib->used_ib_space;
-   ib->base.current.max_dw = ib_size / 4 - amdgpu_cs_epilog_dws(cs);
-   ib->base.gpu_address = info->va_start;
+   rcs->current.max_dw = ib_size / 4 - amdgpu_cs_epilog_dws(cs);
+   rcs->gpu_address = info->va_start;
    return true;
 }
 
-static void amdgpu_set_ib_size(struct amdgpu_ib *ib)
+static void amdgpu_set_ib_size(struct radeon_cmdbuf *rcs, struct amdgpu_ib *ib)
 {
    if (ib->ptr_ib_size_inside_ib) {
-      *ib->ptr_ib_size = ib->base.current.cdw |
+      *ib->ptr_ib_size = rcs->current.cdw |
                          S_3F2_CHAIN(1) | S_3F2_VALID(1);
    } else {
-      *ib->ptr_ib_size = ib->base.current.cdw;
+      *ib->ptr_ib_size = rcs->current.cdw;
    }
 }
 
-static void amdgpu_ib_finalize(struct amdgpu_winsys *ws, struct amdgpu_ib *ib)
+static void amdgpu_ib_finalize(struct amdgpu_winsys *ws, struct radeon_cmdbuf *rcs,
+                               struct amdgpu_ib *ib)
 {
-   amdgpu_set_ib_size(ib);
-   ib->used_ib_space += ib->base.current.cdw * 4;
+   amdgpu_set_ib_size(rcs, ib);
+   ib->used_ib_space += rcs->current.cdw * 4;
    ib->used_ib_space = align(ib->used_ib_space, ws->info.ib_alignment);
-   ib->max_ib_size = MAX2(ib->max_ib_size, ib->base.prev_dw + ib->base.current.cdw);
+   ib->max_ib_size = MAX2(ib->max_ib_size, rcs->prev_dw + rcs->current.cdw);
 }
 
 static bool amdgpu_init_cs_context(struct amdgpu_winsys *ws,
@@ -944,8 +938,9 @@ static void amdgpu_destroy_cs_context(struct amdgpu_cs_context *cs)
 }
 
 
-static struct radeon_cmdbuf *
-amdgpu_cs_create(struct radeon_winsys_ctx *rwctx,
+static bool
+amdgpu_cs_create(struct radeon_cmdbuf *rcs,
+                 struct radeon_winsys_ctx *rwctx,
                  enum ring_type ring_type,
                  void (*flush)(void *ctx, unsigned flags,
                                struct pipe_fence_handle **fence),
@@ -957,7 +952,7 @@ amdgpu_cs_create(struct radeon_winsys_ctx *rwctx,
 
    cs = CALLOC_STRUCT(amdgpu_cs);
    if (!cs) {
-      return NULL;
+      return false;
    }
 
    util_queue_fence_init(&cs->flush_completed);
@@ -979,47 +974,52 @@ amdgpu_cs_create(struct radeon_winsys_ctx *rwctx,
 
    if (!amdgpu_init_cs_context(ctx->ws, &cs->csc1, ring_type)) {
       FREE(cs);
-      return NULL;
+      return false;
    }
 
    if (!amdgpu_init_cs_context(ctx->ws, &cs->csc2, ring_type)) {
       amdgpu_destroy_cs_context(&cs->csc1);
       FREE(cs);
-      return NULL;
+      return false;
    }
 
    /* Set the first submission context as current. */
    cs->csc = &cs->csc1;
    cs->cst = &cs->csc2;
 
-   if (!amdgpu_get_new_ib(ctx->ws, cs, IB_MAIN)) {
+   cs->main.rcs = rcs;
+   rcs->priv = cs;
+
+   if (!amdgpu_get_new_ib(ctx->ws, rcs, &cs->main, cs)) {
       amdgpu_destroy_cs_context(&cs->csc2);
       amdgpu_destroy_cs_context(&cs->csc1);
       FREE(cs);
-      return NULL;
+      rcs->priv = NULL;
+      return false;
    }
 
    p_atomic_inc(&ctx->ws->num_cs);
-   return &cs->main.base;
+   return true;
 }
 
-static struct radeon_cmdbuf *
-amdgpu_cs_add_parallel_compute_ib(struct radeon_cmdbuf *ib,
+static bool
+amdgpu_cs_add_parallel_compute_ib(struct radeon_cmdbuf *compute_cs,
+                                  struct radeon_cmdbuf *gfx_cs,
                                   bool uses_gds_ordered_append)
 {
-   struct amdgpu_cs *cs = (struct amdgpu_cs*)ib;
+   struct amdgpu_cs *cs = amdgpu_cs(gfx_cs);
    struct amdgpu_winsys *ws = cs->ctx->ws;
 
    if (cs->ring_type != RING_GFX)
-      return NULL;
+      return false;
 
    /* only one secondary IB can be added */
    if (cs->compute_ib.ib_mapped)
-      return NULL;
+      return false;
 
    /* Allocate the compute IB. */
-   if (!amdgpu_get_new_ib(ws, cs, IB_PARALLEL_COMPUTE))
-      return NULL;
+   if (!amdgpu_get_new_ib(ws, compute_cs, &cs->compute_ib, cs))
+      return false;
 
    if (uses_gds_ordered_append) {
       cs->csc1.ib[IB_PARALLEL_COMPUTE].flags |=
@@ -1027,15 +1027,17 @@ amdgpu_cs_add_parallel_compute_ib(struct radeon_cmdbuf *ib,
       cs->csc2.ib[IB_PARALLEL_COMPUTE].flags |=
             AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID;
    }
-   return &cs->compute_ib.base;
+
+   cs->compute_ib.rcs = compute_cs;
+   compute_cs->priv = cs;
+   return true;
 }
 
 static bool
 amdgpu_cs_setup_preemption(struct radeon_cmdbuf *rcs, const uint32_t *preamble_ib,
                            unsigned preamble_num_dw)
 {
-   struct amdgpu_ib *ib = amdgpu_ib(rcs);
-   struct amdgpu_cs *cs = amdgpu_cs_from_ib(ib);
+   struct amdgpu_cs *cs = amdgpu_cs(rcs);
    struct amdgpu_winsys *ws = cs->ctx->ws;
    struct amdgpu_cs_context *csc[2] = {&cs->csc1, &cs->csc2};
    unsigned size = align(preamble_num_dw * 4, ws->info.ib_alignment);
@@ -1092,8 +1094,8 @@ static bool amdgpu_cs_validate(struct radeon_cmdbuf *rcs)
 static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw,
                                   bool force_chaining)
 {
-   struct amdgpu_ib *ib = amdgpu_ib(rcs);
-   struct amdgpu_cs *cs = amdgpu_cs_from_ib(ib);
+   struct amdgpu_cs *cs = amdgpu_cs(rcs);
+   struct amdgpu_ib *ib = rcs == cs->main.rcs ? &cs->main : &cs->compute_ib;
    unsigned requested_size = rcs->prev_dw + rcs->current.cdw + dw;
    unsigned cs_epilog_dw = amdgpu_cs_epilog_dws(cs);
    unsigned need_byte_size = (dw + cs_epilog_dw) * 4;
@@ -1138,7 +1140,7 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw,
       rcs->max_prev = new_max_prev;
    }
 
-   if (!amdgpu_ib_new_buffer(cs->ctx->ws, ib, cs->ring_type))
+   if (!amdgpu_ib_new_buffer(cs->ctx->ws, ib, cs))
       return false;
 
    assert(ib->used_ib_space == 0);
@@ -1161,7 +1163,7 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw,
    assert((rcs->current.cdw & 7) == 0);
    assert(rcs->current.cdw <= rcs->current.max_dw);
 
-   amdgpu_set_ib_size(ib);
+   amdgpu_set_ib_size(rcs, ib);
    ib->ptr_ib_size = new_ptr_ib_size;
    ib->ptr_ib_size_inside_ib = true;
 
@@ -1171,14 +1173,14 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw,
    rcs->prev[rcs->num_prev].max_dw = rcs->current.cdw; /* no modifications */
    rcs->num_prev++;
 
-   ib->base.prev_dw += ib->base.current.cdw;
-   ib->base.current.cdw = 0;
+   rcs->prev_dw += rcs->current.cdw;
+   rcs->current.cdw = 0;
 
-   ib->base.current.buf = (uint32_t*)(ib->ib_mapped + ib->used_ib_space);
-   ib->base.current.max_dw = ib->big_ib_buffer->size / 4 - cs_epilog_dw;
-   ib->base.gpu_address = va;
+   rcs->current.buf = (uint32_t*)(ib->ib_mapped + ib->used_ib_space);
+   rcs->current.max_dw = ib->big_ib_buffer->size / 4 - cs_epilog_dw;
+   rcs->gpu_address = va;
 
-   amdgpu_cs_add_buffer(&cs->main.base, ib->big_ib_buffer,
+   amdgpu_cs_add_buffer(cs->main.rcs, ib->big_ib_buffer,
                         RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
 
    return true;
@@ -1764,8 +1766,8 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
 
       /* Also pad secondary IBs. */
       if (cs->compute_ib.ib_mapped) {
-         while (cs->compute_ib.base.current.cdw & ib_pad_dw_mask)
-            radeon_emit(&cs->compute_ib.base, PKT3_NOP_PAD);
+         while (cs->compute_ib.rcs->current.cdw & ib_pad_dw_mask)
+            radeon_emit(cs->compute_ib.rcs, PKT3_NOP_PAD);
       }
       break;
    case RING_UVD:
@@ -1794,17 +1796,17 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
    }
 
    /* If the CS is not empty or overflowed.... */
-   if (likely(radeon_emitted(&cs->main.base, 0) &&
-       cs->main.base.current.cdw <= cs->main.base.current.max_dw &&
+   if (likely(radeon_emitted(rcs, 0) &&
+       rcs->current.cdw <= rcs->current.max_dw &&
        !cs->noop &&
        !(flags & RADEON_FLUSH_NOOP))) {
       struct amdgpu_cs_context *cur = cs->csc;
 
       /* Set IB sizes. */
-      amdgpu_ib_finalize(ws, &cs->main);
+      amdgpu_ib_finalize(ws, rcs, &cs->main);
 
       if (cs->compute_ib.ib_mapped)
-         amdgpu_ib_finalize(ws, &cs->compute_ib);
+         amdgpu_ib_finalize(ws, cs->compute_ib.rcs, &cs->compute_ib);
 
       /* Create a fence. */
       amdgpu_fence_reference(&cur->fence, NULL);
@@ -1858,17 +1860,17 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
       amdgpu_cs_context_cleanup(cs->csc);
    }
 
-   amdgpu_get_new_ib(ws, cs, IB_MAIN);
+   amdgpu_get_new_ib(ws, rcs, &cs->main, cs);
    if (cs->compute_ib.ib_mapped)
-      amdgpu_get_new_ib(ws, cs, IB_PARALLEL_COMPUTE);
+      amdgpu_get_new_ib(ws, cs->compute_ib.rcs, &cs->compute_ib, cs);
 
    if (cs->preamble_ib_bo) {
       amdgpu_cs_add_buffer(rcs, cs->preamble_ib_bo, RADEON_USAGE_READ, 0,
                            RADEON_PRIO_IB1);
    }
 
-   cs->main.base.used_gart = 0;
-   cs->main.base.used_vram = 0;
+   rcs->used_gart = 0;
+   rcs->used_vram = 0;
 
    if (cs->ring_type == RING_GFX)
       ws->num_gfx_IBs++;
@@ -1882,14 +1884,18 @@ static void amdgpu_cs_destroy(struct radeon_cmdbuf *rcs)
 {
    struct amdgpu_cs *cs = amdgpu_cs(rcs);
 
+   if (!cs)
+      return;
+
    amdgpu_cs_sync_flush(rcs);
    util_queue_fence_destroy(&cs->flush_completed);
    p_atomic_dec(&cs->ctx->ws->num_cs);
    pb_reference(&cs->preamble_ib_bo, NULL);
    pb_reference(&cs->main.big_ib_buffer, NULL);
-   FREE(cs->main.base.prev);
+   FREE(rcs->prev);
    pb_reference(&cs->compute_ib.big_ib_buffer, NULL);
-   FREE(cs->compute_ib.base.prev);
+   if (cs->compute_ib.rcs)
+      FREE(cs->compute_ib.rcs->prev);
    amdgpu_destroy_cs_context(&cs->csc1);
    amdgpu_destroy_cs_context(&cs->csc2);
    amdgpu_fence_reference(&cs->next_fence, NULL);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
index d3dbe607445..2652ba0d50f 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
@@ -63,7 +63,7 @@ enum ib_type {
 };
 
 struct amdgpu_ib {
-   struct radeon_cmdbuf base;
+   struct radeon_cmdbuf *rcs; /* pointer to the driver-owned data */
 
    /* A buffer out of which new IBs are allocated. */
    struct pb_buffer        *big_ib_buffer;
@@ -130,7 +130,7 @@ struct amdgpu_cs_context {
 
 struct amdgpu_cs {
    struct amdgpu_ib main; /* must be first because this is inherited */
-   struct amdgpu_ib compute_ib; /* optional parallel compute IB */
+   struct amdgpu_ib compute_ib;      /* optional parallel compute IB */
    struct amdgpu_ctx *ctx;
    enum ring_type ring_type;
    struct drm_amdgpu_cs_chunk_fence fence_chunk;
@@ -210,35 +210,17 @@ static inline void amdgpu_fence_reference(struct pipe_fence_handle **dst,
 
 int amdgpu_lookup_buffer(struct amdgpu_cs_context *cs, struct amdgpu_winsys_bo *bo);
 
-static inline struct amdgpu_ib *
-amdgpu_ib(struct radeon_cmdbuf *base)
-{
-   return (struct amdgpu_ib *)base;
-}
-
 static inline struct amdgpu_cs *
-amdgpu_cs(struct radeon_cmdbuf *base)
+amdgpu_cs(struct radeon_cmdbuf *rcs)
 {
-   assert(amdgpu_ib(base)->ib_type == IB_MAIN);
-   return (struct amdgpu_cs*)base;
+   struct amdgpu_cs *cs = (struct amdgpu_cs*)rcs->priv;
+   assert(!cs || cs->main.ib_type == IB_MAIN);
+   return cs;
 }
 
 #define get_container(member_ptr, container_type, container_member) \
    (container_type *)((char *)(member_ptr) - offsetof(container_type, container_member))
 
-static inline struct amdgpu_cs *
-amdgpu_cs_from_ib(struct amdgpu_ib *ib)
-{
-   switch (ib->ib_type) {
-   case IB_MAIN:
-      return get_container(ib, struct amdgpu_cs, main);
-   case IB_PARALLEL_COMPUTE:
-      return get_container(ib, struct amdgpu_cs, compute_ib);
-   default:
-      unreachable("bad ib_type");
-   }
-}
-
 static inline bool
 amdgpu_bo_is_referenced_by_cs(struct amdgpu_cs *cs,
                               struct amdgpu_winsys_bo *bo)