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authorRob Clark <robdclark@gmail.com>2019-01-10 08:32:51 -0500
committerRob Clark <robdclark@gmail.com>2019-01-10 14:21:39 -0500
commiteb625d30b7b01db98b28a97ab6c15c9d3459fa74 (patch)
treebde5a6a461b0538464ebaa48739579f991eedcfd /src/gallium/drivers
parent04aff7e42b88fdd251617436a589ea0be2f44093 (diff)
freedreno/a6xx: separate stencil restore/resolve fixes
Previously we'd use format/etc from the primary (z32) buffer for the stencil (s8), due to confusion about rsc vs psurf. Rework this to drop extra arg and push down handling of separate stencil case (and make sure we take the fmt from the right place). This doesn't completely fix separate-stencil, but at least it avoids the GPU scribbling over random other cmdstream buffers and causing a bunch of bogus fails in dEQP. Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'src/gallium/drivers')
-rw-r--r--src/gallium/drivers/freedreno/a6xx/fd6_gmem.c35
1 files changed, 21 insertions, 14 deletions
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
index 8cda7d6ddae..75d8025e2a6 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
@@ -595,18 +595,25 @@ emit_blit(struct fd_batch *batch,
struct fd_ringbuffer *ring,
uint32_t base,
struct pipe_surface *psurf,
- struct fd_resource *rsc)
+ bool stencil)
{
struct fd_resource_slice *slice;
+ struct fd_resource *rsc = fd_resource(psurf->texture);
+ enum pipe_format pfmt = psurf->format;
uint32_t offset;
+ /* separate stencil case: */
+ if (stencil) {
+ rsc = rsc->stencil;
+ pfmt = rsc->base.format;
+ }
+
slice = fd_resource_slice(rsc, psurf->u.tex.level);
offset = fd_resource_offset(rsc, psurf->u.tex.level,
psurf->u.tex.first_layer);
debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
- enum pipe_format pfmt = psurf->format;
enum a6xx_color_fmt format = fd6_pipe2color(pfmt);
uint32_t stride = slice->pitch * rsc->cpp;
uint32_t size = slice->size0;
@@ -617,7 +624,7 @@ emit_blit(struct fd_batch *batch,
// TODO: tile mode
// bool tiled;
// tiled = rsc->tile_mode &&
- // !fd_resource_level_linear(psurf->texture, psurf->u.tex.level);
+ // !fd_resource_level_linear(&rsc->base, psurf->u.tex.level);
OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 5);
OUT_RING(ring,
@@ -640,10 +647,10 @@ emit_restore_blit(struct fd_batch *batch,
struct fd_ringbuffer *ring,
uint32_t base,
struct pipe_surface *psurf,
- struct fd_resource *rsc,
unsigned buffer)
{
uint32_t info = 0;
+ bool stencil = false;
switch (buffer) {
case FD_BUFFER_COLOR:
@@ -651,6 +658,7 @@ emit_restore_blit(struct fd_batch *batch,
break;
case FD_BUFFER_STENCIL:
info |= A6XX_RB_BLIT_INFO_UNK0;
+ stencil = true;
break;
case FD_BUFFER_DEPTH:
info |= A6XX_RB_BLIT_INFO_DEPTH | A6XX_RB_BLIT_INFO_UNK0;
@@ -663,7 +671,7 @@ emit_restore_blit(struct fd_batch *batch,
OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
OUT_RING(ring, info | A6XX_RB_BLIT_INFO_GMEM);
- emit_blit(batch, ring, base, psurf, rsc);
+ emit_blit(batch, ring, base, psurf, stencil);
}
static void
@@ -845,7 +853,6 @@ emit_restore_blits(struct fd_batch *batch, struct fd_ringbuffer *ring)
if (!(batch->restore & (PIPE_CLEAR_COLOR0 << i)))
continue;
emit_restore_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
- fd_resource(pfb->cbufs[i]->texture),
FD_BUFFER_COLOR);
}
}
@@ -854,11 +861,11 @@ emit_restore_blits(struct fd_batch *batch, struct fd_ringbuffer *ring)
struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
if (!rsc->stencil || (batch->restore & FD_BUFFER_DEPTH)) {
- emit_restore_blit(batch, ring, gmem->zsbuf_base[0], pfb->zsbuf, rsc,
+ emit_restore_blit(batch, ring, gmem->zsbuf_base[0], pfb->zsbuf,
FD_BUFFER_DEPTH);
}
if (rsc->stencil && (batch->restore & FD_BUFFER_STENCIL)) {
- emit_restore_blit(batch, ring, gmem->zsbuf_base[1], pfb->zsbuf, rsc->stencil,
+ emit_restore_blit(batch, ring, gmem->zsbuf_base[1], pfb->zsbuf,
FD_BUFFER_STENCIL);
}
}
@@ -896,12 +903,12 @@ emit_resolve_blit(struct fd_batch *batch,
struct fd_ringbuffer *ring,
uint32_t base,
struct pipe_surface *psurf,
- struct fd_resource *rsc,
unsigned buffer)
{
uint32_t info = 0;
+ bool stencil = false;
- if (!rsc->valid)
+ if (!fd_resource(psurf->texture)->valid)
return;
switch (buffer) {
@@ -909,6 +916,7 @@ emit_resolve_blit(struct fd_batch *batch,
break;
case FD_BUFFER_STENCIL:
info |= A6XX_RB_BLIT_INFO_UNK0;
+ stencil = true;
break;
case FD_BUFFER_DEPTH:
info |= A6XX_RB_BLIT_INFO_DEPTH;
@@ -921,7 +929,7 @@ emit_resolve_blit(struct fd_batch *batch,
OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
OUT_RING(ring, info);
- emit_blit(batch, ring, base, psurf, rsc);
+ emit_blit(batch, ring, base, psurf, stencil);
}
/*
@@ -967,12 +975,12 @@ prepare_tile_fini_ib(struct fd_batch *batch)
if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH)) {
emit_resolve_blit(batch, ring,
- gmem->zsbuf_base[0], pfb->zsbuf, rsc,
+ gmem->zsbuf_base[0], pfb->zsbuf,
FD_BUFFER_DEPTH);
}
if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL)) {
emit_resolve_blit(batch, ring,
- gmem->zsbuf_base[1], pfb->zsbuf, rsc->stencil,
+ gmem->zsbuf_base[1], pfb->zsbuf,
FD_BUFFER_STENCIL);
}
}
@@ -985,7 +993,6 @@ prepare_tile_fini_ib(struct fd_batch *batch)
if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
continue;
emit_resolve_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
- fd_resource(pfb->cbufs[i]->texture),
FD_BUFFER_COLOR);
}
}