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authorEric Anholt <eric@anholt.net>2019-01-04 09:17:15 -0800
committerEric Anholt <eric@anholt.net>2019-01-14 13:18:02 -0800
commit49b7e26facab793be3b36e3068e758165455e276 (patch)
tree44fd6beffd0ea3d334c7a590f8e9368f54765b77 /src/gallium/drivers/v3d/v3dx_simulator.c
parent3790ee07e6666f734dd595c4c4dd3501a741a59a (diff)
v3d: Add an isr to the simulator to catch GMP violations.
Otherwise, the simulator raises the GMP interrupt and waits for it to be handled, and v3d ends up spinning in v3d_hw_tick(). Aborting right when violation happens gives us a chance to look at the backtrace of whatever thread triggered the violation.
Diffstat (limited to 'src/gallium/drivers/v3d/v3dx_simulator.c')
-rw-r--r--src/gallium/drivers/v3d/v3dx_simulator.c33
1 files changed, 33 insertions, 0 deletions
diff --git a/src/gallium/drivers/v3d/v3dx_simulator.c b/src/gallium/drivers/v3d/v3dx_simulator.c
index 940b8f2ce32..e6db838c0de 100644
--- a/src/gallium/drivers/v3d/v3dx_simulator.c
+++ b/src/gallium/drivers/v3d/v3dx_simulator.c
@@ -157,6 +157,32 @@ v3dX(simulator_get_param_ioctl)(struct v3d_hw *v3d,
abort();
}
+static struct v3d_hw *v3d_isr_hw;
+
+static void
+v3d_isr(uint32_t hub_status)
+{
+ struct v3d_hw *v3d = v3d_isr_hw;
+
+ /* Check the per-core bits */
+ if (hub_status & (1 << 0)) {
+ uint32_t core_status = V3D_READ(V3D_CTL_0_INT_STS);
+
+ if (core_status & V3D_CTL_0_INT_STS_INT_GMPV_SET) {
+ fprintf(stderr, "GMP violation at 0x%08x\n",
+ V3D_READ(V3D_GMP_0_VIO_ADDR));
+ abort();
+ } else {
+ fprintf(stderr,
+ "Unexpected ISR with core status 0x%08x\n",
+ core_status);
+ }
+ abort();
+ }
+
+ return;
+}
+
void
v3dX(simulator_init_regs)(struct v3d_hw *v3d)
{
@@ -171,6 +197,13 @@ v3dX(simulator_init_regs)(struct v3d_hw *v3d)
*/
V3D_WRITE(V3D_CTL_0_MISCCFG, V3D_CTL_1_MISCCFG_OVRTMUOUT_SET);
#endif
+
+ uint32_t core_interrupts = V3D_CTL_0_INT_STS_INT_GMPV_SET;
+ V3D_WRITE(V3D_CTL_0_INT_MSK_SET, ~core_interrupts);
+ V3D_WRITE(V3D_CTL_0_INT_MSK_CLR, core_interrupts);
+
+ v3d_isr_hw = v3d;
+ v3d_hw_set_isr(v3d, v3d_isr);
}
void