diff options
| author | Marek Olšák <marek.olsak@amd.com> | 2016-12-25 19:48:55 +0100 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2017-01-06 21:05:48 +0100 |
| commit | 5871ebd7f104daddced9243ce0c2886ed1f816ef (patch) | |
| tree | ed293fb5936ab5778c0abf476240befd6e3b2969 /src/gallium/drivers/radeonsi | |
| parent | aac07bb79c66202f19d2d28ca6daca71a459d748 (diff) | |
radeonsi: add HUD queries for cache flush stats
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Diffstat (limited to 'src/gallium/drivers/radeonsi')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index cae19dc5a7a..b3f664eff2f 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -735,6 +735,9 @@ void si_emit_cache_flush(struct si_context *sctx) struct radeon_winsys_cs *cs = rctx->gfx.cs; uint32_t cp_coher_cntl = 0; + if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER) + sctx->b.num_fb_cache_flushes++; + /* SI has a bug that it always flushes ICACHE and KCACHE if either * bit is set. An alternative way is to write SQC_CACHES, but that * doesn't seem to work reliably. Since the bug doesn't affect @@ -852,6 +855,7 @@ void si_emit_cache_flush(struct si_context *sctx) S_0085F0_TC_ACTION_ENA(1) | S_0301F0_TC_WB_ACTION_ENA(rctx->chip_class >= VI)); cp_coher_cntl = 0; + sctx->b.num_L2_invalidates++; } else { /* L1 invalidation and L2 writeback must be done separately, * because both operations can't be done together. @@ -867,6 +871,7 @@ void si_emit_cache_flush(struct si_context *sctx) S_0301F0_TC_WB_ACTION_ENA(1) | S_0301F0_TC_NC_ACTION_ENA(1)); cp_coher_cntl = 0; + sctx->b.num_L2_writebacks++; } if (rctx->flags & SI_CONTEXT_INV_VMEM_L1) { /* Invalidate per-CU VMEM L1. */ |