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author | Marek Olšák <marek.olsak@amd.com> | 2021-03-20 00:59:50 -0400 |
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committer | Marge Bot <eric+marge@anholt.net> | 2021-04-02 12:05:00 +0000 |
commit | 4e35eb1d699ebacad14dce2ff8d9992e3c06def2 (patch) | |
tree | 52e9633daae4a9ca60e9f91aee0d54f5301565e9 /src/gallium/drivers/radeonsi/si_texture.c | |
parent | 3345e32de71fc15150233b34310430362ee33d31 (diff) |
radeonsi: set better default depth clear value
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_texture.c')
-rw-r--r-- | src/gallium/drivers/radeonsi/si_texture.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index ac244dbb840..386a5e5262d 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -918,6 +918,11 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen, tex->is_depth = util_format_has_depth(util_format_description(tex->buffer.b.b.format)); tex->surface = *surface; + /* Use 1.0 as the default clear value to get optimal ZRANGE_PRECISION if we don't + * get a fast clear. + */ + tex->depth_clear_value = 1.0; + /* On GFX8, HTILE uses different tiling depending on the TC_COMPATIBLE_HTILE * setting, so we have to enable it if we enabled it at allocation. * |