diff options
author | Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> | 2016-04-21 01:22:02 +0200 |
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committer | Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> | 2016-04-21 12:50:58 +0200 |
commit | 4d13c7c8794082400e383ac6d76eb6ba753dcb0f (patch) | |
tree | 05f2edfbb09e83f9a0faa2b458e910ea95811150 /src/gallium/drivers/radeonsi/si_hw_context.c | |
parent | f45f54e14ac54460f2785bc14fc1f9220a0a763d (diff) |
radeonsi: Enable loading into CE RAM.
We need to enable a bit in the CONTEXT_CONTROL packet for the
loads to work.
v2: Style issues.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_hw_context.c')
-rw-r--r-- | src/gallium/drivers/radeonsi/si_hw_context.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c index e3abb7f67cc..e6018f3b29d 100644 --- a/src/gallium/drivers/radeonsi/si_hw_context.c +++ b/src/gallium/drivers/radeonsi/si_hw_context.c @@ -202,6 +202,11 @@ void si_begin_new_cs(struct si_context *ctx) if (ctx->init_config_gs_rings) si_pm4_emit(ctx, ctx->init_config_gs_rings); + if (ctx->ce_preamble_ib) + si_ce_enable_loads(ctx->ce_preamble_ib); + else if (ctx->ce_ib) + si_ce_enable_loads(ctx->ce_ib); + ctx->framebuffer.dirty_cbufs = (1 << 8) - 1; ctx->framebuffer.dirty_zsbuf = true; si_mark_atom_dirty(ctx, &ctx->framebuffer.atom); |