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authorMarek Olšák <marek.olsak@amd.com>2020-01-03 23:15:27 -0500
committerMarek Olšák <marek.olsak@amd.com>2020-01-06 15:57:20 -0500
commit420fe1e7f9ef56177c8f45e98e057488a2b57646 (patch)
treeb672598dfc95bc48449817d7f87951204a7c45ab /src/gallium/drivers/radeonsi/si_get.c
parente5167a9276de1f383888714b41d3a9be2b9c1da9 (diff)
radeonsi: remove TGSI
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_get.c')
-rw-r--r--src/gallium/drivers/radeonsi/si_get.c27
1 files changed, 9 insertions, 18 deletions
diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
index c34c8649bcf..1adbafda53a 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -159,6 +159,9 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_IMAGE_LOAD_FORMATTED:
case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA:
case PIPE_CAP_TGSI_DIV:
+ case PIPE_CAP_PACKED_UNIFORMS:
+ case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
+ case PIPE_CAP_GL_SPIRV:
return 1;
case PIPE_CAP_QUERY_SO_OVERFLOW:
@@ -195,7 +198,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
if (!sscreen->info.has_indirect_compute_dispatch)
return 420;
- return sscreen->options.enable_nir ? 460 : 450;
+ return 460;
case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
/* Optimal number for good TexSubImage performance on Polaris10. */
@@ -214,15 +217,6 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return sscreen->info.has_sparse_vm_mappings ?
RADEON_SPARSE_PAGE_SIZE : 0;
- case PIPE_CAP_PACKED_UNIFORMS:
- case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
- case PIPE_CAP_GL_SPIRV:
- return sscreen->options.enable_nir;
-
- case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
- if (sscreen->options.enable_nir)
- return 0;
- return 1;
/* Unsupported features. */
case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
@@ -246,6 +240,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
+ case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
return 0;
case PIPE_CAP_FENCE_SIGNAL:
@@ -395,14 +390,14 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
int ir = 1 << PIPE_SHADER_IR_NATIVE;
if (sscreen->info.has_indirect_compute_dispatch)
- ir |= 1 << PIPE_SHADER_IR_TGSI;
+ ir |= 1 << PIPE_SHADER_IR_NIR;
return ir;
}
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
uint64_t max_const_buffer_size;
- pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
+ pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_NIR,
PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
&max_const_buffer_size);
return MIN2(max_const_buffer_size, INT_MAX);
@@ -444,13 +439,9 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
return SI_NUM_IMAGES;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
- if (sscreen->options.enable_nir)
- return 0;
- return 32;
+ return 0;
case PIPE_SHADER_CAP_PREFERRED_IR:
- if (sscreen->options.enable_nir)
- return PIPE_SHADER_IR_NIR;
- return PIPE_SHADER_IR_TGSI;
+ return PIPE_SHADER_IR_NIR;
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
return 4;