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authorMarek Olšák <marek.olsak@amd.com>2021-04-02 13:33:38 -0400
committerMarge Bot <eric+marge@anholt.net>2021-04-12 20:53:45 +0000
commit48dbdc62bf8611c60a7c27ece9b7c5ba11212e46 (patch)
treefa40116608977e275b7c2038816731f8e4a01c39 /src/gallium/drivers/radeon
parentbbda20bf292ba9c74966a311b40d92dcfe019a0b (diff)
ac/surface: change legacy_surf_level::offset to 32-bit offset_256B shifted by 8
Images are always aligned to 256B (enforced by register and descriptor fields) and limited to 40-bit addresses. This saves some space. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
Diffstat (limited to 'src/gallium/drivers/radeon')
-rw-r--r--src/gallium/drivers/radeon/radeon_uvd.c2
-rw-r--r--src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c4
-rw-r--r--src/gallium/drivers/radeon/radeon_vce_40_2_2.c4
-rw-r--r--src/gallium/drivers/radeon/radeon_vce_50.c4
-rw-r--r--src/gallium/drivers/radeon/radeon_vce_52.c4
5 files changed, 9 insertions, 9 deletions
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c
index 612cb18f34c..ec7d8b5ff19 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -1379,7 +1379,7 @@ static unsigned texture_offset(struct radeon_surf *surface, unsigned layer,
switch (type) {
default:
case RUVD_SURFACE_TYPE_LEGACY:
- return surface->u.legacy.level[0].offset +
+ return (uint64_t)surface->u.legacy.level[0].offset_256B * 256 +
layer * (uint64_t)surface->u.legacy.level[0].slice_size_dw * 4;
break;
case RUVD_SURFACE_TYPE_GFX9:
diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
index e90fecd595f..b76d2dc6a4e 100644
--- a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -898,8 +898,8 @@ static void radeon_uvd_enc_encode_params_hevc(struct radeon_uvd_encoder *enc)
RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size);
if (sscreen->info.chip_class < GFX9) {
- RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.legacy.level[0].offset);
- RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.legacy.level[0].offset);
+ RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256);
+ RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256);
} else {
RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset);
RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset);
diff --git a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
index ee7cf15e1e6..30b43536c4a 100644
--- a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
+++ b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
@@ -308,9 +308,9 @@ static void encode(struct rvce_encoder *enc)
RVCE_CS(0x00000000); // endOfSequence
RVCE_CS(0x00000000); // endOfStream
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
- enc->luma->u.legacy.level[0].offset); // inputPictureLumaAddressHi/Lo
+ (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256); // inputPictureLumaAddressHi/Lo
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
- enc->chroma->u.legacy.level[0].offset); // inputPictureChromaAddressHi/Lo
+ (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256); // inputPictureChromaAddressHi/Lo
RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch
RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
diff --git a/src/gallium/drivers/radeon/radeon_vce_50.c b/src/gallium/drivers/radeon/radeon_vce_50.c
index 591207c6f96..e75ceec5950 100644
--- a/src/gallium/drivers/radeon/radeon_vce_50.c
+++ b/src/gallium/drivers/radeon/radeon_vce_50.c
@@ -118,9 +118,9 @@ static void encode(struct rvce_encoder *enc)
RVCE_CS(0x00000000); // endOfSequence
RVCE_CS(0x00000000); // endOfStream
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
- enc->luma->u.legacy.level[0].offset); // inputPictureLumaAddressHi/Lo
+ (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256); // inputPictureLumaAddressHi/Lo
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
- enc->chroma->u.legacy.level[0].offset); // inputPictureChromaAddressHi/Lo
+ (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256); // inputPictureChromaAddressHi/Lo
RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch
RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
diff --git a/src/gallium/drivers/radeon/radeon_vce_52.c b/src/gallium/drivers/radeon/radeon_vce_52.c
index ea1ccec00b8..f70534d14be 100644
--- a/src/gallium/drivers/radeon/radeon_vce_52.c
+++ b/src/gallium/drivers/radeon/radeon_vce_52.c
@@ -263,9 +263,9 @@ static void encode(struct rvce_encoder *enc)
if (sscreen->info.chip_class < GFX9) {
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
- enc->luma->u.legacy.level[0].offset); // inputPictureLumaAddressHi/Lo
+ (uint64_t)enc->luma->u.legacy.level[0].offset_256B * 256); // inputPictureLumaAddressHi/Lo
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
- enc->chroma->u.legacy.level[0].offset); // inputPictureChromaAddressHi/Lo
+ (uint64_t)enc->chroma->u.legacy.level[0].offset_256B * 256); // inputPictureChromaAddressHi/Lo
RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch
RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch