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authorMarek Olšák <marek.olsak@amd.com>2021-04-02 13:33:38 -0400
committerMarge Bot <eric+marge@anholt.net>2021-04-12 20:53:45 +0000
commit48dbdc62bf8611c60a7c27ece9b7c5ba11212e46 (patch)
treefa40116608977e275b7c2038816731f8e4a01c39 /src/gallium/drivers/r600/radeon_uvd.c
parentbbda20bf292ba9c74966a311b40d92dcfe019a0b (diff)
ac/surface: change legacy_surf_level::offset to 32-bit offset_256B shifted by 8
Images are always aligned to 256B (enforced by register and descriptor fields) and limited to 40-bit addresses. This saves some space. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
Diffstat (limited to 'src/gallium/drivers/r600/radeon_uvd.c')
-rw-r--r--src/gallium/drivers/r600/radeon_uvd.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/r600/radeon_uvd.c b/src/gallium/drivers/r600/radeon_uvd.c
index 4d0e0bf83c3..fa22ba586ae 100644
--- a/src/gallium/drivers/r600/radeon_uvd.c
+++ b/src/gallium/drivers/r600/radeon_uvd.c
@@ -1170,7 +1170,7 @@ error:
/* calculate top/bottom offset */
static unsigned texture_offset(struct radeon_surf *surface, unsigned layer)
{
- return surface->u.legacy.level[0].offset +
+ return (uint64_t)surface->u.legacy.level[0].offset_256B * 256 +
layer * (uint64_t)surface->u.legacy.level[0].slice_size_dw * 4;
}