diff options
author | Marek Olšák <marek.olsak@amd.com> | 2017-06-06 23:54:23 +0200 |
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committer | Marek Olšák <marek.olsak@amd.com> | 2017-06-08 23:29:07 +0200 |
commit | 69403617963681ed48fa937e978919b855aa4049 (patch) | |
tree | 53adc06ea5548244e06dd29432b1a23f1e16e6a5 /src/gallium/drivers/r600/r600_blit.c | |
parent | c6451b12096fb4258051b9b38c50ffb0a86df173 (diff) |
gallium/radeon: don't allocate HTILE in a separate buffer
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Diffstat (limited to 'src/gallium/drivers/r600/r600_blit.c')
-rw-r--r-- | src/gallium/drivers/r600/r600_blit.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c index 80aa9c05769..79505d501d0 100644 --- a/src/gallium/drivers/r600/r600_blit.c +++ b/src/gallium/drivers/r600/r600_blit.c @@ -444,7 +444,7 @@ static void r600_clear(struct pipe_context *ctx, unsigned buffers, * disable fast clear for texture array. */ /* Only use htile for first level */ - if (rtex->htile_buffer && !level && + if (rtex->htile_offset && !level && fb->zsbuf->u.tex.first_layer == 0 && fb->zsbuf->u.tex.last_layer == util_max_layer(&rtex->resource.b.b, level)) { if (rtex->depth_clear_value != depth) { |