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authorGrazvydas Ignotas <notasas@gmail.com>2015-12-22 04:12:07 +0200
committerNicolai Hähnle <nicolai.haehnle@amd.com>2015-12-29 09:05:55 -0500
commitda0e216e069bd064199ed04b52de6fb23d810806 (patch)
tree2512f42acc3d6e68aa394774bab1fd432cf2c4af /src/gallium/drivers/r600/evergreen_state.c
parentdfce9759abbc13f7f735ac4bf3f1a19737624ae6 (diff)
r600: fix constant buffer size programming
When buffer size is less than 16, zero ends up being programmed as size, which prevents the hardware from fetching the correct values. Fix it by combining shift and align so that the value is always rounded up. Cc: "11.1 11.0 10.6" <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92229 Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Diffstat (limited to 'src/gallium/drivers/r600/evergreen_state.c')
-rw-r--r--src/gallium/drivers/r600/evergreen_state.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 1443bc0c4af..1aee7dd2da8 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1956,7 +1956,7 @@ static void evergreen_emit_constant_buffers(struct r600_context *rctx,
if (!gs_ring_buffer) {
radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4,
- ALIGN_DIVUP(cb->buffer_size >> 4, 16), pkt_flags);
+ ALIGN_DIVUP(cb->buffer_size, 256), pkt_flags);
radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8,
pkt_flags);
}