nv50/ir: remove symbol table support for compute shaders

The initial plan was to use this for OpenCL kernels, but back then the
plan was to convert from LLVM to TGSI. As it turns out, we didn't went
that way.

Right now for OpenCL we don't reqiure supporting multiple entry points
inside the same binary and if we want to support it later, we can add
this back.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4264>

5 files changed, 4 insertions, 32 deletions

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
index af5c6f7e690..62ff39172fc 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
@@ -437,7 +437,7 @@ nvc0_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
    nvc0_compute_upload_input(nvc0, info);
 
    BEGIN_NVC0(push, NVC0_CP(CP_START_ID), 1);
-   PUSH_DATA (push, nvc0_program_symbol_offset(cp, info->pc));
+   PUSH_DATA (push, cp->code_base);
 
    BEGIN_NVC0(push, NVC0_CP(LOCAL_POS_ALLOC), 3);
    PUSH_DATA (push, (cp->hdr[1] & 0xfffff0) + align(cp->cp.lmem_size, 0x10));
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
index e2697d76b13..d3d6bd2e5dd 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
@@ -326,8 +326,6 @@ bool nvc0_program_translate(struct nvc0_program *, uint16_t chipset,
 bool nvc0_program_upload(struct nvc0_context *, struct nvc0_program *);
 void nvc0_program_destroy(struct nvc0_context *, struct nvc0_program *);
 void nvc0_program_library_upload(struct nvc0_context *);
-uint32_t nvc0_program_symbol_offset(const struct nvc0_program *,
-                                    uint32_t label);
 void nvc0_program_init_tcp_empty(struct nvc0_context *);
 
 /* nvc0_shader_state.c */
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index d2b2de47c8d..59fa2359cb4 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -638,8 +638,6 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
       NOUVEAU_ERR("shader translation failed: %i\n", ret);
       goto out;
    }
-   if (prog->type != PIPE_SHADER_COMPUTE)
-      FREE(info->bin.syms);
 
    prog->code = info->bin.code;
    prog->code_size = info->bin.codeSize;
@@ -676,8 +674,6 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
       ret = nvc0_fp_gen_header(prog, info);
       break;
    case PIPE_SHADER_COMPUTE:
-      prog->cp.syms = info->bin.syms;
-      prog->cp.num_syms = info->bin.numSyms;
       break;
    default:
       ret = -1;
@@ -956,8 +952,6 @@ nvc0_program_destroy(struct nvc0_context *nvc0, struct nvc0_program *prog)
    FREE(prog->code); /* may be 0 for hardcoded shaders */
    FREE(prog->relocs);
    FREE(prog->fixups);
-   if (prog->type == PIPE_SHADER_COMPUTE && prog->cp.syms)
-      FREE(prog->cp.syms);
    if (prog->tfb) {
       if (nvc0->state.tfb == prog->tfb)
          nvc0->state.tfb = NULL;
@@ -970,21 +964,6 @@ nvc0_program_destroy(struct nvc0_context *nvc0, struct nvc0_program *prog)
    prog->type = type;
 }
 
-uint32_t
-nvc0_program_symbol_offset(const struct nvc0_program *prog, uint32_t label)
-{
-   const struct nv50_ir_prog_symbol *syms =
-      (const struct nv50_ir_prog_symbol *)prog->cp.syms;
-   unsigned base = 0;
-   unsigned i;
-   if (prog->type != PIPE_SHADER_COMPUTE)
-      base = GF100_SHADER_HEADER_SIZE;
-   for (i = 0; i < prog->cp.num_syms; ++i)
-      if (syms[i].label == label)
-         return prog->code_base + base + syms[i].offset;
-   return prog->code_base; /* no symbols or symbol not found */
-}
-
 void
 nvc0_program_init_tcp_empty(struct nvc0_context *nvc0)
 {
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.h b/src/gallium/drivers/nouveau/nvc0/nvc0_program.h
index 2c465b342e9..8f209d75ca1 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.h
@@ -61,8 +61,6 @@ struct nvc0_program {
    struct {
       uint32_t lmem_size; /* local memory (TGSI PRIVATE resource) size */
       uint32_t smem_size; /* shared memory (TGSI LOCAL resource) size */
-      void *syms;
-      unsigned num_syms;
    } cp;
    uint8_t num_barriers;
 
diff --git a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
index 8994be65ce4..549205e4565 100644
--- a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
+++ b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
@@ -638,8 +638,7 @@ nve4_compute_setup_launch_desc(struct nvc0_context *nvc0, uint32_t *qmd,
    NVA0C0_QMDV00_06_DEF_SET(qmd, API_VISIBLE_CALL_LIMIT, NO_CHECK);
    NVA0C0_QMDV00_06_VAL_SET(qmd, SASS_VERSION, 0x30);
 
-   NVA0C0_QMDV00_06_VAL_SET(qmd, PROGRAM_OFFSET,
-                                 nvc0_program_symbol_offset(cp, info->pc));
+   NVA0C0_QMDV00_06_VAL_SET(qmd, PROGRAM_OFFSET, cp->code_base);
 
    NVA0C0_QMDV00_06_VAL_SET(qmd, CTA_RASTER_WIDTH, info->grid[0]);
    NVA0C0_QMDV00_06_VAL_SET(qmd, CTA_RASTER_HEIGHT, info->grid[1]);
@@ -699,8 +698,7 @@ gp100_compute_setup_launch_desc(struct nvc0_context *nvc0, uint32_t *qmd,
    NVC0C0_QMDV02_01_DEF_SET(qmd, CWD_MEMBAR_TYPE, L1_SYSMEMBAR);
    NVC0C0_QMDV02_01_DEF_SET(qmd, API_VISIBLE_CALL_LIMIT, NO_CHECK);
 
-   NVC0C0_QMDV02_01_VAL_SET(qmd, PROGRAM_OFFSET,
-                                 nvc0_program_symbol_offset(cp, info->pc));
+   NVC0C0_QMDV02_01_VAL_SET(qmd, PROGRAM_OFFSET, cp->code_base);
 
    NVC0C0_QMDV02_01_VAL_SET(qmd, CTA_RASTER_WIDTH, info->grid[0]);
    NVC0C0_QMDV02_01_VAL_SET(qmd, CTA_RASTER_HEIGHT, info->grid[1]);
@@ -754,8 +752,7 @@ gv100_compute_setup_launch_desc(struct nvc0_context *nvc0, u32 *qmd,
 {
    struct nvc0_program *cp = nvc0->compprog;
    struct nvc0_screen *screen = nvc0->screen;
-   uint64_t entry =
-      screen->text->offset + nvc0_program_symbol_offset(cp, info->pc);
+   uint64_t entry = screen->text->offset + cp->code_base;
 
    NVC3C0_QMDV02_02_VAL_SET(qmd, SM_GLOBAL_CACHING_ENABLE, 1);
    NVC3C0_QMDV02_02_DEF_SET(qmd, API_VISIBLE_CALL_LIMIT, NO_CHECK);