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authorIlia Mirkin <imirkin@alum.mit.edu>2017-01-12 21:06:40 -0500
committerIlia Mirkin <imirkin@alum.mit.edu>2017-01-12 21:08:42 -0500
commitf897036978b42619ce27ea4f41886cc0002f33ef (patch)
tree8543c97fb8ad64477689c3c1d478b59cfbe5b3e5 /src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
parenteb60a89bc3ac2b43faf52d06e05670bbbca7292d (diff)
nvc0/ir: only try to check for zero LOD if we aren't already forcing it
There's a levelZero flag which forces texturing to pick level zero (and not consume an explicit LOD argument). This is set for MS targets, but could also be set for any other incoming instruction. As that is what determines whether a LOD argument is present, check that rather than the more indirect isMS logic. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Diffstat (limited to 'src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp')
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index ff253af6997..95de87c03b3 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -118,7 +118,7 @@ NVC0LegalizeSSA::handleFTZ(Instruction *i)
void
NVC0LegalizeSSA::handleTEXLOD(TexInstruction *i)
{
- if (i->tex.target.isMS())
+ if (i->tex.levelZero)
return;
ImmediateValue lod;