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authorIlia Mirkin <imirkin@alum.mit.edu>2017-05-20 03:11:12 -0400
committerIlia Mirkin <imirkin@alum.mit.edu>2017-05-20 03:12:40 -0400
commit82e77d4e4484b5d4f6a7b4751a17c882e6d2ad69 (patch)
tree9606d41e8546593fde9ba2f4e438798c6b6d1dc1 /src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
parentf0051fcf2beb2c1476c31dfb0ba40111792e4ec7 (diff)
nvc0/ir: SHLADD's middle source must be an immediate
The instruction encodings only allow for immediates. Don't try to replace a zero (which is dumb to have in that op in any case) with RZ. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: mesa-stable@lists.freedesktop.org
Diffstat (limited to 'src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp')
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 732e1a93b42..64d743708a6 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -642,6 +642,8 @@ NVC0LegalizePostRA::replaceZero(Instruction *i)
for (int s = 0; i->srcExists(s); ++s) {
if (s == 2 && i->op == OP_SUCLAMP)
continue;
+ if (s == 1 && i->op == OP_SHLADD)
+ continue;
ImmediateValue *imm = i->getSrc(s)->asImm();
if (imm) {
if (i->op == OP_SELP && s == 2) {