path: root/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
diff options
authorIlia Mirkin <>2019-02-03 10:06:24 -0500
committerIlia Mirkin <>2019-02-06 19:35:57 -0500
commit4443b6ddf2e08d06f3d0457cf20a2e04244cde37 (patch)
tree5426c74cbf8912315a8e809c3046b16d71df3dc4 /src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
parent399215eb7a0517463e5757c598d6cff6ae2301d0 (diff)
nvc0/ir: always use CG mode for loads from atomic-only buffers
Atomic operations don't update the local cache, which means that we would have to issue CCTL operations in order to get the updated values. When we know that a buffer is primarily used for atomic operations, it's easier to just avoid the caching at that level entirely. The same issue persists for non-atomic buffers, which will have to be fixed separately. Fixes the failing dEQP-GLES31.functional.atomic_counter.* tests. Signed-off-by: Ilia Mirkin <> Reviewed-by: Karol Herbst <> Cc: 19.0 <>
Diffstat (limited to 'src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp')
0 files changed, 0 insertions, 0 deletions