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authorKarol Herbst <kherbst@redhat.com>2019-10-24 02:50:51 +0200
committerKarol Herbst <karolherbst@gmail.com>2019-12-11 23:54:39 +0000
commit20d0ae464c4accd97227b1b4e805a9c10183647d (patch)
tree18fa08b692d6144128b5d3576161da9f0e78e28d /src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
parent70c6bff2f01620bf10258067b6e2ef4ac0959f53 (diff)
nv50/ir: implement global atomics and handle it for nir
TGSI doesn't have any concept of global memory right now. Signed-off-by: Karol Herbst <kherbst@redhat.com> Acked-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp')
-rw-r--r--src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index a76d6c60cda..a60881000fe 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -1645,6 +1645,8 @@ NVC0LoweringPass::handleATOM(Instruction *atom)
else if (targ->getChipset() < NVISA_GM107_CHIPSET)
handleSharedATOMNVE4(atom);
return true;
+ case FILE_MEMORY_GLOBAL:
+ return true;
default:
assert(atom->src(0).getFile() == FILE_MEMORY_BUFFER);
base = loadBufInfo64(ind, atom->getSrc(0)->reg.fileIndex * 16);