diff options
| author | Ilia Mirkin <imirkin@alum.mit.edu> | 2014-09-25 03:51:37 -0400 |
|---|---|---|
| committer | Ilia Mirkin <imirkin@alum.mit.edu> | 2014-09-25 22:15:50 -0400 |
| commit | 0532a5fd00cdddda0fd1727fb519cb4312f47e83 (patch) | |
| tree | 6d9187cd5c44db422d53f950fc1b0a95cc3cf47f /src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | |
| parent | d3c3bba6d07c97cfc1499a6bda73337584943971 (diff) | |
gm107/ir: fix texture argument order
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
Diffstat (limited to 'src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp')
| -rw-r--r-- | src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 32 |
1 files changed, 27 insertions, 5 deletions
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index 29857cffe6e..9c06d0477d2 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp @@ -601,6 +601,21 @@ NVC0LoweringPass::handleTEX(TexInstruction *i) // lod bias // depth compare // offsets (same as fermi, except txd which takes it with array) + // + // Maxwell (tex): + // array + // coords + // indirect handle + // sample + // lod bias + // depth compare + // offsets + // + // Maxwell (txd): + // indirect handle + // coords + // array + offsets + // derivatives if (chipset >= NVISA_GK104_CHIPSET) { if (i->tex.rIndirectSrc >= 0 || i->tex.sIndirectSrc >= 0) { @@ -634,12 +649,17 @@ NVC0LoweringPass::handleTEX(TexInstruction *i) const int sat = (i->op == OP_TXF) ? 1 : 0; DataType sTy = (i->op == OP_TXF) ? TYPE_U32 : TYPE_F32; bld.mkCvt(OP_CVT, TYPE_U16, layer, sTy, src)->saturate = sat; - for (int s = dim; s >= 1; --s) - i->setSrc(s, i->getSrc(s - 1)); - i->setSrc(0, layer); + if (i->op != OP_TXD || chipset < NVISA_GM107_CHIPSET) { + for (int s = dim; s >= 1; --s) + i->setSrc(s, i->getSrc(s - 1)); + i->setSrc(0, layer); + } else { + i->setSrc(dim, layer); + } } // Move the indirect reference to the first place - if (i->tex.rIndirectSrc >= 0) { + if (i->tex.rIndirectSrc >= 0 && ( + i->op == OP_TXD || chipset < NVISA_GM107_CHIPSET)) { Value *hnd = i->getIndirectR(); i->setIndirectR(NULL); @@ -742,8 +762,10 @@ NVC0LoweringPass::handleTEX(TexInstruction *i) // create it if it's not already there, and INSBF it if it already // is. s = (i->tex.rIndirectSrc >= 0) ? 1 : 0; + if (chipset >= NVISA_GM107_CHIPSET) + s += dim; if (i->tex.target.isArray()) { - bld.mkOp3(OP_INSBF, TYPE_U32, i->getSrc(0), + bld.mkOp3(OP_INSBF, TYPE_U32, i->getSrc(s), bld.loadImm(NULL, imm), bld.mkImm(0xc10), i->getSrc(s)); } else { |