summaryrefslogtreecommitdiff
path: root/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
diff options
context:
space:
mode:
authorMarek Olšák <marek.olsak@amd.com>2020-10-07 07:41:41 -0400
committerMarge Bot <eric+marge@anholt.net>2020-10-30 05:07:57 +0000
commit5957b0c162290e444d9e57dbed07047c421e7148 (patch)
tree3d7024966c82f81643e3a8563e16537cf8a71648 /src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
parentd8ea50996580a34b17059ec5456c75bb0d1f8750 (diff)
glthread: pin driver threads to the same L3 as the main thread regularlyHEADmaster
This improves performance on my Ryzen 3900X, which has 4 L3 caches and 6 threads per L3. The best improvement is 33% if the kernel CPU scheduler doesn't move the main thread too often. v2: pin only once in 128 batch flushes Acked-by: Jose Fonseca <jfonseca@vmware.com> Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7054>
Diffstat (limited to 'src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp')
0 files changed, 0 insertions, 0 deletions