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authorRob Clark <robdclark@gmail.com>2018-12-05 10:51:16 -0500
committerRob Clark <robdclark@gmail.com>2018-12-07 13:49:21 -0500
commit5c2c1f0a2d5cec771b6cbfadf43f44a632ff57fc (patch)
tree8e5ff7e1c8cce27bdad6fded08494c746cda3f18 /src/gallium/drivers/freedreno
parent9517037bdcd997fbffc0b5b07eede0e6a114ece3 (diff)
freedreno/ir3: track max flow control depth for a5xx/a6xx
Rather than just hard-coding BRANCHSTACK size. Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'src/gallium/drivers/freedreno')
-rw-r--r--src/gallium/drivers/freedreno/a5xx/fd5_program.c4
-rw-r--r--src/gallium/drivers/freedreno/a6xx/fd6_program.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_program.c b/src/gallium/drivers/freedreno/a5xx/fd5_program.c
index 97a84b01c0a..9c54244457f 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_program.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_program.c
@@ -443,7 +443,7 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_RING(ring, A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s[VS].i->max_half_reg + 1) |
A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
0x6 | /* XXX seems to be always set? */
- A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
+ A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(s[VS].v->branchstack) |
COND(s[VS].v->num_samp > 0, A5XX_SP_VS_CTRL_REG0_PIXLODENABLE));
struct ir3_shader_linkage l = {0};
@@ -567,7 +567,7 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
A5XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
- A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
+ A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(s[FS].v->branchstack) |
COND(s[FS].v->num_samp > 0, A5XX_SP_FS_CTRL_REG0_PIXLODENABLE));
OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
index 71dadef97e2..add2d28b866 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
@@ -402,7 +402,7 @@ setup_stateobj(struct fd_ringbuffer *ring,
OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz) |
A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
- A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
+ A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(s[VS].v->branchstack) |
COND(s[VS].v->num_samp > 0, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
struct ir3_shader_linkage l = {0};
@@ -524,7 +524,7 @@ setup_stateobj(struct fd_ringbuffer *ring,
0x1000000 |
A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
- A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
+ A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(s[FS].v->branchstack) |
COND(s[FS].v->num_samp > 0, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);