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authorIlia Mirkin <imirkin@alum.mit.edu>2014-04-25 01:43:05 -0400
committerIlia Mirkin <imirkin@alum.mit.edu>2014-04-28 19:04:46 -0400
commita52eaba78737fd6473490ee8fe6a8415cd52ef98 (patch)
tree2184708689b714ad0650d993c2e68a8ecb5d3e8e /src/gallium/auxiliary
parentb125c92aa9837c80d1b7e26554d0b66b4db3f2e1 (diff)
gallium: add new opcodes for ARB_gs5 bit manipulation support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Diffstat (limited to 'src/gallium/auxiliary')
-rw-r--r--src/gallium/auxiliary/tgsi/tgsi_info.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c b/src/gallium/auxiliary/tgsi/tgsi_info.c
index 5bcc3c918d3..d03a92065f2 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
@@ -223,6 +223,14 @@ static const struct tgsi_opcode_info opcode_info[TGSI_OPCODE_LAST] =
{ 1, 2, 0, 0, 0, 0, COMP, "UMUL_HI", TGSI_OPCODE_UMUL_HI },
{ 1, 3, 1, 0, 0, 0, OTHR, "TG4", TGSI_OPCODE_TG4 },
{ 1, 2, 1, 0, 0, 0, OTHR, "LODQ", TGSI_OPCODE_LODQ },
+ { 1, 3, 0, 0, 0, 0, COMP, "IBFE", TGSI_OPCODE_IBFE },
+ { 1, 3, 0, 0, 0, 0, COMP, "UBFE", TGSI_OPCODE_UBFE },
+ { 1, 4, 0, 0, 0, 0, COMP, "BFI", TGSI_OPCODE_BFI },
+ { 1, 1, 0, 0, 0, 0, COMP, "BREV", TGSI_OPCODE_BREV },
+ { 1, 1, 0, 0, 0, 0, COMP, "POPC", TGSI_OPCODE_POPC },
+ { 1, 1, 0, 0, 0, 0, COMP, "LSB", TGSI_OPCODE_LSB },
+ { 1, 1, 0, 0, 0, 0, COMP, "IMSB", TGSI_OPCODE_IMSB },
+ { 1, 1, 0, 0, 0, 0, COMP, "UMSB", TGSI_OPCODE_UMSB },
};
const struct tgsi_opcode_info *