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authorMarek Olšák <marek.olsak@amd.com>2014-07-26 00:48:48 +0200
committerMarek Olšák <marek.olsak@amd.com>2014-07-28 23:57:08 +0200
commit9b046474c95f15338d4c748df9b62871bba6f36f (patch)
treebab9187ca0708787adacf908b30b68dfeb4ff7fe /src/gallium
parentecbd3a545a3cb5f2c112ae0b02abfcbb3240ec6f (diff)
radeonsi: fix CMASK and HTILE calculations for Hawaii
This fixes the checkerboard pattern in glxgears and anything that triggers fast color clear. num_channels is always <= 8, but Hawaii has 16 pipes. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'src/gallium')
-rw-r--r--src/gallium/drivers/radeon/r600_texture.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 34ecfabfc51..ac9f6808b3e 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -388,7 +388,7 @@ static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
struct r600_cmask_info *out)
{
unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
- unsigned num_pipes = rscreen->tiling_info.num_channels;
+ unsigned num_pipes = rscreen->info.r600_num_tile_pipes;
unsigned cl_width, cl_height;
switch (num_pipes) {
@@ -485,7 +485,7 @@ static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen,
{
unsigned cl_width, cl_height, width, height;
unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
- unsigned num_pipes = rscreen->tiling_info.num_channels;
+ unsigned num_pipes = rscreen->info.r600_num_tile_pipes;
/* HTILE is broken with 1D tiling on old kernels and CIK. */
if (rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&