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authorDanylo Piliaiev <dpiliaiev@igalia.com>2021-12-07 15:15:23 +0200
committerMarge Bot <emma+marge@anholt.net>2022-01-07 15:29:23 +0000
commit57c3e07f96d3a8f6483f680b67aa54755b38f00f (patch)
treebc32ccb0848b90e9419c1e6d0c766a199ca474b7 /src/freedreno/ir3/ir3.c
parenta40f004ecf2cc03aa839783e2dd7628638083986 (diff)
ir3: Be able to reduce register limit for RA when CS has barriers
If barriers are used, it must be possible for all waves in the workgroup to execute concurrently. Thus we may have to reduce the registers limit. Fixes a hang in "Digital Combat Simulator". Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14110>
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