diff options
| author | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2022-01-13 08:51:20 +0100 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2022-01-13 12:57:39 +0000 |
| commit | 49c1b40290c0226a8aecf0e59c838d70a5c0ef0f (patch) | |
| tree | d2f46a4f22ce02da94f888ec8eda53d07f6ce4c5 /src/amd/vulkan | |
| parent | fd2fbc558b8e9c6ffdfbd90473e5b77e20f771e7 (diff) | |
radv: only clear VRS_HTILE_ENCODING on GFX10.3+
On older chips like GFX9, bit 19 is RB_ALIGNED.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5859
Fixes: 9c746157ae4 ("radv: reset VRS if the current subpass doesn't have a VRS attachment")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14530>
Diffstat (limited to 'src/amd/vulkan')
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 82b526a7898..6fab43d0d83 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1930,7 +1930,8 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_buffer_ db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1); } - if (!cmd_buffer->state.subpass->vrs_attachment) { + if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10_3 && + !cmd_buffer->state.subpass->vrs_attachment) { db_htile_surface &= C_028ABC_VRS_HTILE_ENCODING; } |