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authorRhys Perry <pendingchaos02@gmail.com>2019-11-04 17:45:59 +0000
committerRhys Perry <pendingchaos02@gmail.com>2019-11-25 13:59:11 +0000
commitb3a3e4d1d27d9df6b020489cf5aa00affdfbe107 (patch)
treef2bfe7e9588d217d8c9b23b710941af237d4dd96 /src/amd/vulkan/radv_meta_buffer.c
parentc14f823ee5e109a0051225a24685e3fa015abb49 (diff)
radv: set alignment for load_ssbo/store_ssbo in meta shaders
Otherwise, nir_intrinsic_align() will assert when called on the intrinsics Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Diffstat (limited to 'src/amd/vulkan/radv_meta_buffer.c')
-rw-r--r--src/amd/vulkan/radv_meta_buffer.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_meta_buffer.c b/src/amd/vulkan/radv_meta_buffer.c
index c457ac4e5f2..28343ebd83a 100644
--- a/src/amd/vulkan/radv_meta_buffer.c
+++ b/src/amd/vulkan/radv_meta_buffer.c
@@ -52,6 +52,7 @@ build_buffer_fill_shader(struct radv_device *dev)
store->src[2] = nir_src_for_ssa(offset);
nir_intrinsic_set_write_mask(store, 0xf);
nir_intrinsic_set_access(store, ACCESS_NON_READABLE);
+ nir_intrinsic_set_align(store, 16, 0);
store->num_components = 4;
nir_builder_instr_insert(&b, &store->instr);
@@ -104,6 +105,7 @@ build_buffer_copy_shader(struct radv_device *dev)
load->src[1] = nir_src_for_ssa(offset);
nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
load->num_components = 4;
+ nir_intrinsic_set_align(load, 16, 0);
nir_builder_instr_insert(&b, &load->instr);
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
@@ -112,6 +114,7 @@ build_buffer_copy_shader(struct radv_device *dev)
store->src[2] = nir_src_for_ssa(offset);
nir_intrinsic_set_write_mask(store, 0xf);
nir_intrinsic_set_access(store, ACCESS_NON_READABLE);
+ nir_intrinsic_set_align(store, 16, 0);
store->num_components = 4;
nir_builder_instr_insert(&b, &store->instr);