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| author | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2019-06-25 17:57:45 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <samuel.pitoiset@gmail.com> | 2019-06-25 18:38:37 +0200 |
| commit | 8ea7ee153649ac07c8418cc0d4aa5a4e123d19d1 (patch) | |
| tree | 05b4740f8d00e8de9c3d9b0ff0c896dab358b6dd /src/amd/vulkan/radv_meta_buffer.c | |
| parent | 5411f470564f6f1c2a55d037103f051cbddd5623 (diff) | |
radv: rename and re-document cache flush flags
SMEM and VMEM caches are L0 on gfx10. Ported from RadeonSI.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Diffstat (limited to 'src/amd/vulkan/radv_meta_buffer.c')
| -rw-r--r-- | src/amd/vulkan/radv_meta_buffer.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/amd/vulkan/radv_meta_buffer.c b/src/amd/vulkan/radv_meta_buffer.c index c19bf0da1c3..c457ac4e5f2 100644 --- a/src/amd/vulkan/radv_meta_buffer.c +++ b/src/amd/vulkan/radv_meta_buffer.c @@ -415,8 +415,8 @@ uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer, if (size >= RADV_BUFFER_OPS_CS_THRESHOLD) { fill_buffer_shader(cmd_buffer, bo, offset, size, value); flush_bits = RADV_CMD_FLAG_CS_PARTIAL_FLUSH | - RADV_CMD_FLAG_INV_VMEM_L1 | - RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2; + RADV_CMD_FLAG_INV_VCACHE | + RADV_CMD_FLAG_WB_L2; } else if (size) { uint64_t va = radv_buffer_get_va(bo); va += offset; |