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authorSamuel Pitoiset <samuel.pitoiset@gmail.com>2020-06-02 17:29:14 +0200
committerMarge Bot <eric+marge@anholt.net>2020-09-21 15:37:11 +0000
commit3808fa40b4e89e1f3c90ae05f2b44142f4cb23ed (patch)
tree1652dfb6fef1c975d5b5807f2a7412e0d00e8055 /src/amd/vulkan/radv_meta_buffer.c
parent0836e90418e11371a49f6c1004a8039a44392ea7 (diff)
radv: add a helper for loading meta descriptors
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6202>
Diffstat (limited to 'src/amd/vulkan/radv_meta_buffer.c')
-rw-r--r--src/amd/vulkan/radv_meta_buffer.c34
1 files changed, 6 insertions, 28 deletions
diff --git a/src/amd/vulkan/radv_meta_buffer.c b/src/amd/vulkan/radv_meta_buffer.c
index e27cae1e61b..51c24d9e052 100644
--- a/src/amd/vulkan/radv_meta_buffer.c
+++ b/src/amd/vulkan/radv_meta_buffer.c
@@ -27,14 +27,7 @@ build_buffer_fill_shader(struct radv_device *dev)
nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16));
offset = nir_channel(&b, offset, 0);
- nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
- nir_intrinsic_vulkan_resource_index);
- dst_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
- dst_buf->num_components = 1;
- nir_intrinsic_set_desc_set(dst_buf, 0);
- nir_intrinsic_set_binding(dst_buf, 0);
- nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, dst_buf->num_components, 32, NULL);
- nir_builder_instr_insert(&b, &dst_buf->instr);
+ nir_ssa_def *dst_buf = radv_meta_load_descriptor(&b, 0, 0);
nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(load, 0);
@@ -48,7 +41,7 @@ build_buffer_fill_shader(struct radv_device *dev)
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
store->src[0] = nir_src_for_ssa(swizzled_load);
- store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
+ store->src[1] = nir_src_for_ssa(dst_buf);
store->src[2] = nir_src_for_ssa(offset);
nir_intrinsic_set_write_mask(store, 0xf);
nir_intrinsic_set_access(store, ACCESS_NON_READABLE);
@@ -82,26 +75,11 @@ build_buffer_copy_shader(struct radv_device *dev)
nir_ssa_def *offset = nir_imul(&b, global_id, nir_imm_int(&b, 16));
offset = nir_channel(&b, offset, 0);
- nir_intrinsic_instr *dst_buf = nir_intrinsic_instr_create(b.shader,
- nir_intrinsic_vulkan_resource_index);
- dst_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
- dst_buf->num_components = 1;
- nir_intrinsic_set_desc_set(dst_buf, 0);
- nir_intrinsic_set_binding(dst_buf, 0);
- nir_ssa_dest_init(&dst_buf->instr, &dst_buf->dest, dst_buf->num_components, 32, NULL);
- nir_builder_instr_insert(&b, &dst_buf->instr);
-
- nir_intrinsic_instr *src_buf = nir_intrinsic_instr_create(b.shader,
- nir_intrinsic_vulkan_resource_index);
- src_buf->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
- src_buf->num_components = 1;
- nir_intrinsic_set_desc_set(src_buf, 0);
- nir_intrinsic_set_binding(src_buf, 1);
- nir_ssa_dest_init(&src_buf->instr, &src_buf->dest, src_buf->num_components, 32, NULL);
- nir_builder_instr_insert(&b, &src_buf->instr);
+ nir_ssa_def *dst_buf = radv_meta_load_descriptor(&b, 0, 0);
+ nir_ssa_def *src_buf = radv_meta_load_descriptor(&b, 0, 1);
nir_intrinsic_instr *load = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_ssbo);
- load->src[0] = nir_src_for_ssa(&src_buf->dest.ssa);
+ load->src[0] = nir_src_for_ssa(src_buf);
load->src[1] = nir_src_for_ssa(offset);
nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
load->num_components = 4;
@@ -110,7 +88,7 @@ build_buffer_copy_shader(struct radv_device *dev)
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo);
store->src[0] = nir_src_for_ssa(&load->dest.ssa);
- store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa);
+ store->src[1] = nir_src_for_ssa(dst_buf);
store->src[2] = nir_src_for_ssa(offset);
nir_intrinsic_set_write_mask(store, 0xf);
nir_intrinsic_set_access(store, ACCESS_NON_READABLE);